Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	167375	1			T80	700		T81	32		T82	97
values[2]	5349	1			T80	10		T81	4		T430	3
values[3]	2761	1			T396	1		T489	1		T515	1
values[4]	1964	1			T396	1		T492	33		T400	30
values[5]	1699	1			T396	1		T492	30		T400	25
values[6]	1468	1			T396	1		T492	41		T400	20
values[7]	1025	1			T396	1		T492	57		T400	30
values[8]	834	1			T396	1		T492	71		T400	22
values[9]	675	1			T396	1		T492	45		T400	32
values[10]	631	1			T396	1		T492	40		T400	27
values[11]	608	1			T396	1		T492	56		T400	20
values[12]	568	1			T396	1		T492	51		T400	10
values[13]	509	1			T396	1		T492	33		T400	4
values[14]	406	1			T396	1		T492	11		T400	18
values[15]	368	1			T396	1		T492	16		T400	25
values[16]	337	1			T396	1		T492	35		T400	11
values[17]	350	1			T396	1		T492	46		T400	18
values[18]	320	1			T396	1		T492	28		T400	12
values[19]	276	1			T396	1		T492	12		T400	24
values[20]	232	1			T396	1		T492	2		T400	8
values[21]	186	1			T396	1		T492	1		T796	1
values[22]	158	1			T396	1		T796	1		T798	1
values[23]	166	1			T396	1		T796	1		T798	1
values[24]	147	1			T396	1		T796	1		T798	1
values[25]	142	1			T396	1		T796	1		T798	1
values[26]	116	1			T396	1		T796	1		T798	1
values[27]	117	1			T396	1		T796	1		T798	1
values[28]	112	1			T396	1		T796	1		T798	1
values[29]	101	1			T396	1		T796	1		T798	1
values[30]	74	1			T396	1		T796	1		T798	1
values[31]	78	1			T396	1		T796	1		T798	1
values[32]	71	1			T396	1		T796	1		T798	1
values[33]	60	1			T396	1		T796	1		T798	1
values[34]	70	1			T396	1		T796	1		T798	1
values[35]	102	1			T396	1		T796	1		T798	1
values[36]	93	1			T396	1		T796	1		T798	1
values[37]	82	1			T396	1		T796	1		T798	1
values[38]	83	1			T396	1		T796	1		T798	1
values[39]	57	1			T396	1		T796	1		T798	1
values[40]	42	1			T396	1		T796	1		T798	1
values[41]	44	1			T396	1		T796	1		T798	1
values[42]	54	1			T396	1		T796	1		T798	1
values[43]	70	1			T396	1		T796	1		T798	1
values[44]	80	1			T396	1		T796	1		T798	1
values[45]	94	1			T396	1		T796	1		T798	1
values[46]	71	1			T396	1		T796	1		T798	1
values[47]	50	1			T396	1		T796	1		T798	1
values[48]	37	1			T396	1		T796	1		T798	1
values[49]	43	1			T396	1		T796	1		T798	1
values[50]	37	1			T396	1		T796	1		T798	1
values[51]	38	1			T396	1		T796	1		T798	1
values[52]	37	1			T396	1		T796	1		T798	1
values[53]	43	1			T396	1		T796	1		T798	1
values[54]	33	1			T396	1		T796	1		T798	1
values[55]	39	1			T396	1		T796	1		T798	1
values[56]	34	1			T396	1		T796	1		T798	1
values[57]	44	1			T396	1		T796	1		T798	1
values[58]	43	1			T396	1		T796	1		T798	1
values[59]	42	1			T396	1		T796	1		T798	1
values[60]	40	1			T396	1		T796	1		T798	1
values[61]	39	1			T396	1		T796	1		T798	1
values[62]	40	1			T396	1		T796	1		T798	1
values[63]	34	1			T396	1		T796	1		T798	1
values[64]	40	1			T396	1		T796	1		T798	1
values[65]	38	1			T396	1		T796	1		T798	1
values[66]	41	1			T396	1		T796	1		T798	1
values[67]	36	1			T396	1		T796	1		T798	1
values[68]	37	1			T396	1		T796	1		T798	1
values[69]	42	1			T396	1		T796	1		T798	1
values[70]	46	1			T396	1		T796	1		T798	1
values[71]	46	1			T396	1		T796	1		T798	1
values[72]	47	1			T396	1		T796	1		T798	1
values[73]	41	1			T396	1		T796	1		T798	1
values[74]	39	1			T396	1		T796	1		T798	1
values[75]	38	1			T396	1		T796	1		T798	1
values[76]	45	1			T396	1		T796	1		T798	1
values[77]	43	1			T396	1		T796	1		T798	1
values[78]	39	1			T396	1		T796	1		T798	1
values[79]	36	1			T396	1		T796	1		T798	1
values[80]	36	1			T396	1		T796	1		T798	1
values[81]	40	1			T396	1		T796	1		T798	1
values[82]	49	1			T396	1		T796	1		T798	1
values[83]	47	1			T396	1		T796	1		T798	1
values[84]	43	1			T396	1		T796	1		T798	1
values[85]	54	1			T396	1		T796	1		T798	1
values[86]	52	1			T396	1		T796	1		T798	1
values[87]	61	1			T396	1		T796	1		T798	1
values[88]	55	1			T396	1		T796	1		T798	1
values[89]	52	1			T396	1		T796	1		T798	1
values[90]	60	1			T396	1		T796	1		T798	1
values[91]	54	1			T396	1		T796	1		T798	1
values[92]	60	1			T396	1		T796	1		T798	1
values[93]	62	1			T396	1		T796	1		T798	1
values[94]	70	1			T396	3		T796	1		T798	1
values[95]	65	1			T396	4		T796	1		T798	1
values[96]	69	1			T396	4		T796	1		T798	1
values[97]	69	1			T396	3		T796	2		T798	1
values[98]	72	1			T396	2		T796	8		T798	1
values[99]	79	1			T396	2		T796	2		T798	1
values[100]	55	1			T396	3		T796	3		T798	1
values[101]	90	1			T396	1		T796	1		T798	1
values[102]	73	1			T396	3		T796	2		T798	1
values[103]	58	1			T396	2		T796	5		T798	1
values[104]	58	1			T396	1		T796	1		T798	1
values[105]	79	1			T396	6		T796	4		T798	1
values[106]	83	1			T396	5		T796	3		T798	1
values[107]	71	1			T396	2		T796	2		T798	2
values[108]	79	1			T396	3		T796	4		T798	3
values[109]	81	1			T396	2		T796	2		T798	3
values[110]	68	1			T396	2		T796	8		T798	1
values[111]	73	1			T396	6		T796	3		T798	1
values[112]	62	1			T396	1		T796	1		T798	1
values[113]	77	1			T396	3		T796	6		T798	3
values[114]	74	1			T396	2		T796	2		T798	2
values[115]	87	1			T396	1		T796	2		T798	2
values[116]	81	1			T396	2		T796	2		T798	2
values[117]	73	1			T396	3		T796	1		T798	1
values[118]	63	1			T396	2		T796	1		T798	1
values[119]	74	1			T396	4		T796	2		T798	3
values[120]	76	1			T396	6		T796	3		T798	1
values[121]	61	1			T396	1		T796	2		T798	1
values[122]	99	1			T396	4		T796	2		T798	3
values[123]	115	1			T396	2		T796	2		T798	5
values[124]	154	1			T396	3		T796	2		T798	5
values[125]	230	1			T396	2		T796	2		T798	6
values[126]	495	1			T396	23		T796	8		T798	6
values[127]	2604	1			T396	111		T796	108		T798	100
values[128]	4945	1			T396	189		T796	174		T798	182