Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165357	1			T80	937		T81	29		T82	95
values[2]	4537	1			T80	104		T81	1		T399	3
values[3]	2002	1			T80	42		T797	1		T404	1
values[4]	1614	1			T80	3		T797	1		T400	58
values[5]	1298	1			T797	1		T400	34		T403	1
values[6]	999	1			T797	1		T400	5		T403	1
values[7]	769	1			T797	1		T403	1		T462	48
values[8]	634	1			T797	1		T403	1		T462	40
values[9]	602	1			T797	1		T403	1		T462	21
values[10]	551	1			T797	1		T403	1		T462	12
values[11]	467	1			T797	1		T403	1		T462	1
values[12]	437	1			T797	1		T403	1		T462	2
values[13]	383	1			T797	1		T403	1		T808	1
values[14]	402	1			T797	1		T403	1		T808	4
values[15]	382	1			T797	1		T403	1		T808	11
values[16]	365	1			T797	1		T403	1		T808	8
values[17]	351	1			T797	1		T403	1		T808	2
values[18]	352	1			T797	1		T403	1		T808	3
values[19]	315	1			T797	1		T403	1		T808	4
values[20]	271	1			T797	1		T403	1		T808	5
values[21]	252	1			T797	1		T403	1		T808	5
values[22]	171	1			T797	1		T403	1		T808	4
values[23]	125	1			T797	1		T403	1		T808	2
values[24]	86	1			T797	1		T403	1		T808	2
values[25]	67	1			T797	1		T403	1		T808	2
values[26]	51	1			T797	1		T403	1		T808	3
values[27]	59	1			T797	1		T403	1		T808	4
values[28]	64	1			T797	1		T403	1		T808	2
values[29]	76	1			T797	1		T403	1		T808	2
values[30]	81	1			T797	1		T403	1		T808	2
values[31]	118	1			T797	1		T403	1		T808	4
values[32]	102	1			T797	1		T403	1		T808	1
values[33]	106	1			T797	1		T403	1		T808	5
values[34]	85	1			T797	1		T403	1		T808	4
values[35]	61	1			T797	1		T403	1		T808	2
values[36]	42	1			T797	1		T403	1		T808	1
values[37]	41	1			T797	1		T403	1		T822	4
values[38]	48	1			T797	1		T403	1		T822	1
values[39]	53	1			T797	1		T403	1		T822	1
values[40]	37	1			T797	1		T403	1		T822	1
values[41]	43	1			T797	1		T403	1		T822	2
values[42]	39	1			T797	1		T403	1		T822	1
values[43]	36	1			T797	1		T403	1		T822	2
values[44]	42	1			T797	1		T403	1		T822	2
values[45]	45	1			T797	1		T403	1		T822	2
values[46]	37	1			T797	1		T403	1		T822	3
values[47]	35	1			T797	1		T403	1		T822	2
values[48]	44	1			T797	1		T403	1		T822	9
values[49]	55	1			T797	1		T403	1		T822	7
values[50]	44	1			T797	1		T403	1		T822	4
values[51]	51	1			T797	1		T403	1		T822	7
values[52]	43	1			T797	1		T403	1		T822	3
values[53]	39	1			T797	1		T403	1		T822	2
values[54]	35	1			T797	1		T403	1		T822	1
values[55]	37	1			T797	1		T403	1		T822	1
values[56]	38	1			T797	1		T403	1		T822	3
values[57]	37	1			T797	1		T403	1		T822	2
values[58]	37	1			T797	1		T403	1		T822	1
values[59]	41	1			T797	1		T403	1		T822	1
values[60]	41	1			T797	1		T403	1		T822	2
values[61]	42	1			T797	1		T403	1		T822	2
values[62]	43	1			T797	1		T403	1		T822	6
values[63]	41	1			T797	1		T403	1		T822	5
values[64]	39	1			T797	1		T403	1		T822	2
values[65]	40	1			T797	1		T403	1		T822	1
values[66]	35	1			T797	1		T403	1		T822	3
values[67]	34	1			T797	2		T403	1		T822	4
values[68]	46	1			T797	2		T403	1		T822	2
values[69]	38	1			T797	1		T403	1		T822	4
values[70]	34	1			T797	1		T403	1		T822	1
values[71]	46	1			T797	1		T403	1		T822	1
values[72]	46	1			T797	1		T403	1		T822	6
values[73]	38	1			T797	1		T403	1		T822	3
values[74]	45	1			T797	1		T403	1		T822	1
values[75]	54	1			T797	1		T403	1		T822	3
values[76]	56	1			T797	2		T403	1		T822	2
values[77]	39	1			T797	1		T403	1		T822	2
values[78]	35	1			T797	1		T403	1		T822	1
values[79]	40	1			T797	1		T403	1		T822	5
values[80]	47	1			T797	1		T403	1		T822	4
values[81]	40	1			T797	1		T403	1		T822	3
values[82]	46	1			T797	1		T403	1		T822	5
values[83]	51	1			T797	1		T403	1		T822	3
values[84]	38	1			T797	1		T403	1		T822	1
values[85]	50	1			T797	1		T403	1		T822	6
values[86]	48	1			T797	1		T403	1		T822	3
values[87]	47	1			T797	1		T403	1		T822	3
values[88]	74	1			T797	1		T403	1		T822	9
values[89]	53	1			T797	1		T403	1		T822	8
values[90]	64	1			T797	1		T403	1		T822	9
values[91]	51	1			T797	1		T403	1		T822	5
values[92]	49	1			T797	1		T403	1		T822	4
values[93]	56	1			T797	1		T403	1		T822	8
values[94]	65	1			T797	1		T403	1		T822	12
values[95]	63	1			T797	1		T403	2		T822	2
values[96]	53	1			T797	1		T403	1		T822	5
values[97]	54	1			T797	1		T403	1		T822	8
values[98]	61	1			T797	1		T403	1		T822	15
values[99]	49	1			T797	1		T403	1		T822	6
values[100]	50	1			T797	1		T403	1		T822	3
values[101]	51	1			T797	1		T403	1		T822	2
values[102]	74	1			T797	1		T403	1		T822	4
values[103]	61	1			T797	1		T403	1		T822	11
values[104]	75	1			T797	1		T403	1		T822	11
values[105]	58	1			T797	2		T403	1		T822	6
values[106]	73	1			T797	1		T403	1		T822	8
values[107]	76	1			T797	2		T403	1		T822	7
values[108]	80	1			T797	4		T403	1		T822	3
values[109]	84	1			T797	4		T403	1		T822	6
values[110]	60	1			T797	2		T403	1		T822	4
values[111]	66	1			T797	4		T403	1		T822	1
values[112]	63	1			T797	2		T403	1		T822	1
values[113]	72	1			T797	3		T403	1		T822	2
values[114]	70	1			T797	9		T403	1		T822	3
values[115]	60	1			T797	2		T403	1		T822	1
values[116]	77	1			T797	3		T403	1		T822	3
values[117]	72	1			T797	2		T403	1		T822	2
values[118]	78	1			T797	2		T403	2		T822	4
values[119]	80	1			T797	3		T403	4		T822	2
values[120]	74	1			T797	2		T403	1		T822	7
values[121]	91	1			T797	3		T403	1		T822	6
values[122]	83	1			T797	2		T403	1		T822	7
values[123]	95	1			T797	1		T403	1		T822	6
values[124]	186	1			T797	3		T403	1		T822	23
values[125]	317	1			T797	1		T403	1		T822	40
values[126]	661	1			T797	20		T403	18		T822	43
values[127]	2206	1			T797	109		T403	183		T822	14
values[128]	3566	1			T797	175		T403	246		T822	2