Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138888	1			T80	649		T81	31		T82	87
values[2]	9893	1			T80	7		T81	2		T239	1
values[3]	3788	1			T81	1		T399	90		T524	15
values[4]	2162	1			T399	35		T524	22		T525	6
values[5]	1322	1			T399	28		T524	11		T525	11
values[6]	909	1			T399	10		T524	10		T525	14
values[7]	593	1			T399	7		T524	8		T525	4
values[8]	467	1			T399	2		T524	5		T525	3
values[9]	454	1			T399	1		T524	2		T525	6
values[10]	373	1			T524	7		T525	17		T528	10
values[11]	352	1			T524	13		T525	7		T528	10
values[12]	337	1			T524	7		T525	14		T528	7
values[13]	306	1			T524	4		T525	5		T528	5
values[14]	314	1			T524	9		T525	4		T528	6
values[15]	307	1			T524	5		T525	5		T528	8
values[16]	304	1			T524	5		T525	6		T528	12
values[17]	324	1			T524	9		T525	13		T528	13
values[18]	284	1			T524	11		T525	12		T528	3
values[19]	307	1			T524	7		T525	9		T528	6
values[20]	296	1			T524	7		T525	11		T528	4
values[21]	292	1			T524	3		T525	6		T528	3
values[22]	291	1			T524	5		T525	7		T528	6
values[23]	204	1			T524	3		T525	3		T528	4
values[24]	218	1			T524	11		T525	4		T528	7
values[25]	274	1			T524	9		T525	7		T528	12
values[26]	313	1			T524	10		T525	5		T528	13
values[27]	276	1			T524	3		T525	16		T528	5
values[28]	286	1			T524	9		T525	21		T528	3
values[29]	281	1			T524	11		T525	6		T528	13
values[30]	234	1			T524	6		T525	5		T528	6
values[31]	322	1			T524	8		T525	14		T528	19
values[32]	245	1			T524	5		T525	7		T528	4
values[33]	331	1			T524	5		T525	13		T528	4
values[34]	270	1			T524	14		T525	4		T528	13
values[35]	270	1			T524	3		T525	5		T528	2
values[36]	284	1			T524	9		T525	8		T528	3
values[37]	282	1			T524	8		T525	7		T528	8
values[38]	251	1			T524	8		T525	10		T528	12
values[39]	236	1			T525	6		T528	5		T668	2
values[40]	230	1			T525	4		T528	4		T615	5
values[41]	294	1			T525	10		T528	2		T615	10
values[42]	221	1			T525	6		T528	5		T615	5
values[43]	247	1			T525	3		T528	10		T615	7
values[44]	254	1			T525	7		T528	8		T615	7
values[45]	207	1			T525	4		T528	5		T615	3
values[46]	229	1			T525	11		T528	5		T615	5
values[47]	272	1			T525	8		T528	5		T615	14
values[48]	233	1			T525	6		T528	11		T615	9
values[49]	241	1			T525	3		T528	12		T615	9
values[50]	227	1			T525	5		T528	3		T615	7
values[51]	254	1			T525	23		T528	4		T615	16
values[52]	256	1			T525	13		T528	8		T615	7
values[53]	300	1			T525	16		T528	15		T615	9
values[54]	194	1			T525	6		T528	6		T615	3
values[55]	247	1			T525	4		T528	7		T615	7
values[56]	221	1			T525	6		T528	6		T615	6
values[57]	193	1			T525	7		T528	5		T615	7
values[58]	199	1			T525	3		T528	11		T615	6
values[59]	226	1			T525	9		T528	20		T615	8
values[60]	216	1			T525	7		T528	19		T615	4
values[61]	179	1			T525	5		T528	13		T615	10
values[62]	233	1			T525	3		T528	3		T615	9
values[63]	226	1			T525	3		T528	10		T615	5
values[64]	216	1			T525	7		T528	6		T615	5
values[65]	202	1			T525	6		T528	6		T615	3
values[66]	221	1			T525	6		T528	7		T615	3
values[67]	212	1			T525	2		T528	4		T615	4
values[68]	181	1			T528	15		T615	11		T798	1
values[69]	186	1			T528	9		T615	11		T798	1
values[70]	152	1			T528	13		T615	7		T798	1
values[71]	172	1			T528	2		T615	4		T798	1
values[72]	133	1			T615	5		T798	1		T802	1
values[73]	155	1			T615	8		T798	1		T802	1
values[74]	127	1			T615	6		T798	1		T802	1
values[75]	88	1			T615	2		T798	1		T802	1
values[76]	71	1			T798	1		T802	1		T633	2
values[77]	65	1			T798	1		T802	1		T823	1
values[78]	69	1			T798	1		T802	1		T823	1
values[79]	61	1			T798	1		T802	2		T823	1
values[80]	60	1			T798	1		T802	1		T823	1
values[81]	49	1			T798	1		T802	5		T823	1
values[82]	52	1			T798	1		T802	4		T823	1
values[83]	59	1			T798	1		T802	2		T823	1
values[84]	58	1			T798	1		T802	1		T823	1
values[85]	67	1			T798	1		T802	1		T823	1
values[86]	74	1			T798	1		T802	1		T823	1
values[87]	84	1			T798	1		T802	1		T823	1
values[88]	79	1			T798	1		T802	1		T823	1
values[89]	50	1			T798	1		T802	3		T823	1
values[90]	66	1			T798	1		T802	5		T823	1
values[91]	59	1			T798	1		T802	6		T823	1
values[92]	61	1			T798	1		T802	4		T823	1
values[93]	52	1			T798	1		T802	8		T823	1
values[94]	47	1			T798	1		T802	2		T823	1
values[95]	52	1			T798	1		T802	4		T823	1
values[96]	60	1			T798	2		T802	2		T823	1
values[97]	46	1			T798	1		T802	1		T823	1
values[98]	51	1			T798	1		T802	1		T823	1
values[99]	57	1			T798	1		T802	1		T823	1
values[100]	61	1			T798	1		T802	5		T823	1
values[101]	70	1			T798	1		T802	4		T823	1
values[102]	64	1			T798	1		T802	5		T823	1
values[103]	46	1			T798	1		T802	3		T823	1
values[104]	56	1			T798	1		T802	2		T823	1
values[105]	50	1			T798	1		T802	2		T823	1
values[106]	53	1			T798	1		T802	3		T823	1
values[107]	51	1			T798	1		T802	4		T823	1
values[108]	69	1			T798	1		T802	5		T823	1
values[109]	53	1			T798	1		T802	4		T823	1
values[110]	53	1			T798	1		T802	2		T823	1
values[111]	53	1			T798	1		T802	1		T823	1
values[112]	50	1			T798	1		T802	1		T823	1
values[113]	50	1			T798	1		T802	1		T823	1
values[114]	55	1			T798	1		T802	1		T823	1
values[115]	46	1			T798	1		T802	2		T823	1
values[116]	54	1			T798	1		T802	1		T823	3
values[117]	74	1			T798	2		T802	3		T823	4
values[118]	62	1			T798	1		T802	2		T823	1
values[119]	63	1			T798	2		T802	2		T823	4
values[120]	70	1			T798	7		T802	4		T823	4
values[121]	59	1			T798	3		T802	1		T823	3
values[122]	61	1			T798	1		T802	2		T823	4
values[123]	50	1			T798	1		T802	1		T823	1
values[124]	64	1			T798	1		T802	2		T823	1
values[125]	51	1			T798	1		T802	1		T823	1
values[126]	90	1			T798	3		T802	1		T823	10
values[127]	575	1			T798	42		T802	27		T823	29
values[128]	4973	1			T798	375		T802	268		T823	255