Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156153	1			T80	649		T81	23		T82	75
values[2]	4211	1			T80	3		T81	1		T523	4
values[3]	2048	1			T523	3		T797	1		T621	105
values[4]	1464	1			T523	1		T797	1		T621	58
values[5]	1126	1			T523	6		T797	1		T621	24
values[6]	901	1			T523	15		T797	1		T621	31
values[7]	708	1			T523	6		T797	1		T621	23
values[8]	649	1			T523	17		T797	1		T621	8
values[9]	645	1			T523	17		T797	1		T621	1
values[10]	606	1			T523	29		T797	1		T621	1
values[11]	532	1			T523	29		T797	1		T492	6
values[12]	453	1			T523	23		T797	1		T492	7
values[13]	381	1			T523	11		T797	1		T492	3
values[14]	397	1			T523	4		T797	1		T492	15
values[15]	395	1			T523	29		T797	1		T492	23
values[16]	368	1			T523	26		T797	1		T492	38
values[17]	289	1			T523	29		T797	1		T492	48
values[18]	248	1			T523	33		T797	1		T492	33
values[19]	251	1			T523	37		T797	1		T492	38
values[20]	212	1			T523	9		T797	1		T492	26
values[21]	222	1			T523	15		T797	1		T492	19
values[22]	227	1			T523	24		T797	1		T492	17
values[23]	203	1			T523	22		T797	1		T492	16
values[24]	156	1			T523	18		T797	1		T492	13
values[25]	104	1			T523	3		T797	1		T492	8
values[26]	117	1			T523	15		T797	1		T492	14
values[27]	111	1			T523	4		T797	1		T492	2
values[28]	140	1			T797	1		T492	2		T798	1
values[29]	125	1			T797	1		T798	1		T800	1
values[30]	113	1			T797	1		T798	1		T800	1
values[31]	123	1			T797	1		T798	1		T800	1
values[32]	136	1			T797	1		T798	1		T800	1
values[33]	103	1			T797	1		T798	1		T800	1
values[34]	59	1			T797	1		T798	1		T800	1
values[35]	38	1			T797	1		T798	1		T800	1
values[36]	60	1			T797	1		T798	1		T800	1
values[37]	62	1			T797	1		T798	1		T800	1
values[38]	42	1			T797	1		T798	1		T800	1
values[39]	37	1			T797	1		T798	1		T800	1
values[40]	36	1			T797	1		T798	1		T800	1
values[41]	37	1			T797	1		T798	1		T800	1
values[42]	38	1			T797	1		T798	1		T800	1
values[43]	31	1			T797	1		T798	1		T800	1
values[44]	33	1			T797	1		T798	1		T800	1
values[45]	31	1			T797	1		T798	1		T800	1
values[46]	35	1			T797	1		T798	1		T800	1
values[47]	30	1			T797	1		T798	1		T800	1
values[48]	34	1			T797	1		T798	1		T800	1
values[49]	32	1			T797	1		T798	1		T800	1
values[50]	40	1			T797	1		T798	1		T800	1
values[51]	28	1			T797	1		T798	1		T800	1
values[52]	38	1			T797	1		T798	1		T800	1
values[53]	33	1			T797	1		T798	1		T800	1
values[54]	36	1			T797	1		T798	1		T800	1
values[55]	42	1			T797	1		T798	1		T800	1
values[56]	40	1			T797	1		T798	1		T800	1
values[57]	31	1			T797	1		T798	1		T800	1
values[58]	36	1			T797	1		T798	1		T800	1
values[59]	28	1			T797	1		T798	1		T800	1
values[60]	38	1			T797	1		T798	1		T800	1
values[61]	39	1			T797	1		T798	1		T800	1
values[62]	43	1			T797	1		T798	2		T800	1
values[63]	41	1			T797	1		T798	1		T800	1
values[64]	34	1			T797	1		T798	1		T800	1
values[65]	38	1			T797	1		T798	1		T800	1
values[66]	43	1			T797	1		T798	1		T800	1
values[67]	43	1			T797	1		T798	1		T800	1
values[68]	41	1			T797	1		T798	1		T800	1
values[69]	43	1			T797	1		T798	1		T800	1
values[70]	41	1			T797	1		T798	1		T800	1
values[71]	45	1			T797	1		T798	1		T800	1
values[72]	32	1			T797	1		T798	1		T800	1
values[73]	30	1			T797	1		T798	1		T800	1
values[74]	33	1			T797	1		T798	1		T800	1
values[75]	34	1			T797	1		T798	1		T800	1
values[76]	38	1			T797	1		T798	1		T800	1
values[77]	36	1			T797	1		T798	1		T800	1
values[78]	35	1			T797	1		T798	1		T800	1
values[79]	40	1			T797	1		T798	1		T800	1
values[80]	32	1			T797	1		T798	1		T800	1
values[81]	44	1			T797	1		T798	4		T800	1
values[82]	54	1			T797	1		T798	8		T800	1
values[83]	36	1			T797	1		T798	3		T800	1
values[84]	44	1			T797	1		T798	6		T800	1
values[85]	44	1			T797	1		T798	6		T800	1
values[86]	39	1			T797	1		T798	1		T800	1
values[87]	32	1			T797	1		T798	1		T800	1
values[88]	38	1			T797	1		T798	3		T800	1
values[89]	44	1			T797	1		T798	7		T800	1
values[90]	37	1			T797	1		T798	1		T800	1
values[91]	49	1			T797	1		T798	2		T800	1
values[92]	50	1			T797	1		T798	7		T800	3
values[93]	56	1			T797	1		T798	6		T800	5
values[94]	57	1			T797	1		T798	4		T800	4
values[95]	52	1			T797	1		T798	5		T800	3
values[96]	37	1			T797	1		T798	1		T800	3
values[97]	50	1			T797	1		T798	2		T800	3
values[98]	63	1			T797	1		T798	2		T800	5
values[99]	51	1			T797	1		T798	1		T800	4
values[100]	66	1			T797	1		T798	2		T800	2
values[101]	66	1			T797	1		T798	2		T800	7
values[102]	52	1			T797	1		T798	2		T800	2
values[103]	47	1			T797	1		T798	2		T800	2
values[104]	51	1			T797	1		T798	1		T800	2
values[105]	49	1			T797	1		T798	1		T800	1
values[106]	68	1			T797	3		T798	3		T800	1
values[107]	71	1			T797	4		T798	2		T800	4
values[108]	57	1			T797	1		T798	6		T800	4
values[109]	68	1			T797	3		T798	3		T800	2
values[110]	64	1			T797	5		T798	2		T800	2
values[111]	56	1			T797	1		T798	4		T800	2
values[112]	64	1			T797	2		T798	2		T800	1
values[113]	60	1			T797	5		T798	3		T800	3
values[114]	82	1			T797	5		T798	2		T800	1
values[115]	86	1			T797	1		T798	4		T800	1
values[116]	69	1			T797	2		T798	1		T800	3
values[117]	66	1			T797	2		T798	1		T800	2
values[118]	75	1			T797	1		T798	3		T800	2
values[119]	68	1			T797	1		T798	5		T800	3
values[120]	72	1			T797	3		T798	3		T800	3
values[121]	63	1			T797	1		T798	1		T800	1
values[122]	69	1			T797	1		T798	2		T800	3
values[123]	84	1			T797	1		T798	3		T800	2
values[124]	161	1			T797	1		T798	1		T800	1
values[125]	332	1			T797	1		T798	2		T800	1
values[126]	677	1			T797	17		T798	14		T800	5
values[127]	1618	1			T797	109		T798	79		T800	114
values[128]	2678	1			T797	195		T798	176		T800	274