Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	489	1			T80	5		T352	1		T528	2
all_values[1]	441	1			T80	6		T352	2		T399	1
all_values[2]	445	1			T80	3		T352	5		T399	1
all_values[3]	465	1			T80	4		T352	3		T523	1
all_values[4]	504	1			T80	8		T352	4		T523	1
all_values[5]	460	1			T80	4		T352	2		T397	1
all_values[6]	437	1			T80	5		T352	2		T523	1
all_values[7]	454	1			T80	4		T352	3		T397	1
all_values[8]	490	1			T80	3		T352	3		T399	1
all_values[9]	470	1			T80	5		T352	2		T524	2
all_values[10]	459	1			T80	3		T352	2		T397	1
all_values[11]	460	1			T80	7		T352	1		T397	1
all_values[12]	443	1			T80	3		T352	1		T523	1
all_values[13]	462	1			T80	5		T352	1		T397	1
all_values[14]	436	1			T80	6		T352	3		T523	1
all_values[15]	424	1			T80	3		T352	1		T397	1
all_values[16]	440	1			T80	3		T352	1		T397	1
all_values[17]	446	1			T80	1		T352	3		T397	1
all_values[18]	456	1			T80	1		T352	2		T807	1
all_values[19]	464	1			T80	7		T352	3		T399	1
all_values[20]	464	1			T80	3		T352	2		T396	1
all_values[21]	423	1			T80	1		T352	2		T524	1
all_values[22]	468	1			T80	6		T352	2		T525	1
all_values[23]	433	1			T80	2		T525	2		T402	1
all_values[24]	468	1			T80	7		T524	1		T678	1
all_values[25]	486	1			T80	4		T352	2		T524	1
all_values[26]	482	1			T80	8		T352	2		T397	1
all_values[27]	456	1			T80	3		T352	1		T396	1
all_values[28]	463	1			T80	4		T352	1		T807	1
all_values[29]	486	1			T80	6		T352	1		T399	1
all_values[30]	471	1			T80	5		T352	2		T396	1
all_values[31]	480	1			T80	6		T797	1		T528	2
all_values[32]	489	1			T80	5		T352	1		T523	2
all_values[33]	460	1			T80	5		T352	1		T397	3
all_values[34]	419	1			T80	2		T352	2		T399	2
all_values[35]	450	1			T80	4		T352	1		T524	1
all_values[36]	465	1			T80	12		T397	1		T399	2
all_values[37]	459	1			T80	5		T352	4		T399	1
all_values[38]	467	1			T80	4		T399	1		T396	1
all_values[39]	416	1			T80	7		T352	3		T523	1
all_values[40]	455	1			T80	7		T352	5		T397	1
all_values[41]	465	1			T80	6		T352	4		T523	1
all_values[42]	446	1			T80	4		T352	4		T523	1
all_values[43]	463	1			T80	11		T352	3		T523	1
all_values[44]	448	1			T80	2		T352	1		T397	2
all_values[45]	478	1			T80	4		T397	1		T399	1
all_values[46]	479	1			T80	5		T397	1		T399	1
all_values[47]	458	1			T80	4		T352	1		T402	3
all_values[48]	468	1			T80	8		T352	1		T525	1
all_values[49]	469	1			T80	9		T352	3		T523	1