Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3462	1			T80	26		T352	13		T397	2
all_values[1]	3450	1			T80	21		T352	11		T397	8
all_values[2]	3457	1			T80	36		T352	12		T397	5
all_values[3]	3490	1			T80	33		T352	11		T397	7
all_values[4]	3440	1			T80	21		T352	12		T397	4
all_values[5]	3494	1			T80	27		T352	10		T397	6
all_values[6]	3475	1			T80	23		T352	9		T397	8
all_values[7]	3593	1			T80	31		T352	20		T397	5
all_values[8]	3368	1			T80	19		T352	6		T397	9
all_values[9]	3513	1			T80	26		T352	8		T397	13
all_values[10]	3616	1			T80	32		T352	9		T397	7
all_values[11]	3473	1			T80	22		T352	13		T397	15
all_values[12]	3476	1			T80	25		T352	7		T397	6
all_values[13]	3448	1			T80	33		T352	15		T397	2
all_values[14]	3539	1			T80	33		T352	19		T397	6
all_values[15]	3439	1			T80	27		T352	18		T397	4
all_values[16]	3539	1			T80	25		T352	16		T397	10
all_values[17]	3437	1			T80	21		T352	16		T397	5
all_values[18]	3445	1			T80	24		T352	22		T397	9
all_values[19]	3562	1			T80	29		T352	16		T397	4
all_values[20]	3495	1			T80	25		T352	14		T397	7
all_values[21]	3373	1			T80	25		T352	16		T397	8
all_values[22]	3415	1			T80	32		T352	11		T397	11
all_values[23]	3506	1			T80	29		T352	15		T397	4
all_values[24]	3420	1			T80	23		T352	8		T397	7
all_values[25]	3470	1			T80	22		T352	17		T397	2
all_values[26]	3445	1			T80	25		T352	17		T397	6
all_values[27]	3377	1			T80	18		T352	13		T397	4
all_values[28]	3426	1			T80	20		T352	14		T397	6
all_values[29]	3475	1			T80	35		T352	10		T397	11
all_values[30]	3531	1			T80	21		T352	13		T397	8
all_values[31]	3398	1			T80	30		T352	11		T397	10
all_values[32]	3466	1			T80	27		T352	19		T399	2
all_values[33]	3527	1			T80	20		T352	23		T397	6
all_values[34]	3381	1			T80	27		T352	12		T397	4
all_values[35]	3599	1			T80	30		T352	10		T397	6
all_values[36]	3523	1			T80	21		T352	10		T397	9
all_values[37]	3562	1			T80	30		T352	13		T397	7
all_values[38]	3586	1			T80	29		T352	9		T397	5
all_values[39]	3455	1			T80	22		T352	12		T397	8
all_values[40]	3461	1			T80	24		T352	12		T397	9
all_values[41]	3435	1			T80	20		T352	16		T397	9
all_values[42]	3386	1			T80	21		T352	15		T397	9
all_values[43]	3443	1			T80	36		T352	15		T397	3
all_values[44]	3516	1			T80	28		T352	17		T397	7
all_values[45]	3513	1			T80	28		T352	14		T397	3
all_values[46]	3527	1			T80	22		T352	14		T397	8
all_values[47]	3421	1			T80	25		T352	15		T397	9
all_values[48]	3463	1			T80	27		T352	13		T397	7
all_values[49]	3429	1			T80	29		T352	10		T397	7
all_values[50]	3445	1			T80	26		T352	11		T397	4
all_values[51]	3453	1			T80	26		T352	13		T397	6
all_values[52]	3437	1			T80	25		T352	16		T397	6
all_values[53]	3491	1			T80	28		T352	15		T397	6
all_values[54]	3430	1			T80	29		T352	19		T397	4
all_values[55]	3498	1			T80	30		T352	18		T397	7
all_values[56]	3436	1			T80	20		T352	12		T397	13
all_values[57]	3452	1			T80	19		T352	12		T397	5
all_values[58]	3527	1			T80	26		T352	10		T397	6
all_values[59]	3559	1			T80	28		T352	13		T397	10
all_values[60]	3494	1			T80	16		T352	11		T397	8
all_values[61]	3367	1			T80	27		T352	14		T397	7
all_values[62]	3483	1			T80	25		T352	12		T397	5
all_values[63]	3438	1			T80	33		T352	6		T397	3