Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141666	1			T73	39		T75	18		T80	88
values[2]	9485	1			T420	5		T447	278		T716	1
values[3]	4694	1			T420	1		T447	154		T476	1
values[4]	2833	1			T447	81		T476	1		T411	110
values[5]	1774	1			T447	48		T411	37		T613	43
values[6]	1271	1			T447	24		T411	5		T613	12
values[7]	1050	1			T447	4		T613	10		T481	2
values[8]	834	1			T447	2		T613	13		T481	2
values[9]	741	1			T613	2		T481	2		T405	5
values[10]	702	1			T481	2		T405	20		T417	17
values[11]	640	1			T481	3		T405	6		T417	25
values[12]	656	1			T481	2		T405	3		T417	22
values[13]	582	1			T481	2		T405	12		T417	19
values[14]	609	1			T481	2		T405	11		T417	23
values[15]	574	1			T481	2		T405	6		T417	19
values[16]	466	1			T481	2		T405	9		T417	1
values[17]	528	1			T481	2		T405	7		T452	29
values[18]	543	1			T481	2		T405	16		T452	44
values[19]	486	1			T481	2		T405	8		T452	38
values[20]	413	1			T481	2		T405	19		T452	25
values[21]	518	1			T481	2		T405	13		T452	61
values[22]	547	1			T481	2		T405	6		T452	41
values[23]	466	1			T481	2		T405	5		T452	37
values[24]	480	1			T481	2		T405	10		T452	39
values[25]	433	1			T481	2		T405	13		T452	43
values[26]	432	1			T481	2		T405	8		T452	47
values[27]	423	1			T481	2		T405	12		T452	42
values[28]	427	1			T481	2		T405	7		T452	40
values[29]	463	1			T481	2		T405	7		T452	32
values[30]	462	1			T481	2		T405	13		T452	42
values[31]	361	1			T481	2		T405	9		T452	18
values[32]	412	1			T481	2		T405	7		T452	28
values[33]	443	1			T481	2		T405	13		T452	31
values[34]	408	1			T481	2		T405	17		T452	23
values[35]	366	1			T481	2		T405	14		T452	21
values[36]	372	1			T481	2		T405	4		T452	25
values[37]	427	1			T481	2		T405	7		T452	52
values[38]	402	1			T481	2		T405	5		T452	41
values[39]	405	1			T481	2		T405	6		T452	26
values[40]	374	1			T481	2		T405	14		T452	24
values[41]	264	1			T481	2		T405	5		T452	19
values[42]	254	1			T481	2		T405	9		T452	20
values[43]	233	1			T481	2		T405	7		T452	12
values[44]	310	1			T481	2		T405	16		T452	30
values[45]	291	1			T481	2		T405	41		T452	10
values[46]	239	1			T481	2		T405	4		T452	7
values[47]	244	1			T481	2		T405	10		T452	8
values[48]	197	1			T481	2		T405	8		T452	1
values[49]	194	1			T481	2		T405	5		T796	1
values[50]	157	1			T481	2		T405	10		T796	1
values[51]	151	1			T481	2		T405	3		T796	1
values[52]	117	1			T481	2		T796	1		T474	10
values[53]	100	1			T481	2		T796	1		T474	13
values[54]	70	1			T481	2		T796	1		T474	5
values[55]	81	1			T481	2		T796	1		T474	5
values[56]	90	1			T481	2		T796	1		T474	9
values[57]	67	1			T481	2		T796	1		T474	4
values[58]	77	1			T481	2		T796	1		T474	5
values[59]	67	1			T481	2		T796	1		T797	1
values[60]	53	1			T481	2		T796	1		T797	1
values[61]	48	1			T481	2		T796	1		T797	1
values[62]	55	1			T481	2		T796	1		T797	1
values[63]	51	1			T481	2		T796	1		T797	1
values[64]	54	1			T481	2		T796	1		T797	1
values[65]	59	1			T481	2		T796	1		T797	1
values[66]	41	1			T481	2		T796	1		T797	1
values[67]	40	1			T481	2		T796	1		T797	1
values[68]	46	1			T481	2		T796	1		T797	1
values[69]	45	1			T481	2		T796	1		T797	1
values[70]	53	1			T481	2		T796	1		T797	1
values[71]	57	1			T481	2		T796	1		T797	1
values[72]	49	1			T481	2		T796	1		T797	1
values[73]	60	1			T481	2		T796	2		T797	1
values[74]	42	1			T481	2		T796	1		T797	1
values[75]	49	1			T481	2		T796	1		T797	1
values[76]	57	1			T481	3		T796	1		T797	1
values[77]	55	1			T481	8		T796	1		T797	1
values[78]	54	1			T481	7		T796	1		T797	1
values[79]	53	1			T481	3		T796	1		T797	1
values[80]	49	1			T481	4		T796	1		T797	1
values[81]	48	1			T481	6		T796	1		T797	1
values[82]	52	1			T481	5		T796	1		T797	1
values[83]	56	1			T481	4		T796	1		T797	1
values[84]	45	1			T481	3		T796	1		T797	1
values[85]	57	1			T481	2		T796	1		T797	1
values[86]	45	1			T481	4		T796	1		T797	1
values[87]	50	1			T481	10		T796	1		T797	1
values[88]	52	1			T481	7		T796	1		T797	1
values[89]	65	1			T481	3		T796	1		T797	1
values[90]	70	1			T481	10		T796	1		T797	1
values[91]	71	1			T481	3		T796	1		T797	1
values[92]	80	1			T481	8		T796	1		T797	1
values[93]	54	1			T481	5		T796	1		T797	1
values[94]	50	1			T481	2		T796	1		T797	1
values[95]	60	1			T481	4		T796	1		T797	1
values[96]	58	1			T481	4		T796	1		T797	1
values[97]	51	1			T481	2		T796	1		T797	1
values[98]	58	1			T481	3		T796	1		T797	1
values[99]	56	1			T481	3		T796	1		T797	1
values[100]	57	1			T481	9		T796	1		T797	1
values[101]	45	1			T481	2		T796	1		T797	1
values[102]	53	1			T481	3		T796	1		T797	1
values[103]	49	1			T481	6		T796	1		T797	1
values[104]	57	1			T481	4		T796	1		T797	1
values[105]	77	1			T481	5		T796	2		T797	1
values[106]	65	1			T481	7		T796	3		T797	1
values[107]	59	1			T481	5		T796	5		T797	1
values[108]	41	1			T481	3		T796	2		T797	1
values[109]	58	1			T481	4		T796	1		T797	1
values[110]	66	1			T481	4		T796	5		T797	1
values[111]	44	1			T481	3		T796	1		T797	1
values[112]	64	1			T481	5		T796	2		T797	1
values[113]	64	1			T481	8		T796	2		T797	1
values[114]	61	1			T481	7		T796	1		T797	1
values[115]	51	1			T481	5		T796	1		T797	1
values[116]	69	1			T481	3		T796	1		T797	1
values[117]	59	1			T481	4		T796	1		T797	2
values[118]	69	1			T481	6		T796	1		T797	1
values[119]	56	1			T481	2		T796	2		T797	3
values[120]	49	1			T481	2		T796	4		T797	3
values[121]	53	1			T481	4		T796	2		T797	6
values[122]	64	1			T481	5		T796	4		T797	3
values[123]	64	1			T481	9		T796	4		T797	3
values[124]	47	1			T481	3		T796	1		T797	1
values[125]	46	1			T481	4		T796	2		T797	1
values[126]	116	1			T481	8		T796	6		T797	4
values[127]	1541	1			T481	98		T796	47		T797	63
values[128]	7146	1			T481	530		T796	248		T797	262