Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 95.29 93.57 95.62 94.21 97.38 99.55


Total tests in report: 2847
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.44 40.44 45.61 45.61 43.19 43.19 32.14 32.14 58.31 58.31 63.03 63.03 0.39 0.39 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1407530615
49.45 9.01 51.15 5.55 54.90 11.71 32.79 0.66 66.70 8.39 89.65 26.62 1.50 1.12 /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.219698737
54.81 5.36 51.80 0.65 60.42 5.52 33.71 0.92 67.98 1.29 89.65 0.00 25.32 23.82 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1232795569
60.06 5.25 62.87 11.07 68.16 7.74 36.15 2.44 78.22 10.23 89.65 0.00 25.32 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.2760600197
64.38 4.32 75.46 12.59 68.66 0.51 44.09 7.94 78.38 0.16 89.65 0.00 30.06 4.74 /workspace/coverage/cover_reg_top/49.xbar_same_source.1160080075
67.44 3.06 75.46 0.00 68.79 0.13 44.09 0.00 78.40 0.02 89.65 0.00 48.27 18.21 /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1667142850
69.79 2.35 80.77 5.32 72.64 3.84 47.53 3.44 79.91 1.52 89.65 0.00 48.27 0.00 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2262055095
72.08 2.29 80.77 0.00 72.64 0.00 61.20 13.67 79.91 0.00 89.65 0.00 48.31 0.05 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.121150855
74.18 2.10 80.77 0.00 72.64 0.00 61.20 0.00 79.91 0.00 89.65 0.00 60.91 12.60 /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1511466466
75.99 1.81 82.65 1.87 75.08 2.44 65.79 4.59 81.66 1.75 89.83 0.18 60.91 0.00 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4064216471
77.77 1.79 82.65 0.00 75.09 0.01 65.79 0.00 81.66 0.00 89.83 0.00 71.61 10.70 /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2221698607
79.28 1.51 84.70 2.05 78.59 3.50 66.07 0.28 84.91 3.25 89.83 0.00 71.61 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.813249911
80.69 1.41 84.93 0.24 78.75 0.16 73.56 7.49 85.09 0.18 90.20 0.37 71.61 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.862208307
81.85 1.16 86.59 1.65 80.06 1.31 74.30 0.74 86.45 1.37 92.05 1.85 71.66 0.05 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3425936577
82.93 1.08 86.59 0.00 80.06 0.00 74.30 0.00 86.45 0.00 92.05 0.00 78.15 6.49 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3449699072
83.92 0.99 86.77 0.19 80.18 0.12 79.80 5.50 86.53 0.07 92.05 0.00 78.19 0.05 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2216535181
84.87 0.95 87.54 0.77 80.60 0.43 79.81 0.02 86.93 0.40 96.12 4.07 78.19 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1809608555
85.74 0.87 87.54 0.00 80.73 0.13 79.81 0.00 86.95 0.02 96.12 0.00 83.28 5.09 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2406293524
86.58 0.84 88.77 1.22 81.78 1.05 81.41 1.60 88.11 1.16 96.12 0.00 83.28 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.662312789
87.34 0.76 89.54 0.77 83.73 1.96 81.79 0.38 89.29 1.18 96.12 0.00 83.55 0.27 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1899472096
88.08 0.75 90.91 1.37 84.54 0.80 82.96 1.17 90.43 1.15 96.12 0.00 83.55 0.00 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.783422832
88.70 0.61 91.27 0.36 84.90 0.36 85.23 2.27 90.85 0.41 96.12 0.00 83.83 0.28 /workspace/coverage/default/0.chip_jtag_csr_rw.3908705965
89.28 0.58 91.27 0.00 85.37 0.48 85.23 0.00 90.95 0.10 96.12 0.00 86.75 2.91 /workspace/coverage/cover_reg_top/54.xbar_stress_all.1576993893
89.79 0.51 92.14 0.88 86.36 0.98 85.56 0.33 91.79 0.85 96.12 0.00 86.75 0.00 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2468009481
90.29 0.50 92.14 0.00 86.36 0.00 85.56 0.00 91.79 0.00 96.12 0.00 89.74 3.00 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3965907025
90.74 0.45 93.06 0.91 87.23 0.88 85.77 0.21 92.44 0.64 96.12 0.00 89.80 0.06 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.965359565
91.15 0.41 93.09 0.03 87.28 0.05 86.84 1.07 92.44 0.00 96.12 0.00 91.12 1.32 /workspace/coverage/default/1.chip_sw_alert_test.2864455694
91.53 0.38 93.10 0.01 89.16 1.88 86.84 0.00 92.44 0.00 96.12 0.00 91.53 0.41 /workspace/coverage/cover_reg_top/4.chip_tl_errors.3041138907
91.90 0.37 93.10 0.00 89.16 0.00 86.84 0.00 92.44 0.00 96.12 0.00 93.76 2.23 /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2509298661
92.26 0.36 93.10 0.00 89.16 0.00 88.99 2.15 92.44 0.00 96.12 0.00 93.76 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3866873637
92.55 0.29 93.15 0.05 89.30 0.14 90.19 1.20 92.54 0.11 96.30 0.18 93.81 0.05 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.937440406
92.82 0.27 93.15 0.00 89.35 0.05 90.20 0.01 92.54 0.00 96.30 0.00 95.36 1.55 /workspace/coverage/cover_reg_top/17.xbar_random.3634492342
93.06 0.24 93.58 0.43 89.75 0.40 90.42 0.23 92.94 0.40 96.30 0.00 95.36 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.2235182108
93.27 0.21 93.58 0.00 89.75 0.00 90.42 0.00 92.94 0.00 96.30 0.00 96.60 1.25 /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3727962817
93.45 0.18 93.66 0.08 89.76 0.01 91.41 0.98 92.95 0.01 96.30 0.00 96.62 0.01 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1802654967
93.62 0.18 93.66 0.00 89.89 0.13 91.41 0.00 92.96 0.02 96.30 0.00 97.52 0.90 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3712060401
93.80 0.17 93.73 0.08 90.34 0.44 91.45 0.05 93.43 0.47 96.30 0.00 97.52 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1486395619
93.92 0.13 93.95 0.22 90.66 0.33 91.66 0.21 93.43 0.00 96.30 0.00 97.52 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3680792468
94.04 0.12 93.95 0.00 90.66 0.00 92.34 0.68 93.43 0.00 96.30 0.00 97.56 0.04 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3584867931
94.16 0.12 93.95 0.00 90.74 0.08 92.34 0.00 93.43 0.00 96.30 0.00 98.17 0.61 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.979216038
94.25 0.10 93.95 0.00 90.74 0.00 92.91 0.57 93.43 0.00 96.30 0.00 98.17 0.00 /workspace/coverage/default/0.chip_sw_edn_auto_mode.628712841
94.34 0.09 93.95 0.00 91.27 0.53 92.91 0.00 93.43 0.00 96.30 0.00 98.17 0.00 /workspace/coverage/cover_reg_top/5.chip_tl_errors.2714995604
94.41 0.07 93.95 0.00 91.27 0.00 93.36 0.44 93.43 0.00 96.30 0.00 98.17 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4234837243
94.49 0.07 94.10 0.15 91.38 0.11 93.41 0.06 93.56 0.12 96.30 0.00 98.17 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3538599127
94.56 0.07 94.21 0.11 91.55 0.16 93.49 0.08 93.64 0.08 96.30 0.00 98.17 0.00 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.467402960
94.63 0.07 94.21 0.00 91.55 0.00 93.92 0.43 93.64 0.00 96.30 0.00 98.17 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1072010097
94.70 0.07 94.29 0.08 91.74 0.20 93.92 0.00 93.79 0.15 96.30 0.00 98.17 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2643269502
94.76 0.06 94.44 0.15 91.77 0.03 94.09 0.17 93.80 0.02 96.30 0.00 98.18 0.01 /workspace/coverage/default/97.chip_sw_all_escalation_resets.4278184582
94.81 0.05 94.44 0.00 91.91 0.14 94.09 0.00 93.82 0.02 96.30 0.00 98.32 0.14 /workspace/coverage/cover_reg_top/69.xbar_stress_all.124682262
94.86 0.05 94.47 0.03 91.94 0.03 94.09 0.01 93.85 0.02 96.49 0.18 98.33 0.01 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2137338749
94.90 0.04 94.48 0.01 91.95 0.01 94.12 0.03 93.85 0.01 96.67 0.18 98.33 0.00 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3611782034
94.94 0.04 94.49 0.01 91.96 0.01 94.12 0.00 93.88 0.02 96.86 0.18 98.34 0.01 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1268980490
94.98 0.04 94.50 0.01 91.98 0.01 94.12 0.00 93.89 0.01 97.04 0.18 98.36 0.01 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188948393
95.02 0.04 94.50 0.01 91.99 0.01 94.13 0.01 93.89 0.01 97.23 0.18 98.37 0.01 /workspace/coverage/default/13.chip_sw_all_escalation_resets.4130606638
95.06 0.04 94.51 0.01 92.00 0.01 94.13 0.01 93.90 0.01 97.41 0.18 98.38 0.01 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1662795738
95.09 0.04 94.51 0.00 92.22 0.22 94.13 0.00 93.90 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/cover_reg_top/27.chip_tl_errors.477601572
95.12 0.03 94.51 0.00 92.22 0.00 94.32 0.19 93.90 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.263642237
95.15 0.03 94.51 0.00 92.22 0.00 94.50 0.18 93.90 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.62566861
95.18 0.03 94.58 0.07 92.27 0.05 94.52 0.02 93.94 0.03 97.41 0.00 98.38 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3330507120
95.21 0.03 94.62 0.04 92.33 0.05 94.55 0.03 93.98 0.04 97.41 0.00 98.38 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.780477998
95.24 0.03 94.62 0.00 92.33 0.01 94.71 0.16 93.98 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1378083965
95.26 0.03 94.68 0.06 92.36 0.03 94.73 0.02 94.03 0.05 97.41 0.00 98.38 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4112883596
95.29 0.03 94.68 0.00 92.52 0.16 94.73 0.00 94.03 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.4158690164
95.32 0.03 94.68 0.00 92.52 0.00 94.88 0.15 94.03 0.00 97.41 0.00 98.38 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.936279259
95.34 0.03 94.68 0.00 92.58 0.06 94.88 0.00 94.04 0.02 97.41 0.00 98.45 0.07 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4164937325
95.37 0.02 94.71 0.03 92.62 0.04 94.93 0.05 94.07 0.02 97.41 0.00 98.45 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2583997791
95.39 0.02 94.79 0.08 92.62 0.00 94.99 0.06 94.08 0.01 97.41 0.00 98.45 0.00 /workspace/coverage/default/3.chip_tap_straps_testunlock0.659345375
95.41 0.02 94.86 0.07 92.67 0.05 94.99 0.00 94.09 0.02 97.41 0.00 98.45 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3200035131
95.43 0.02 94.86 0.00 92.74 0.06 94.99 0.00 94.11 0.02 97.41 0.00 98.50 0.05 /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3254751476
95.45 0.02 94.86 0.00 92.84 0.10 94.99 0.00 94.11 0.00 97.41 0.00 98.50 0.00 /workspace/coverage/cover_reg_top/3.chip_tl_errors.3834645058
95.47 0.02 94.86 0.00 92.93 0.09 94.99 0.00 94.11 0.00 97.41 0.00 98.50 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.4177159536
95.48 0.01 94.86 0.00 92.94 0.01 94.99 0.00 94.11 0.00 97.41 0.00 98.57 0.07 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3613229246
95.49 0.01 94.86 0.00 92.94 0.00 95.07 0.08 94.11 0.00 97.41 0.00 98.57 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.759418815
95.51 0.01 94.86 0.00 92.94 0.00 95.14 0.07 94.11 0.00 97.41 0.00 98.57 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1395069905
95.52 0.01 94.86 0.00 92.99 0.04 95.14 0.00 94.11 0.00 97.41 0.00 98.59 0.02 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.296546749
95.53 0.01 94.86 0.00 92.99 0.00 95.20 0.05 94.11 0.00 97.41 0.00 98.60 0.01 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1759090232
95.54 0.01 94.86 0.00 93.01 0.02 95.20 0.00 94.13 0.02 97.41 0.00 98.63 0.02 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.651119970
95.55 0.01 94.86 0.00 93.07 0.06 95.20 0.00 94.13 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.1420546821
95.56 0.01 94.88 0.03 93.08 0.01 95.21 0.01 94.14 0.02 97.41 0.00 98.63 0.00 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3181636490
95.57 0.01 94.89 0.01 93.08 0.01 95.23 0.02 94.16 0.02 97.41 0.00 98.63 0.00 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2752295384
95.58 0.01 94.89 0.00 93.08 0.00 95.28 0.05 94.16 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2481966600
95.58 0.01 94.89 0.00 93.14 0.05 95.28 0.00 94.16 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.4244535019
95.59 0.01 94.90 0.01 93.16 0.03 95.28 0.00 94.17 0.01 97.41 0.00 98.63 0.00 /workspace/coverage/cover_reg_top/16.chip_csr_rw.674442605
95.60 0.01 94.90 0.01 93.19 0.03 95.30 0.01 94.17 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3261150424
95.61 0.01 94.91 0.01 93.21 0.01 95.31 0.01 94.17 0.01 97.41 0.00 98.63 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2409846002
95.61 0.01 94.91 0.00 93.25 0.04 95.31 0.00 94.17 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/cover_reg_top/11.chip_tl_errors.1750357722
95.62 0.01 94.92 0.01 93.26 0.01 95.33 0.02 94.17 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1526573670
95.63 0.01 94.92 0.00 93.26 0.00 95.37 0.04 94.17 0.00 97.41 0.00 98.63 0.00 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3928813898
95.63 0.01 94.92 0.00 93.26 0.00 95.37 0.00 94.17 0.00 97.41 0.00 98.66 0.04 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2529974482
95.64 0.01 94.92 0.00 93.26 0.00 95.37 0.00 94.17 0.00 97.41 0.00 98.70 0.04 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.434754558
95.64 0.01 94.92 0.00 93.26 0.00 95.37 0.00 94.17 0.00 97.41 0.00 98.73 0.04 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2919778816
95.65 0.01 94.92 0.00 93.26 0.00 95.40 0.03 94.17 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_kmac_entropy.385635611
95.65 0.01 94.92 0.00 93.26 0.00 95.43 0.03 94.17 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3007613378
95.66 0.01 94.92 0.00 93.26 0.00 95.46 0.03 94.17 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1854210671
95.66 0.01 94.92 0.00 93.27 0.01 95.46 0.00 94.17 0.00 97.41 0.00 98.75 0.02 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1840423108
95.67 0.01 94.92 0.00 93.29 0.03 95.46 0.00 94.17 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/cover_reg_top/10.chip_tl_errors.3254638398
95.67 0.01 94.92 0.00 93.32 0.03 95.46 0.00 94.17 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3813633424
95.68 0.01 94.92 0.00 93.33 0.01 95.46 0.00 94.18 0.01 97.41 0.00 98.75 0.00 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1867393709
95.68 0.01 94.92 0.00 93.35 0.02 95.46 0.00 94.18 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.870707094
95.68 0.01 94.92 0.00 93.37 0.02 95.46 0.00 94.18 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/0.chip_sw_gpio.1135728867
95.69 0.01 94.94 0.02 93.37 0.00 95.46 0.00 94.18 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/0.chip_sw_power_idle_load.3993038675
95.69 0.01 94.94 0.00 93.37 0.00 95.47 0.02 94.18 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2950787103
95.69 0.01 94.94 0.00 93.37 0.00 95.48 0.01 94.18 0.00 97.41 0.00 98.77 0.01 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3448682430
95.70 0.01 94.94 0.00 93.39 0.02 95.48 0.00 94.18 0.00 97.41 0.00 98.77 0.00 /workspace/coverage/cover_reg_top/46.xbar_stress_all.3858318735
95.70 0.01 94.94 0.01 93.41 0.01 95.48 0.00 94.18 0.00 97.41 0.00 98.77 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.750750385
95.70 0.01 94.96 0.01 93.41 0.00 95.49 0.01 94.18 0.00 97.41 0.00 98.77 0.00 /workspace/coverage/default/2.chip_sw_pattgen_ios.3754739447
95.70 0.01 94.96 0.00 93.41 0.01 95.49 0.00 94.18 0.00 97.41 0.00 98.78 0.01 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3647054759
95.71 0.01 94.96 0.00 93.42 0.01 95.49 0.00 94.18 0.00 97.41 0.00 98.78 0.00 /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2167587762
95.71 0.01 94.96 0.00 93.44 0.01 95.49 0.00 94.18 0.00 97.41 0.00 98.78 0.00 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1604961597
95.71 0.01 94.96 0.00 93.45 0.01 95.49 0.00 94.18 0.00 97.41 0.00 98.78 0.00 /workspace/coverage/default/2.chip_sw_gpio.1716894914
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95.89 0.01 95.00 0.00 93.56 0.01 95.61 0.00 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/1.chip_sw_gpio.2173706752
95.89 0.01 95.00 0.00 93.57 0.01 95.61 0.00 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.855684659
95.89 0.01 95.00 0.00 93.57 0.00 95.61 0.01 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.575517722
95.89 0.01 95.00 0.00 93.57 0.00 95.62 0.01 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3210535654
95.89 0.01 95.00 0.00 93.57 0.00 95.62 0.01 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1022539035
95.89 0.01 95.00 0.00 93.57 0.00 95.62 0.01 94.21 0.00 97.41 0.00 99.55 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3939100099


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.605574926
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2304381692
/workspace/coverage/cover_reg_top/0.chip_csr_rw.149029301
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1940409605
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1274127176
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3512537737
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1759922045
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.329280154
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.917737260
/workspace/coverage/cover_reg_top/0.xbar_error_random.2197601331
/workspace/coverage/cover_reg_top/0.xbar_random.2124165330
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2605078735
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1003265263
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3324363996
/workspace/coverage/cover_reg_top/0.xbar_same_source.3950122646
/workspace/coverage/cover_reg_top/0.xbar_smoke.3132422792
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.785946745
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.564681012
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1585656610
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3671833803
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2084111304
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.174840256
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.557683533
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3695153591
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1978392579
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2628819430
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.175663531
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.763224461
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3879256976
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1914359249
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2139286227
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3535026369
/workspace/coverage/cover_reg_top/1.xbar_error_random.1252051475
/workspace/coverage/cover_reg_top/1.xbar_random.3007269352
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1745193921
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3260527723
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3048635507
/workspace/coverage/cover_reg_top/1.xbar_same_source.3426220158
/workspace/coverage/cover_reg_top/1.xbar_smoke.2787990954
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4029793790
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.818029883
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2824627986
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3940415199
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1392869897
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.350140111
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2858397779
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1357231625
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.239997837
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.689796960
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1517183389
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2917988710
/workspace/coverage/cover_reg_top/10.xbar_error_random.876473976
/workspace/coverage/cover_reg_top/10.xbar_random.1914808078
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4185681773
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2782721818
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3073275241
/workspace/coverage/cover_reg_top/10.xbar_same_source.2555216921
/workspace/coverage/cover_reg_top/10.xbar_smoke.1509980712
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3876135998
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1173372180
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3446400995
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1605753651
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2802714231
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2652642590
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3028303344
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1910759637
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2265422679
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3698135741
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1549722166
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2588037973
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1914203206
/workspace/coverage/cover_reg_top/11.xbar_error_random.3630352890
/workspace/coverage/cover_reg_top/11.xbar_random.136177202
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3491980613
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3452887930
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1269699463
/workspace/coverage/cover_reg_top/11.xbar_same_source.3254369265
/workspace/coverage/cover_reg_top/11.xbar_smoke.3878779987
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1337065487
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4024582909
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.187186626
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2126562799
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1985917568
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2867206582
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.71914952
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3219884051
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.662540130
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1220856611
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.4204811084
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1248259192
/workspace/coverage/cover_reg_top/12.xbar_error_random.1676373811
/workspace/coverage/cover_reg_top/12.xbar_random.4079704108
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1543466912
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.970842491
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.7199116
/workspace/coverage/cover_reg_top/12.xbar_same_source.3848583332
/workspace/coverage/cover_reg_top/12.xbar_smoke.523758774
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4034308371
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2768863311
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3646175386
/workspace/coverage/cover_reg_top/12.xbar_stress_all.233079385
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1322941595
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.511452315
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3737475922
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3599037593
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3655086408
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2652701356
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.242421517
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.36117378
/workspace/coverage/cover_reg_top/13.xbar_error_random.1566807764
/workspace/coverage/cover_reg_top/13.xbar_random.509771094
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1736568249
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.733176617
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4152458216
/workspace/coverage/cover_reg_top/13.xbar_same_source.4079129320
/workspace/coverage/cover_reg_top/13.xbar_smoke.3741836762
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2831582536
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3603021268
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.47657585
/workspace/coverage/cover_reg_top/13.xbar_stress_all.853800664
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.977399014
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2433515663
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3859086308
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2232411413
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1368885770
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.469770396
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.624017690
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.769624408
/workspace/coverage/cover_reg_top/14.xbar_error_random.2013465310
/workspace/coverage/cover_reg_top/14.xbar_random.3512948715
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2940653364
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3580506739
/workspace/coverage/cover_reg_top/14.xbar_same_source.3407927230
/workspace/coverage/cover_reg_top/14.xbar_smoke.485930134
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3966467424
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1940592933
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2142369270
/workspace/coverage/cover_reg_top/14.xbar_stress_all.214648700
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2359782230
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1402854546
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1824697029
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2905919359
/workspace/coverage/cover_reg_top/15.chip_csr_rw.361690965
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.286772333
/workspace/coverage/cover_reg_top/15.chip_tl_errors.103304938
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.49493482
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3194512462
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3967435862
/workspace/coverage/cover_reg_top/15.xbar_error_random.1827200530
/workspace/coverage/cover_reg_top/15.xbar_random.3157901680
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1995271684
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.330253037
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2084033537
/workspace/coverage/cover_reg_top/15.xbar_same_source.214392598
/workspace/coverage/cover_reg_top/15.xbar_smoke.3514281782
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2025748754
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1229211918
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2605979635
/workspace/coverage/cover_reg_top/15.xbar_stress_all.276058599
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1776370725
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2281254222
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1380227108
/workspace/coverage/cover_reg_top/16.chip_tl_errors.521609728
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.598901284
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2797355821
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2867509381
/workspace/coverage/cover_reg_top/16.xbar_error_random.1553002275
/workspace/coverage/cover_reg_top/16.xbar_random.1010712548
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1612000127
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4230157645
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.4266369845
/workspace/coverage/cover_reg_top/16.xbar_same_source.893549482
/workspace/coverage/cover_reg_top/16.xbar_smoke.2086712670
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.278573303
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2212693996
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2287502553
/workspace/coverage/cover_reg_top/16.xbar_stress_all.3411596307
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3315019417
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.777872904
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.605536763
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1689405267
/workspace/coverage/cover_reg_top/17.chip_csr_rw.4182808183
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2887717106
/workspace/coverage/cover_reg_top/17.chip_tl_errors.2138219736
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.1856409738
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.228494722
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3949138713
/workspace/coverage/cover_reg_top/17.xbar_error_random.825352149
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2804376863
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1439444819
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3685021811
/workspace/coverage/cover_reg_top/17.xbar_same_source.1590881453
/workspace/coverage/cover_reg_top/17.xbar_smoke.1830377946
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.3567319964
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3171833138
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1500992206
/workspace/coverage/cover_reg_top/17.xbar_stress_all.3621895395
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2674276151
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.286611027
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2268669379
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3587514124
/workspace/coverage/cover_reg_top/18.chip_csr_rw.3000304355
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3351209403
/workspace/coverage/cover_reg_top/18.chip_tl_errors.639555899
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.1431031627
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3001881584
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3363542926
/workspace/coverage/cover_reg_top/18.xbar_error_random.3385369240
/workspace/coverage/cover_reg_top/18.xbar_random.4064357114
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1173732912
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.4100932960
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.743499695
/workspace/coverage/cover_reg_top/18.xbar_same_source.342700670
/workspace/coverage/cover_reg_top/18.xbar_smoke.3827812563
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2732146616
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.4094594446
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.4186300798
/workspace/coverage/cover_reg_top/18.xbar_stress_all.944824471
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3036347659
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2309398198
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2628958430
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1451295305
/workspace/coverage/cover_reg_top/19.chip_csr_rw.3814697277
/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.562142006
/workspace/coverage/cover_reg_top/19.chip_tl_errors.2601570184
/workspace/coverage/cover_reg_top/19.xbar_access_same_device.1177870452
/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2422034793
/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1649021403
/workspace/coverage/cover_reg_top/19.xbar_error_random.3185875666
/workspace/coverage/cover_reg_top/19.xbar_random.1121830737
/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2594171533
/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.4099960325
/workspace/coverage/cover_reg_top/19.xbar_same_source.401910884
/workspace/coverage/cover_reg_top/19.xbar_smoke.1360779845
/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.990149300
/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2934115628
/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.838399587
/workspace/coverage/cover_reg_top/19.xbar_stress_all.1966207578
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1346229989
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.4096128590
/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1904936368
/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.3274807434
/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1539952200
/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.124815224
/workspace/coverage/cover_reg_top/2.chip_csr_rw.4080668769
/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.745325599
/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1883076846
/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3852947662
/workspace/coverage/cover_reg_top/2.chip_tl_errors.2314243038
/workspace/coverage/cover_reg_top/2.xbar_access_same_device.1560646007
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/workspace/coverage/default/85.chip_sw_all_escalation_resets.3246050123
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1573428281
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3292179125
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4115697096
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2346848945
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385880752
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1495805695
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617671493
/workspace/coverage/default/89.chip_sw_all_escalation_resets.356729101
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3744757303
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2417025052
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1628275352
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3471956159
/workspace/coverage/default/91.chip_sw_all_escalation_resets.286194610
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1448888993
/workspace/coverage/default/94.chip_sw_all_escalation_resets.442653409
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2679234984
/workspace/coverage/default/98.chip_sw_all_escalation_resets.629227431
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1738183550
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.811043625
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4014481565
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3915154746
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1991970846
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1319692662
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3163943661
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2310088611
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2776145995




Total test records in report: 2847
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.chip_sw_usbdev_stream.1653901571 Apr 18 04:17:29 PM PDT 24 Apr 18 05:28:39 PM PDT 24 18700500396 ps
T2 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1407530615 Apr 18 04:45:26 PM PDT 24 Apr 18 04:55:23 PM PDT 24 3737177648 ps
T3 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1935295412 Apr 18 04:21:03 PM PDT 24 Apr 18 04:31:51 PM PDT 24 4910085118 ps
T68 /workspace/coverage/default/1.chip_tap_straps_dev.979649149 Apr 18 04:29:33 PM PDT 24 Apr 18 04:49:03 PM PDT 24 9374537914 ps
T85 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2216535181 Apr 18 04:19:15 PM PDT 24 Apr 18 04:35:14 PM PDT 24 4691564308 ps
T29 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3638384296 Apr 18 04:28:25 PM PDT 24 Apr 18 04:49:05 PM PDT 24 11936395448 ps
T86 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1270047660 Apr 18 04:17:34 PM PDT 24 Apr 18 04:27:11 PM PDT 24 5209342640 ps
T58 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2275641399 Apr 18 04:17:34 PM PDT 24 Apr 18 04:28:00 PM PDT 24 3928008130 ps
T87 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.37783062 Apr 18 04:43:25 PM PDT 24 Apr 18 04:47:13 PM PDT 24 2551458696 ps
T88 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.907380151 Apr 18 04:20:42 PM PDT 24 Apr 18 04:32:27 PM PDT 24 3735473585 ps
T4 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1802654967 Apr 18 04:23:18 PM PDT 24 Apr 18 07:30:24 PM PDT 24 58968977100 ps
T172 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.783422832 Apr 18 04:46:17 PM PDT 24 Apr 18 04:53:58 PM PDT 24 3692247136 ps
T5 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4224027286 Apr 18 04:25:23 PM PDT 24 Apr 18 04:27:30 PM PDT 24 3009026463 ps
T128 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.952058827 Apr 18 04:40:14 PM PDT 24 Apr 18 04:53:37 PM PDT 24 4237373120 ps
T63 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2150464878 Apr 18 04:49:41 PM PDT 24 Apr 18 05:00:25 PM PDT 24 5777049800 ps
T10 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.467402960 Apr 18 04:24:29 PM PDT 24 Apr 18 04:33:03 PM PDT 24 4053321238 ps
T64 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1759090232 Apr 18 04:52:53 PM PDT 24 Apr 18 05:00:42 PM PDT 24 5630505074 ps
T125 /workspace/coverage/default/0.chip_sw_edn_auto_mode.628712841 Apr 18 04:20:16 PM PDT 24 Apr 18 04:40:56 PM PDT 24 5239532448 ps
T6 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3866873637 Apr 18 04:16:04 PM PDT 24 Apr 18 05:39:50 PM PDT 24 44611881164 ps
T173 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2623429582 Apr 18 04:49:04 PM PDT 24 Apr 18 05:00:36 PM PDT 24 6115253362 ps
T39 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1378083965 Apr 18 04:25:18 PM PDT 24 Apr 18 05:46:14 PM PDT 24 17743796344 ps
T174 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3448682430 Apr 18 04:52:23 PM PDT 24 Apr 18 05:01:15 PM PDT 24 5224585640 ps
T113 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.40385672 Apr 18 04:19:31 PM PDT 24 Apr 18 04:22:25 PM PDT 24 2482529994 ps
T114 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.937440406 Apr 18 04:28:05 PM PDT 24 Apr 18 04:37:32 PM PDT 24 4277686707 ps
T187 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.965359565 Apr 18 04:50:16 PM PDT 24 Apr 18 04:55:55 PM PDT 24 3162125492 ps
T188 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385880752 Apr 18 04:53:28 PM PDT 24 Apr 18 04:59:40 PM PDT 24 3119740240 ps
T275 /workspace/coverage/default/2.chip_sw_aes_idle.2762518828 Apr 18 04:37:04 PM PDT 24 Apr 18 04:41:54 PM PDT 24 2646905376 ps
T16 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.780477998 Apr 18 04:17:02 PM PDT 24 Apr 18 06:13:02 PM PDT 24 31406134800 ps
T175 /workspace/coverage/default/97.chip_sw_all_escalation_resets.4278184582 Apr 18 04:54:28 PM PDT 24 Apr 18 05:03:28 PM PDT 24 4753952164 ps
T276 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2530023906 Apr 18 04:37:44 PM PDT 24 Apr 18 04:46:25 PM PDT 24 4852559924 ps
T176 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3438125921 Apr 18 04:38:34 PM PDT 24 Apr 18 04:48:42 PM PDT 24 3651067742 ps
T40 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3341350521 Apr 18 04:24:26 PM PDT 24 Apr 18 05:17:05 PM PDT 24 14573008136 ps
T124 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1329648680 Apr 18 04:19:15 PM PDT 24 Apr 18 07:49:25 PM PDT 24 254664152370 ps
T443 /workspace/coverage/default/0.chip_sw_kmac_idle.4267682206 Apr 18 04:18:50 PM PDT 24 Apr 18 04:23:35 PM PDT 24 2938029960 ps
T684 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1917353146 Apr 18 04:18:18 PM PDT 24 Apr 18 04:26:06 PM PDT 24 4758486216 ps
T865 /workspace/coverage/default/0.chip_sw_aes_idle.1846454622 Apr 18 04:17:01 PM PDT 24 Apr 18 04:20:07 PM PDT 24 2198732320 ps
T337 /workspace/coverage/default/91.chip_sw_all_escalation_resets.286194610 Apr 18 04:53:38 PM PDT 24 Apr 18 05:02:06 PM PDT 24 4039012568 ps
T235 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1652710197 Apr 18 04:38:46 PM PDT 24 Apr 18 04:43:22 PM PDT 24 3336272094 ps
T186 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3711994120 Apr 18 04:21:35 PM PDT 24 Apr 18 04:31:11 PM PDT 24 3644755356 ps
T328 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.690514464 Apr 18 04:53:20 PM PDT 24 Apr 18 04:58:55 PM PDT 24 3536632360 ps
T185 /workspace/coverage/default/0.chip_tap_straps_prod.3087381510 Apr 18 04:22:42 PM PDT 24 Apr 18 04:25:38 PM PDT 24 3228646333 ps
T293 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1995643206 Apr 18 04:47:21 PM PDT 24 Apr 18 04:58:48 PM PDT 24 6482520972 ps
T202 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1448888993 Apr 18 04:54:16 PM PDT 24 Apr 18 05:03:27 PM PDT 24 4641287320 ps
T145 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3071307701 Apr 18 04:26:43 PM PDT 24 Apr 18 05:46:32 PM PDT 24 16927371550 ps
T117 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.862208307 Apr 18 04:21:59 PM PDT 24 Apr 18 05:52:04 PM PDT 24 49158534342 ps
T42 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4064216471 Apr 18 04:26:18 PM PDT 24 Apr 18 05:05:09 PM PDT 24 10523483851 ps
T65 /workspace/coverage/default/2.chip_tap_straps_rma.282889376 Apr 18 04:41:09 PM PDT 24 Apr 18 04:47:32 PM PDT 24 4179441413 ps
T335 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2922541069 Apr 18 04:48:38 PM PDT 24 Apr 18 04:58:08 PM PDT 24 4571508604 ps
T167 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.8760112 Apr 18 04:35:59 PM PDT 24 Apr 18 05:00:09 PM PDT 24 8655065444 ps
T69 /workspace/coverage/default/0.chip_tap_straps_dev.3128497192 Apr 18 04:22:33 PM PDT 24 Apr 18 04:39:27 PM PDT 24 9275556203 ps
T47 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2752295384 Apr 18 04:30:07 PM PDT 24 Apr 18 04:36:13 PM PDT 24 4324302104 ps
T422 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4485714 Apr 18 04:27:30 PM PDT 24 Apr 18 04:33:13 PM PDT 24 3127282674 ps
T423 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.966707761 Apr 18 04:19:19 PM PDT 24 Apr 18 04:22:19 PM PDT 24 3305307520 ps
T126 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2536160389 Apr 18 04:19:40 PM PDT 24 Apr 18 04:45:33 PM PDT 24 6344254472 ps
T424 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3471956159 Apr 18 04:53:21 PM PDT 24 Apr 18 05:03:04 PM PDT 24 4898701880 ps
T334 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3246050123 Apr 18 04:53:28 PM PDT 24 Apr 18 05:04:18 PM PDT 24 5366221424 ps
T66 /workspace/coverage/default/3.chip_tap_straps_testunlock0.659345375 Apr 18 04:51:11 PM PDT 24 Apr 18 04:53:53 PM PDT 24 2286426535 ps
T292 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3000771570 Apr 18 04:52:59 PM PDT 24 Apr 18 05:02:09 PM PDT 24 5230604940 ps
T239 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.404033217 Apr 18 04:17:51 PM PDT 24 Apr 18 04:42:28 PM PDT 24 7960126110 ps
T246 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4115380722 Apr 18 04:43:34 PM PDT 24 Apr 18 04:46:59 PM PDT 24 2374339800 ps
T115 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.388993756 Apr 18 04:31:48 PM PDT 24 Apr 18 04:43:28 PM PDT 24 4785581973 ps
T662 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.631337553 Apr 18 04:48:30 PM PDT 24 Apr 18 04:55:21 PM PDT 24 3482127160 ps
T116 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2418555430 Apr 18 04:42:10 PM PDT 24 Apr 18 04:54:24 PM PDT 24 4778934166 ps
T389 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.644180898 Apr 18 04:27:56 PM PDT 24 Apr 18 05:19:29 PM PDT 24 12318457624 ps
T127 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.967984841 Apr 18 04:27:34 PM PDT 24 Apr 18 05:27:14 PM PDT 24 17535656164 ps
T76 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3215683930 Apr 18 04:16:36 PM PDT 24 Apr 18 07:09:39 PM PDT 24 58863309455 ps
T130 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4112883596 Apr 18 04:19:11 PM PDT 24 Apr 18 04:31:54 PM PDT 24 7511772456 ps
T355 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.521444514 Apr 18 04:26:06 PM PDT 24 Apr 18 04:29:44 PM PDT 24 2431228676 ps
T356 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.85799508 Apr 18 04:26:00 PM PDT 24 Apr 18 04:29:35 PM PDT 24 2523934400 ps
T357 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.453130121 Apr 18 04:51:00 PM PDT 24 Apr 18 04:57:58 PM PDT 24 4107541386 ps
T358 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3653991847 Apr 18 04:39:15 PM PDT 24 Apr 18 04:48:08 PM PDT 24 3933824152 ps
T13 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2468009481 Apr 18 04:45:02 PM PDT 24 Apr 18 04:49:14 PM PDT 24 3417065433 ps
T240 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1638234197 Apr 18 04:36:34 PM PDT 24 Apr 18 04:43:45 PM PDT 24 4586201184 ps
T119 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2834915155 Apr 18 04:17:02 PM PDT 24 Apr 18 04:39:50 PM PDT 24 8164205626 ps
T41 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1821588905 Apr 18 04:45:29 PM PDT 24 Apr 18 05:35:28 PM PDT 24 15139456166 ps
T359 /workspace/coverage/default/2.chip_sw_example_manufacturer.3685687268 Apr 18 04:35:06 PM PDT 24 Apr 18 04:38:18 PM PDT 24 2063058040 ps
T118 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.331437194 Apr 18 04:43:44 PM PDT 24 Apr 18 04:50:08 PM PDT 24 6571147143 ps
T112 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4216742959 Apr 18 04:26:45 PM PDT 24 Apr 18 04:38:53 PM PDT 24 4751824596 ps
T339 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4126256373 Apr 18 04:27:06 PM PDT 24 Apr 18 04:32:21 PM PDT 24 3436685419 ps
T168 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3499104576 Apr 18 04:46:09 PM PDT 24 Apr 18 04:58:41 PM PDT 24 10665479684 ps
T663 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.97595075 Apr 18 04:52:03 PM PDT 24 Apr 18 04:57:53 PM PDT 24 3460113160 ps
T671 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.639979798 Apr 18 04:49:50 PM PDT 24 Apr 18 04:55:43 PM PDT 24 3331219628 ps
T146 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.355399781 Apr 18 04:18:17 PM PDT 24 Apr 18 05:16:16 PM PDT 24 17285114360 ps
T442 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2585772291 Apr 18 04:34:57 PM PDT 24 Apr 18 04:46:37 PM PDT 24 5546809480 ps
T163 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3469682619 Apr 18 04:23:15 PM PDT 24 Apr 18 04:37:51 PM PDT 24 7791645184 ps
T670 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762259766 Apr 18 04:53:38 PM PDT 24 Apr 18 04:59:41 PM PDT 24 3971087328 ps
T203 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4234068675 Apr 18 04:51:47 PM PDT 24 Apr 18 04:58:46 PM PDT 24 3777823252 ps
T444 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1243918611 Apr 18 04:37:25 PM PDT 24 Apr 18 04:47:20 PM PDT 24 5589491960 ps
T138 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3181636490 Apr 18 04:43:52 PM PDT 24 Apr 18 04:50:27 PM PDT 24 4912080536 ps
T368 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1355276485 Apr 18 04:44:30 PM PDT 24 Apr 18 04:52:44 PM PDT 24 3572927904 ps
T166 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.263642237 Apr 18 04:31:42 PM PDT 24 Apr 18 05:10:49 PM PDT 24 26163540689 ps
T367 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.428013437 Apr 18 04:24:05 PM PDT 24 Apr 18 04:26:40 PM PDT 24 2603960984 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.741727181 Apr 18 04:26:37 PM PDT 24 Apr 18 04:37:35 PM PDT 24 6547758919 ps
T866 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1628275352 Apr 18 04:44:59 PM PDT 24 Apr 18 04:54:32 PM PDT 24 4237421192 ps
T390 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1480471016 Apr 18 04:24:05 PM PDT 24 Apr 18 05:11:13 PM PDT 24 11914220136 ps
T194 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1052259053 Apr 18 04:45:58 PM PDT 24 Apr 18 05:33:52 PM PDT 24 12536652420 ps
T867 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1476571894 Apr 18 04:41:15 PM PDT 24 Apr 18 04:45:50 PM PDT 24 3202836180 ps
T110 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1698823342 Apr 18 04:41:54 PM PDT 24 Apr 18 05:28:02 PM PDT 24 15273230881 ps
T391 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1754294205 Apr 18 04:26:02 PM PDT 24 Apr 18 05:26:32 PM PDT 24 15238957748 ps
T868 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3862663969 Apr 18 04:39:09 PM PDT 24 Apr 18 04:43:34 PM PDT 24 3592327792 ps
T869 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3517737772 Apr 18 04:39:31 PM PDT 24 Apr 18 04:49:45 PM PDT 24 4164363082 ps
T14 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2583997791 Apr 18 04:17:49 PM PDT 24 Apr 18 04:28:09 PM PDT 24 3654073970 ps
T445 /workspace/coverage/default/1.chip_sw_otbn_randomness.1615786311 Apr 18 04:27:16 PM PDT 24 Apr 18 04:45:02 PM PDT 24 5894150204 ps
T230 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2137338749 Apr 18 04:47:52 PM PDT 24 Apr 18 04:59:34 PM PDT 24 6139557740 ps
T249 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.440369167 Apr 18 04:50:33 PM PDT 24 Apr 18 04:56:29 PM PDT 24 4039810450 ps
T131 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3324510836 Apr 18 04:29:27 PM PDT 24 Apr 18 04:47:23 PM PDT 24 6830711052 ps
T67 /workspace/coverage/default/1.chip_tap_straps_rma.3522208252 Apr 18 04:30:41 PM PDT 24 Apr 18 04:47:30 PM PDT 24 8926298777 ps
T169 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3342188559 Apr 18 04:45:44 PM PDT 24 Apr 18 04:59:26 PM PDT 24 12069406798 ps
T250 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1187445061 Apr 18 04:26:52 PM PDT 24 Apr 18 05:17:59 PM PDT 24 15607198840 ps
T251 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2537922460 Apr 18 04:34:37 PM PDT 24 Apr 18 04:41:15 PM PDT 24 3511223826 ps
T252 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.364188498 Apr 18 04:28:34 PM PDT 24 Apr 18 04:33:16 PM PDT 24 2484159390 ps
T253 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.575517722 Apr 18 04:19:35 PM PDT 24 Apr 18 04:26:43 PM PDT 24 5769521852 ps
T120 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.635617542 Apr 18 04:35:53 PM PDT 24 Apr 18 05:08:45 PM PDT 24 8947173567 ps
T870 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3021606463 Apr 18 04:24:08 PM PDT 24 Apr 18 04:34:22 PM PDT 24 4568766000 ps
T12 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1893725778 Apr 18 04:34:41 PM PDT 24 Apr 18 04:39:40 PM PDT 24 2672134680 ps
T516 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2981535312 Apr 18 04:38:25 PM PDT 24 Apr 18 04:53:44 PM PDT 24 4872859752 ps
T871 /workspace/coverage/default/0.chip_sw_otbn_randomness.3968315186 Apr 18 04:19:21 PM PDT 24 Apr 18 04:34:21 PM PDT 24 5936631676 ps
T342 /workspace/coverage/default/89.chip_sw_all_escalation_resets.356729101 Apr 18 04:54:13 PM PDT 24 Apr 18 05:06:26 PM PDT 24 5665543136 ps
T295 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.618398547 Apr 18 04:19:36 PM PDT 24 Apr 18 04:40:14 PM PDT 24 8964261930 ps
T43 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3330507120 Apr 18 04:18:40 PM PDT 24 Apr 18 04:26:35 PM PDT 24 5195883760 ps
T101 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2391854754 Apr 18 04:18:23 PM PDT 24 Apr 18 04:23:26 PM PDT 24 2859611790 ps
T102 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3876502560 Apr 18 04:16:42 PM PDT 24 Apr 18 05:04:46 PM PDT 24 34307526816 ps
T103 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1544594486 Apr 18 04:29:45 PM PDT 24 Apr 18 04:35:52 PM PDT 24 2934943485 ps
T104 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1662217483 Apr 18 04:34:12 PM PDT 24 Apr 18 04:45:37 PM PDT 24 5434014860 ps
T105 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3862316830 Apr 18 04:49:17 PM PDT 24 Apr 18 04:55:34 PM PDT 24 3626288940 ps
T106 /workspace/coverage/default/3.chip_sw_all_escalation_resets.370395572 Apr 18 04:51:59 PM PDT 24 Apr 18 04:59:31 PM PDT 24 4610095752 ps
T81 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2051754004 Apr 18 04:26:45 PM PDT 24 Apr 18 08:13:14 PM PDT 24 255762549420 ps
T107 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4232649298 Apr 18 04:28:28 PM PDT 24 Apr 18 05:14:00 PM PDT 24 14553666090 ps
T15 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2119785620 Apr 18 04:21:54 PM PDT 24 Apr 18 04:32:34 PM PDT 24 4638286568 ps
T19 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1627456421 Apr 18 04:24:10 PM PDT 24 Apr 18 05:14:17 PM PDT 24 20890496774 ps
T364 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3726533249 Apr 18 04:52:27 PM PDT 24 Apr 18 04:59:45 PM PDT 24 3384743524 ps
T365 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4141041722 Apr 18 04:49:31 PM PDT 24 Apr 18 04:54:04 PM PDT 24 3087630400 ps
T17 /workspace/coverage/default/0.chip_sw_usbdev_vbus.2160685736 Apr 18 04:18:40 PM PDT 24 Apr 18 04:22:34 PM PDT 24 2686316492 ps
T366 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.855044291 Apr 18 04:43:21 PM PDT 24 Apr 18 04:48:37 PM PDT 24 3285662256 ps
T206 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1824309732 Apr 18 04:38:07 PM PDT 24 Apr 18 04:46:26 PM PDT 24 5411873143 ps
T872 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.873837884 Apr 18 04:25:25 PM PDT 24 Apr 18 04:28:49 PM PDT 24 3173452048 ps
T873 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3648960866 Apr 18 04:25:40 PM PDT 24 Apr 18 05:26:06 PM PDT 24 15208340723 ps
T874 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3305386002 Apr 18 04:18:21 PM PDT 24 Apr 18 04:29:00 PM PDT 24 4638145744 ps
T321 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.196334057 Apr 18 04:25:11 PM PDT 24 Apr 18 04:28:57 PM PDT 24 2729249752 ps
T373 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2072814711 Apr 18 04:25:35 PM PDT 24 Apr 18 05:23:37 PM PDT 24 14033613444 ps
T200 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1239318095 Apr 18 04:39:16 PM PDT 24 Apr 18 05:18:02 PM PDT 24 21201374640 ps
T254 /workspace/coverage/default/0.rom_volatile_raw_unlock.2019505036 Apr 18 04:26:03 PM PDT 24 Apr 18 04:27:41 PM PDT 24 2289596329 ps
T155 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3776037633 Apr 18 04:17:56 PM PDT 24 Apr 18 04:54:05 PM PDT 24 10720960318 ps
T668 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1218922108 Apr 18 04:30:39 PM PDT 24 Apr 18 04:37:10 PM PDT 24 3459433160 ps
T32 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3790033262 Apr 18 04:26:21 PM PDT 24 Apr 18 04:36:24 PM PDT 24 5528875288 ps
T77 /workspace/coverage/default/0.chip_jtag_mem_access.1435325901 Apr 18 04:11:15 PM PDT 24 Apr 18 04:35:29 PM PDT 24 13311620288 ps
T429 /workspace/coverage/default/1.chip_sw_kmac_app_rom.106839249 Apr 18 04:29:42 PM PDT 24 Apr 18 04:32:52 PM PDT 24 1918702422 ps
T255 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3229503135 Apr 18 04:24:51 PM PDT 24 Apr 18 05:23:04 PM PDT 24 14855759744 ps
T121 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2280264067 Apr 18 04:28:52 PM PDT 24 Apr 18 04:37:58 PM PDT 24 4337033100 ps
T149 /workspace/coverage/default/1.chip_plic_all_irqs_10.2235182108 Apr 18 04:29:12 PM PDT 24 Apr 18 04:39:32 PM PDT 24 3503191468 ps
T344 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1935061963 Apr 18 04:22:28 PM PDT 24 Apr 18 04:27:39 PM PDT 24 3576642632 ps
T122 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.302347024 Apr 18 04:21:51 PM PDT 24 Apr 18 04:31:59 PM PDT 24 4361245620 ps
T204 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.121150855 Apr 18 04:28:38 PM PDT 24 Apr 18 05:19:34 PM PDT 24 11134213672 ps
T219 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1072010097 Apr 18 04:36:52 PM PDT 24 Apr 18 06:10:38 PM PDT 24 50136698227 ps
T875 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3504857203 Apr 18 04:38:29 PM PDT 24 Apr 18 04:45:15 PM PDT 24 4101682202 ps
T215 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2523782263 Apr 18 04:20:26 PM PDT 24 Apr 18 04:44:31 PM PDT 24 7328960196 ps
T876 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2033234597 Apr 18 04:44:17 PM PDT 24 Apr 18 04:54:37 PM PDT 24 3764208140 ps
T647 /workspace/coverage/default/25.chip_sw_all_escalation_resets.531590453 Apr 18 04:48:25 PM PDT 24 Apr 18 05:00:37 PM PDT 24 5205156100 ps
T877 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2494850060 Apr 18 04:24:43 PM PDT 24 Apr 18 05:20:21 PM PDT 24 12638786196 ps
T878 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2565990800 Apr 18 04:40:47 PM PDT 24 Apr 18 04:45:19 PM PDT 24 2691399502 ps
T879 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4000354983 Apr 18 04:30:36 PM PDT 24 Apr 18 04:33:50 PM PDT 24 2583879093 ps
T220 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.759418815 Apr 18 04:23:16 PM PDT 24 Apr 18 05:54:53 PM PDT 24 50652496600 ps
T256 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.265864441 Apr 18 04:26:15 PM PDT 24 Apr 18 05:05:27 PM PDT 24 10629556398 ps
T294 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2512739207 Apr 18 04:37:16 PM PDT 24 Apr 18 05:07:02 PM PDT 24 7141549608 ps
T880 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2195123833 Apr 18 04:45:53 PM PDT 24 Apr 18 05:31:06 PM PDT 24 13209195920 ps
T881 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3934713066 Apr 18 04:37:35 PM PDT 24 Apr 18 05:47:56 PM PDT 24 14683206848 ps
T882 /workspace/coverage/default/1.chip_sw_aes_smoketest.2888573233 Apr 18 04:33:09 PM PDT 24 Apr 18 04:38:06 PM PDT 24 2577946010 ps
T269 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.747525967 Apr 18 04:22:07 PM PDT 24 Apr 18 04:30:50 PM PDT 24 4914919448 ps
T666 /workspace/coverage/default/27.chip_sw_all_escalation_resets.4126563630 Apr 18 04:47:54 PM PDT 24 Apr 18 04:58:01 PM PDT 24 4978898692 ps
T669 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.446814113 Apr 18 04:31:50 PM PDT 24 Apr 18 04:48:10 PM PDT 24 7839871766 ps
T883 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3220083193 Apr 18 04:43:22 PM PDT 24 Apr 18 04:48:02 PM PDT 24 3258940746 ps
T177 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2612855873 Apr 18 04:19:52 PM PDT 24 Apr 18 04:23:41 PM PDT 24 2554542968 ps
T284 /workspace/coverage/default/2.chip_plic_all_irqs_0.2760600197 Apr 18 04:41:04 PM PDT 24 Apr 18 04:57:08 PM PDT 24 5990071368 ps
T285 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4178645288 Apr 18 04:38:48 PM PDT 24 Apr 18 04:42:57 PM PDT 24 2253917166 ps
T286 /workspace/coverage/default/3.chip_tap_straps_prod.2861612551 Apr 18 04:43:04 PM PDT 24 Apr 18 04:45:40 PM PDT 24 2703158197 ps
T287 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4226653071 Apr 18 04:31:04 PM PDT 24 Apr 18 04:35:35 PM PDT 24 2827434918 ps
T270 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1218715427 Apr 18 04:19:45 PM PDT 24 Apr 18 04:32:39 PM PDT 24 3766342080 ps
T288 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.28161196 Apr 18 04:45:56 PM PDT 24 Apr 18 04:49:49 PM PDT 24 2650120751 ps
T289 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1416152338 Apr 18 04:36:05 PM PDT 24 Apr 18 05:31:38 PM PDT 24 15512633800 ps
T221 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2122535368 Apr 18 04:35:30 PM PDT 24 Apr 18 06:06:05 PM PDT 24 50974600932 ps
T290 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739893054 Apr 18 04:38:51 PM PDT 24 Apr 18 04:44:44 PM PDT 24 3675457928 ps
T309 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1943481136 Apr 18 04:18:40 PM PDT 24 Apr 18 04:31:29 PM PDT 24 4408148960 ps
T229 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1098332193 Apr 18 04:35:28 PM PDT 24 Apr 18 04:59:01 PM PDT 24 7163700448 ps
T30 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1228605571 Apr 18 04:15:54 PM PDT 24 Apr 18 04:19:29 PM PDT 24 2591053694 ps
T712 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.504839391 Apr 18 04:52:41 PM PDT 24 Apr 18 04:58:52 PM PDT 24 4304715898 ps
T325 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1526573670 Apr 18 04:36:25 PM PDT 24 Apr 18 05:05:14 PM PDT 24 13963416640 ps
T191 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1779382639 Apr 18 04:35:53 PM PDT 24 Apr 18 04:52:05 PM PDT 24 6027573118 ps
T884 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2311772859 Apr 18 04:47:02 PM PDT 24 Apr 18 05:23:43 PM PDT 24 12893995964 ps
T885 /workspace/coverage/default/2.chip_sw_otbn_randomness.2365300114 Apr 18 04:37:18 PM PDT 24 Apr 18 04:54:17 PM PDT 24 5941433228 ps
T207 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1143309326 Apr 18 04:37:24 PM PDT 24 Apr 18 04:46:15 PM PDT 24 4895643612 ps
T326 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2527644478 Apr 18 04:35:34 PM PDT 24 Apr 18 05:20:47 PM PDT 24 37284206590 ps
T322 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3881107868 Apr 18 04:32:40 PM PDT 24 Apr 18 04:37:04 PM PDT 24 2301690362 ps
T664 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231876131 Apr 18 04:51:02 PM PDT 24 Apr 18 04:59:28 PM PDT 24 3522342728 ps
T241 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.609275699 Apr 18 04:23:11 PM PDT 24 Apr 18 04:31:22 PM PDT 24 4547530502 ps
T886 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.280224890 Apr 18 04:34:35 PM PDT 24 Apr 18 04:45:33 PM PDT 24 4317609170 ps
T887 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3287094412 Apr 18 04:17:02 PM PDT 24 Apr 18 04:33:18 PM PDT 24 13005979515 ps
T340 /workspace/coverage/default/2.chip_sw_hmac_enc.683079150 Apr 18 04:38:48 PM PDT 24 Apr 18 04:43:24 PM PDT 24 2747986700 ps
T170 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.761289178 Apr 18 04:35:19 PM PDT 24 Apr 18 04:39:10 PM PDT 24 3087188232 ps
T665 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261077557 Apr 18 04:47:31 PM PDT 24 Apr 18 04:55:51 PM PDT 24 3888429476 ps
T156 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2833289047 Apr 18 04:49:46 PM PDT 24 Apr 18 04:57:36 PM PDT 24 3628061750 ps
T888 /workspace/coverage/default/1.chip_sw_csrng_kat_test.758642760 Apr 18 04:26:26 PM PDT 24 Apr 18 04:30:54 PM PDT 24 2623517462 ps
T336 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3089359506 Apr 18 04:46:54 PM PDT 24 Apr 18 04:54:52 PM PDT 24 4507590970 ps
T20 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1095279703 Apr 18 04:37:13 PM PDT 24 Apr 18 05:29:25 PM PDT 24 20385718728 ps
T889 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1010198512 Apr 18 04:24:14 PM PDT 24 Apr 18 04:30:41 PM PDT 24 4700392856 ps
T721 /workspace/coverage/default/79.chip_sw_all_escalation_resets.4073478773 Apr 18 04:51:32 PM PDT 24 Apr 18 05:00:03 PM PDT 24 5848046264 ps
T441 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2155598767 Apr 18 04:44:01 PM PDT 24 Apr 18 04:52:39 PM PDT 24 4292723040 ps
T327 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3479348294 Apr 18 04:45:39 PM PDT 24 Apr 18 04:55:02 PM PDT 24 4765910194 ps
T178 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2351737723 Apr 18 04:29:18 PM PDT 24 Apr 18 04:45:01 PM PDT 24 6858235538 ps
T78 /workspace/coverage/default/2.chip_jtag_csr_rw.3942558052 Apr 18 04:32:25 PM PDT 24 Apr 18 04:52:22 PM PDT 24 11272944042 ps
T890 /workspace/coverage/default/4.chip_tap_straps_dev.3798879386 Apr 18 04:43:34 PM PDT 24 Apr 18 05:08:09 PM PDT 24 14841203460 ps
T22 /workspace/coverage/default/1.chip_sw_gpio.2173706752 Apr 18 04:23:29 PM PDT 24 Apr 18 04:32:10 PM PDT 24 3783885677 ps
T708 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1696249279 Apr 18 04:39:55 PM PDT 24 Apr 18 04:53:23 PM PDT 24 6579072790 ps
T244 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1808207618 Apr 18 04:53:32 PM PDT 24 Apr 18 05:02:29 PM PDT 24 5481884776 ps
T296 /workspace/coverage/default/1.chip_plic_all_irqs_20.662312789 Apr 18 04:29:00 PM PDT 24 Apr 18 04:41:55 PM PDT 24 4643320084 ps
T18 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1083455399 Apr 18 04:17:08 PM PDT 24 Apr 18 04:48:46 PM PDT 24 8035244204 ps
T891 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1779289899 Apr 18 04:25:14 PM PDT 24 Apr 18 04:35:45 PM PDT 24 4917143020 ps
T892 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2328760672 Apr 18 04:22:41 PM PDT 24 Apr 18 04:28:03 PM PDT 24 3304212590 ps
T689 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2279134720 Apr 18 04:37:12 PM PDT 24 Apr 18 04:47:23 PM PDT 24 7676511240 ps
T893 /workspace/coverage/default/0.chip_sw_uart_smoketest.4145606760 Apr 18 04:24:38 PM PDT 24 Apr 18 04:29:03 PM PDT 24 2764497260 ps
T157 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1470990146 Apr 18 04:44:48 PM PDT 24 Apr 18 04:57:50 PM PDT 24 5522883018 ps
T894 /workspace/coverage/default/0.chip_sw_kmac_entropy.385635611 Apr 18 04:18:03 PM PDT 24 Apr 18 04:23:17 PM PDT 24 2880217880 ps
T123 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3007613378 Apr 18 04:19:29 PM PDT 24 Apr 18 04:26:48 PM PDT 24 3683873490 ps
T751 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3823898751 Apr 18 04:46:19 PM PDT 24 Apr 18 04:52:13 PM PDT 24 2909907908 ps
T895 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3801399003 Apr 18 04:21:27 PM PDT 24 Apr 18 04:25:45 PM PDT 24 3098036050 ps
T896 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.970709149 Apr 18 04:30:15 PM PDT 24 Apr 18 04:34:04 PM PDT 24 2380227047 ps
T897 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2092763925 Apr 18 04:29:26 PM PDT 24 Apr 18 04:38:38 PM PDT 24 4003598868 ps
T440 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.749302830 Apr 18 04:31:50 PM PDT 24 Apr 18 04:55:20 PM PDT 24 5286660352 ps
T711 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2957811490 Apr 18 04:45:33 PM PDT 24 Apr 18 04:55:41 PM PDT 24 5728654840 ps
T898 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.321868474 Apr 18 04:43:42 PM PDT 24 Apr 18 04:46:53 PM PDT 24 2502444380 ps
T23 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3160507120 Apr 18 04:33:29 PM PDT 24 Apr 18 04:37:42 PM PDT 24 2847009744 ps
T108 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3373580790 Apr 18 04:32:36 PM PDT 24 Apr 18 05:08:01 PM PDT 24 16352729770 ps
T899 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1599791360 Apr 18 04:35:47 PM PDT 24 Apr 18 05:14:16 PM PDT 24 21384251856 ps
T433 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4115697096 Apr 18 04:52:36 PM PDT 24 Apr 18 04:59:15 PM PDT 24 3756750646 ps
T900 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2735169865 Apr 18 04:24:05 PM PDT 24 Apr 18 04:36:57 PM PDT 24 7822075793 ps
T237 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3084054351 Apr 18 04:20:36 PM PDT 24 Apr 18 04:23:32 PM PDT 24 2516706328 ps
T44 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3425936577 Apr 18 04:40:40 PM PDT 24 Apr 18 05:04:48 PM PDT 24 21248512980 ps
T398 /workspace/coverage/default/1.chip_sw_hmac_enc.1586347085 Apr 18 04:27:03 PM PDT 24 Apr 18 04:31:31 PM PDT 24 2150402588 ps
T82 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.912140473 Apr 18 04:26:20 PM PDT 24 Apr 18 04:51:07 PM PDT 24 9224785448 ps
T399 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4044819632 Apr 18 04:26:33 PM PDT 24 Apr 18 05:47:33 PM PDT 24 17679422139 ps
T400 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3692344764 Apr 18 04:28:59 PM PDT 24 Apr 18 05:12:34 PM PDT 24 12140265640 ps
T401 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2517143426 Apr 18 04:29:34 PM PDT 24 Apr 18 04:38:55 PM PDT 24 3489794744 ps
T402 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3204676904 Apr 18 04:51:52 PM PDT 24 Apr 18 04:58:03 PM PDT 24 3998158082 ps
T403 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1992936185 Apr 18 04:47:35 PM PDT 24 Apr 18 04:59:02 PM PDT 24 5591503096 ps
T404 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.567543987 Apr 18 04:49:26 PM PDT 24 Apr 18 04:57:43 PM PDT 24 4101868332 ps
T109 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3362723659 Apr 18 04:19:02 PM PDT 24 Apr 18 04:25:44 PM PDT 24 18494812090 ps
T152 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4234837243 Apr 18 04:18:29 PM PDT 24 Apr 18 04:29:24 PM PDT 24 6297142570 ps
T901 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4091983086 Apr 18 04:45:30 PM PDT 24 Apr 18 05:23:29 PM PDT 24 12840193240 ps
T297 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3930933492 Apr 18 04:50:40 PM PDT 24 Apr 18 04:58:22 PM PDT 24 3569163736 ps
T158 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.318425935 Apr 18 04:53:11 PM PDT 24 Apr 18 04:59:58 PM PDT 24 3286062638 ps
T141 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3580337567 Apr 18 04:23:45 PM PDT 24 Apr 18 04:30:13 PM PDT 24 8753343252 ps
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