Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136172	1			T73	44		T75	20		T80	87
values[2]	9063	1			T129	1		T420	6		T506	1
values[3]	3503	1			T447	20		T496	1		T411	105
values[4]	2038	1			T447	10		T411	40		T613	15
values[5]	1301	1			T447	19		T411	14		T613	3
values[6]	940	1			T447	17		T411	5		T790	2
values[7]	656	1			T447	12		T411	5		T790	2
values[8]	445	1			T447	16		T790	2		T550	7
values[9]	428	1			T447	13		T790	2		T550	5
values[10]	341	1			T447	16		T790	2		T550	3
values[11]	303	1			T447	15		T790	2		T550	3
values[12]	250	1			T447	6		T790	2		T550	4
values[13]	272	1			T447	5		T790	2		T550	8
values[14]	274	1			T447	4		T790	2		T550	3
values[15]	250	1			T447	3		T790	2		T550	2
values[16]	273	1			T447	3		T790	2		T550	6
values[17]	252	1			T447	4		T790	2		T550	7
values[18]	240	1			T447	3		T790	2		T550	4
values[19]	247	1			T447	1		T790	2		T550	4
values[20]	293	1			T447	2		T790	2		T550	1
values[21]	273	1			T447	3		T790	2		T405	3
values[22]	348	1			T447	2		T790	2		T405	13
values[23]	258	1			T447	2		T790	2		T405	4
values[24]	241	1			T447	2		T790	2		T405	12
values[25]	262	1			T447	1		T790	2		T405	16
values[26]	239	1			T447	3		T790	2		T405	4
values[27]	228	1			T447	1		T790	2		T405	7
values[28]	225	1			T447	4		T790	2		T405	7
values[29]	295	1			T447	4		T790	2		T405	2
values[30]	264	1			T447	3		T790	2		T405	5
values[31]	279	1			T447	3		T790	2		T405	4
values[32]	260	1			T447	1		T790	2		T405	3
values[33]	206	1			T447	3		T790	2		T405	8
values[34]	231	1			T447	1		T790	2		T405	4
values[35]	250	1			T447	6		T790	2		T405	15
values[36]	241	1			T447	2		T790	2		T405	22
values[37]	227	1			T447	3		T790	2		T405	4
values[38]	235	1			T447	1		T790	2		T405	3
values[39]	266	1			T447	3		T790	2		T405	7
values[40]	254	1			T447	1		T790	2		T405	13
values[41]	261	1			T447	7		T790	2		T405	3
values[42]	255	1			T447	3		T790	2		T405	3
values[43]	226	1			T447	1		T790	2		T405	5
values[44]	217	1			T447	3		T790	2		T405	8
values[45]	241	1			T447	4		T790	2		T405	3
values[46]	268	1			T447	5		T790	2		T405	12
values[47]	221	1			T447	1		T790	2		T405	7
values[48]	247	1			T447	2		T790	2		T405	7
values[49]	246	1			T447	1		T790	2		T405	11
values[50]	250	1			T447	1		T790	2		T405	6
values[51]	253	1			T447	3		T790	2		T646	8
values[52]	202	1			T447	3		T790	2		T646	6
values[53]	214	1			T447	2		T790	2		T646	4
values[54]	175	1			T447	1		T790	2		T646	9
values[55]	184	1			T447	1		T790	2		T646	7
values[56]	169	1			T447	8		T790	2		T646	11
values[57]	196	1			T447	2		T790	2		T646	5
values[58]	212	1			T447	1		T790	2		T646	3
values[59]	211	1			T447	1		T790	2		T646	3
values[60]	174	1			T447	1		T790	2		T646	6
values[61]	171	1			T447	8		T790	2		T646	5
values[62]	186	1			T447	5		T790	2		T646	14
values[63]	183	1			T447	9		T790	2		T646	14
values[64]	181	1			T447	2		T790	2		T646	3
values[65]	175	1			T447	9		T790	2		T646	7
values[66]	185	1			T447	5		T790	2		T646	6
values[67]	188	1			T447	1		T790	2		T646	4
values[68]	175	1			T447	4		T790	2		T817	16
values[69]	162	1			T447	1		T790	2		T817	14
values[70]	142	1			T447	2		T790	2		T817	5
values[71]	147	1			T447	1		T790	2		T817	4
values[72]	134	1			T447	2		T790	2		T806	8
values[73]	176	1			T447	2		T790	2		T806	20
values[74]	143	1			T447	1		T790	2		T806	14
values[75]	112	1			T447	1		T790	2		T806	6
values[76]	122	1			T447	6		T790	2		T806	26
values[77]	159	1			T447	4		T790	2		T806	28
values[78]	153	1			T447	10		T790	2		T806	15
values[79]	135	1			T447	16		T790	2		T806	12
values[80]	144	1			T447	11		T790	2		T806	21
values[81]	128	1			T447	7		T790	2		T806	17
values[82]	112	1			T447	6		T790	2		T806	4
values[83]	131	1			T447	5		T790	2		T806	5
values[84]	116	1			T447	4		T790	2		T806	4
values[85]	129	1			T447	5		T790	2		T806	4
values[86]	138	1			T447	12		T790	2		T806	3
values[87]	126	1			T447	5		T790	2		T806	12
values[88]	135	1			T447	3		T790	2		T806	9
values[89]	143	1			T447	6		T790	2		T806	5
values[90]	140	1			T447	3		T790	2		T806	2
values[91]	137	1			T447	9		T790	2		T806	3
values[92]	140	1			T447	7		T790	2		T806	5
values[93]	108	1			T447	5		T790	2		T806	2
values[94]	102	1			T447	7		T790	2		T806	4
values[95]	88	1			T447	1		T790	2		T806	4
values[96]	83	1			T447	7		T790	2		T806	2
values[97]	73	1			T447	5		T790	2		T806	8
values[98]	95	1			T447	4		T790	2		T806	11
values[99]	77	1			T447	3		T790	2		T806	8
values[100]	85	1			T447	6		T790	2		T806	4
values[101]	95	1			T447	4		T790	2		T806	5
values[102]	93	1			T447	4		T790	3		T806	2
values[103]	85	1			T447	2		T790	2		T806	4
values[104]	75	1			T447	4		T790	2		T806	3
values[105]	83	1			T447	4		T790	2		T806	2
values[106]	87	1			T447	4		T790	3		T806	2
values[107]	95	1			T447	2		T790	2		T806	1
values[108]	77	1			T447	3		T790	2		T825	2
values[109]	81	1			T447	8		T790	2		T825	6
values[110]	66	1			T447	8		T790	2		T825	4
values[111]	95	1			T447	4		T790	2		T825	9
values[112]	71	1			T447	4		T790	2		T825	6
values[113]	66	1			T447	4		T790	2		T825	4
values[114]	51	1			T447	2		T790	3		T825	3
values[115]	76	1			T447	2		T790	4		T825	6
values[116]	79	1			T447	4		T790	4		T825	2
values[117]	82	1			T447	8		T790	2		T825	4
values[118]	50	1			T447	7		T790	2		T825	3
values[119]	51	1			T447	3		T790	4		T825	3
values[120]	58	1			T447	3		T790	3		T825	3
values[121]	51	1			T447	4		T790	3		T825	6
values[122]	57	1			T447	4		T790	2		T825	3
values[123]	51	1			T447	2		T790	3		T825	1
values[124]	49	1			T447	7		T790	7		T826	7
values[125]	40	1			T447	8		T790	5		T826	4
values[126]	63	1			T447	23		T790	5		T826	10
values[127]	585	1			T447	40		T790	62		T826	61
values[128]	5446	1			T447	28		T790	566		T826	613