Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137744	1			T73	35		T75	14		T80	79
values[2]	10553	1			T420	6		T519	2		T447	7
values[3]	4517	1			T420	2		T419	92		T411	84
values[4]	2533	1			T419	53		T411	73		T613	60
values[5]	1514	1			T419	18		T411	75		T613	22
values[6]	993	1			T419	10		T411	36		T613	7
values[7]	633	1			T419	11		T411	6		T613	2
values[8]	597	1			T419	13		T613	1		T448	35
values[9]	439	1			T419	6		T448	22		T405	17
values[10]	344	1			T448	9		T405	11		T486	2
values[11]	299	1			T448	3		T405	8		T486	4
values[12]	246	1			T448	1		T405	6		T486	14
values[13]	267	1			T405	6		T486	12		T452	11
values[14]	232	1			T405	6		T486	12		T452	3
values[15]	236	1			T405	8		T486	3		T452	8
values[16]	237	1			T405	5		T486	3		T452	19
values[17]	233	1			T405	8		T486	3		T452	5
values[18]	224	1			T405	13		T486	2		T452	7
values[19]	212	1			T405	5		T486	7		T452	6
values[20]	204	1			T405	5		T486	4		T452	5
values[21]	220	1			T405	8		T486	10		T452	6
values[22]	191	1			T405	9		T486	7		T452	4
values[23]	220	1			T405	11		T486	4		T452	11
values[24]	209	1			T405	7		T486	4		T452	7
values[25]	269	1			T405	15		T486	10		T452	7
values[26]	239	1			T405	12		T486	4		T452	5
values[27]	271	1			T405	5		T486	6		T452	16
values[28]	223	1			T405	7		T486	1		T452	7
values[29]	231	1			T405	7		T486	5		T452	6
values[30]	224	1			T405	5		T486	1		T452	11
values[31]	231	1			T405	3		T486	5		T452	4
values[32]	205	1			T405	3		T486	5		T452	5
values[33]	204	1			T405	4		T486	8		T452	9
values[34]	182	1			T405	7		T486	1		T452	6
values[35]	228	1			T405	18		T486	4		T452	7
values[36]	202	1			T405	11		T486	2		T452	3
values[37]	192	1			T405	5		T486	1		T452	4
values[38]	247	1			T405	10		T486	1		T452	6
values[39]	229	1			T405	3		T486	4		T452	9
values[40]	204	1			T405	8		T486	6		T452	7
values[41]	212	1			T405	5		T486	4		T452	8
values[42]	203	1			T405	6		T486	5		T452	5
values[43]	231	1			T405	7		T486	2		T452	7
values[44]	256	1			T405	3		T486	3		T452	3
values[45]	209	1			T486	2		T452	11		T454	6
values[46]	191	1			T486	2		T452	3		T454	4
values[47]	203	1			T486	3		T452	2		T454	11
values[48]	190	1			T486	2		T452	5		T454	12
values[49]	217	1			T486	2		T452	7		T454	6
values[50]	159	1			T486	2		T452	5		T454	7
values[51]	184	1			T486	1		T452	9		T454	4
values[52]	186	1			T486	4		T452	9		T454	5
values[53]	186	1			T486	5		T452	8		T454	8
values[54]	177	1			T486	2		T452	4		T454	6
values[55]	196	1			T486	2		T452	9		T454	6
values[56]	205	1			T486	1		T452	9		T454	8
values[57]	157	1			T486	1		T452	8		T454	11
values[58]	163	1			T486	6		T452	4		T454	11
values[59]	159	1			T486	2		T452	4		T454	11
values[60]	171	1			T486	3		T452	9		T454	15
values[61]	147	1			T486	2		T452	8		T454	11
values[62]	146	1			T486	2		T452	4		T454	15
values[63]	144	1			T486	8		T452	6		T454	15
values[64]	165	1			T486	10		T452	3		T454	8
values[65]	146	1			T486	7		T452	5		T454	7
values[66]	138	1			T486	2		T452	8		T454	3
values[67]	139	1			T486	3		T452	8		T454	5
values[68]	130	1			T486	3		T452	8		T454	6
values[69]	122	1			T486	3		T452	10		T454	4
values[70]	119	1			T486	2		T452	4		T454	6
values[71]	113	1			T486	2		T452	8		T454	6
values[72]	81	1			T486	1		T452	5		T454	5
values[73]	70	1			T486	1		T452	2		T454	3
values[74]	76	1			T486	3		T452	10		T807	4
values[75]	65	1			T486	1		T452	11		T807	8
values[76]	77	1			T486	1		T807	9		T601	15
values[77]	81	1			T486	5		T807	4		T601	12
values[78]	78	1			T486	2		T807	7		T601	6
values[79]	90	1			T486	3		T807	8		T601	10
values[80]	95	1			T486	3		T807	6		T601	9
values[81]	73	1			T486	2		T807	8		T601	5
values[82]	72	1			T486	2		T807	12		T601	4
values[83]	75	1			T486	3		T807	8		T601	4
values[84]	85	1			T486	3		T807	11		T601	1
values[85]	77	1			T486	1		T807	9		T467	1
values[86]	71	1			T486	2		T807	7		T467	1
values[87]	74	1			T486	1		T807	4		T467	1
values[88]	59	1			T486	2		T807	4		T467	1
values[89]	61	1			T486	1		T807	11		T467	1
values[90]	57	1			T486	4		T807	10		T467	1
values[91]	78	1			T486	3		T807	7		T467	1
values[92]	80	1			T486	9		T807	4		T467	1
values[93]	88	1			T486	13		T807	2		T467	1
values[94]	74	1			T486	7		T807	3		T467	1
values[95]	57	1			T486	4		T807	2		T467	1
values[96]	70	1			T486	2		T807	10		T467	1
values[97]	64	1			T486	2		T807	7		T467	1
values[98]	66	1			T486	4		T807	8		T467	1
values[99]	82	1			T486	5		T807	7		T467	1
values[100]	66	1			T486	3		T807	1		T467	1
values[101]	71	1			T486	7		T807	4		T467	1
values[102]	66	1			T486	6		T807	3		T467	1
values[103]	63	1			T486	8		T807	1		T467	1
values[104]	58	1			T486	2		T807	4		T467	1
values[105]	53	1			T486	2		T807	2		T467	1
values[106]	54	1			T486	3		T807	4		T467	1
values[107]	62	1			T486	3		T807	3		T467	1
values[108]	59	1			T486	2		T807	5		T467	3
values[109]	59	1			T486	2		T807	3		T467	2
values[110]	51	1			T486	2		T807	4		T467	4
values[111]	76	1			T486	8		T807	4		T467	6
values[112]	52	1			T486	5		T807	3		T467	1
values[113]	37	1			T486	1		T807	1		T467	5
values[114]	43	1			T486	5		T467	2		T791	1
values[115]	60	1			T486	11		T467	4		T791	1
values[116]	57	1			T486	8		T467	2		T791	4
values[117]	53	1			T486	9		T467	4		T791	1
values[118]	43	1			T486	3		T467	1		T791	4
values[119]	52	1			T486	1		T467	1		T791	6
values[120]	39	1			T486	1		T467	2		T791	1
values[121]	34	1			T486	5		T467	2		T791	1
values[122]	42	1			T486	3		T467	2		T791	2
values[123]	41	1			T486	3		T467	4		T791	1
values[124]	54	1			T486	2		T467	1		T791	6
values[125]	51	1			T486	9		T467	1		T791	1
values[126]	67	1			T486	11		T467	2		T791	5
values[127]	601	1			T486	9		T467	26		T791	35
values[128]	5220	1			T486	2		T467	266		T791	389