Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	434	1			T447	1		T419	1		T418	3
all_values[1]	405	1			T416	1		T419	3		T411	1
all_values[2]	452	1			T447	1		T411	1		T418	1
all_values[3]	453	1			T447	1		T411	1		T418	3
all_values[4]	423	1			T419	1		T411	2		T418	1
all_values[5]	477	1			T447	2		T411	3		T418	4
all_values[6]	450	1			T418	3		T693	2		T448	1
all_values[7]	473	1			T447	1		T416	1		T419	1
all_values[8]	448	1			T447	3		T411	2		T418	1
all_values[9]	476	1			T411	1		T418	3		T588	3
all_values[10]	459	1			T447	2		T416	1		T419	1
all_values[11]	460	1			T419	1		T411	3		T418	2
all_values[12]	454	1			T447	2		T416	1		T418	2
all_values[13]	446	1			T411	3		T418	4		T588	5
all_values[14]	453	1			T447	1		T416	1		T411	1
all_values[15]	448	1			T447	1		T416	1		T419	1
all_values[16]	454	1			T411	2		T588	1		T792	1
all_values[17]	458	1			T419	2		T411	2		T418	1
all_values[18]	473	1			T74	1		T411	5		T418	1
all_values[19]	461	1			T447	1		T419	1		T418	2
all_values[20]	445	1			T447	1		T416	1		T419	1
all_values[21]	437	1			T447	1		T418	1		T588	1
all_values[22]	424	1			T447	1		T419	2		T418	2
all_values[23]	441	1			T419	1		T588	4		T792	1
all_values[24]	476	1			T419	1		T411	1		T418	2
all_values[25]	438	1			T419	1		T411	3		T588	1
all_values[26]	454	1			T74	1		T416	1		T411	2
all_values[27]	444	1			T411	1		T418	1		T588	2
all_values[28]	472	1			T447	1		T416	1		T419	1
all_values[29]	444	1			T447	1		T419	1		T418	1
all_values[30]	463	1			T416	1		T418	1		T613	2
all_values[31]	474	1			T447	1		T416	1		T419	1
all_values[32]	466	1			T447	2		T411	1		T418	1
all_values[33]	455	1			T447	1		T419	1		T411	1
all_values[34]	453	1			T447	1		T416	1		T418	2
all_values[35]	445	1			T74	1		T419	2		T411	1
all_values[36]	497	1			T419	1		T411	1		T418	1
all_values[37]	415	1			T419	1		T411	1		T588	5
all_values[38]	475	1			T447	1		T416	1		T419	1
all_values[39]	463	1			T74	1		T418	3		T588	4
all_values[40]	452	1			T74	1		T416	1		T411	1
all_values[41]	463	1			T447	1		T419	2		T418	1
all_values[42]	467	1			T416	1		T588	4		T792	2
all_values[43]	427	1			T447	1		T416	1		T419	2
all_values[44]	449	1			T447	1		T419	2		T411	1
all_values[45]	472	1			T447	2		T416	1		T411	1
all_values[46]	461	1			T447	1		T416	1		T419	2
all_values[47]	494	1			T419	2		T411	1		T588	1
all_values[48]	465	1			T447	2		T411	2		T418	4
all_values[49]	466	1			T419	1		T411	1		T418	1