Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3358	1			T73	1		T519	2		T447	7
all_values[1]	3334	1			T447	2		T518	8		T525	2
all_values[2]	3321	1			T73	1		T519	1		T447	4
all_values[3]	3518	1			T73	1		T447	2		T518	2
all_values[4]	3450	1			T73	1		T447	2		T518	3
all_values[5]	3318	1			T73	1		T447	1		T518	6
all_values[6]	3444	1			T73	1		T447	3		T518	4
all_values[7]	3424	1			T73	1		T519	1		T447	4
all_values[8]	3420	1			T73	1		T519	2		T518	4
all_values[9]	3441	1			T73	2		T447	3		T518	9
all_values[10]	3484	1			T73	3		T447	6		T518	2
all_values[11]	3376	1			T73	1		T447	4		T518	4
all_values[12]	3391	1			T73	4		T519	2		T447	2
all_values[13]	3396	1			T73	1		T519	3		T447	3
all_values[14]	3330	1			T73	2		T519	1		T447	3
all_values[15]	3356	1			T519	3		T518	4		T525	3
all_values[16]	3337	1			T73	2		T447	5		T518	6
all_values[17]	3368	1			T518	8		T525	1		T421	1
all_values[18]	3398	1			T73	1		T519	2		T447	4
all_values[19]	3447	1			T519	1		T447	3		T518	3
all_values[20]	3300	1			T73	1		T519	2		T447	6
all_values[21]	3476	1			T447	3		T518	5		T421	2
all_values[22]	3355	1			T73	1		T447	2		T518	7
all_values[23]	3281	1			T73	1		T447	1		T518	1
all_values[24]	3410	1			T73	2		T519	1		T447	2
all_values[25]	3464	1			T73	1		T519	2		T447	2
all_values[26]	3313	1			T73	3		T519	1		T447	2
all_values[27]	3415	1			T73	1		T519	2		T447	2
all_values[28]	3322	1			T519	1		T447	2		T518	8
all_values[29]	3419	1			T73	2		T447	1		T518	7
all_values[30]	3453	1			T73	1		T519	2		T447	2
all_values[31]	3439	1			T73	1		T519	1		T447	5
all_values[32]	3416	1			T73	1		T447	2		T518	7
all_values[33]	3427	1			T73	4		T519	1		T447	4
all_values[34]	3397	1			T73	3		T447	2		T518	4
all_values[35]	3377	1			T73	3		T519	1		T447	5
all_values[36]	3452	1			T447	3		T518	5		T525	1
all_values[37]	3371	1			T519	1		T447	1		T518	6
all_values[38]	3238	1			T447	3		T518	6		T525	1
all_values[39]	3378	1			T73	1		T447	1		T518	10
all_values[40]	3351	1			T447	4		T518	4		T525	1
all_values[41]	3360	1			T447	2		T518	5		T525	1
all_values[42]	3453	1			T519	1		T447	1		T518	7
all_values[43]	3491	1			T73	3		T447	1		T518	7
all_values[44]	3443	1			T519	2		T518	5		T416	9
all_values[45]	3398	1			T73	1		T447	1		T518	3
all_values[46]	3539	1			T73	2		T519	1		T447	5
all_values[47]	3333	1			T447	2		T518	2		T525	2
all_values[48]	3300	1			T518	4		T416	6		T411	2
all_values[49]	3355	1			T73	2		T519	1		T447	4
all_values[50]	3369	1			T447	2		T518	7		T421	1
all_values[51]	3377	1			T519	1		T447	3		T518	6
all_values[52]	3482	1			T73	1		T519	2		T518	9
all_values[53]	3438	1			T73	2		T519	2		T447	3
all_values[54]	3436	1			T73	1		T447	1		T518	5
all_values[55]	3471	1			T73	2		T519	1		T447	1
all_values[56]	3411	1			T73	2		T518	9		T525	3
all_values[57]	3365	1			T519	1		T447	2		T518	8
all_values[58]	3350	1			T447	2		T518	9		T525	1
all_values[59]	3416	1			T73	1		T447	2		T518	11
all_values[60]	3422	1			T518	7		T525	2		T421	1
all_values[61]	3343	1			T73	2		T519	1		T447	2
all_values[62]	3393	1			T447	2		T518	3		T525	2
all_values[63]	3466	1			T73	2		T447	3		T518	2