Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141738	1			T81	33		T82	6		T83	2
values[2]	11141	1			T82	8		T83	7		T85	1
values[3]	4430	1			T82	13		T83	2		T501	1
values[4]	2474	1			T82	3		T83	2		T501	1
values[5]	1488	1			T82	7		T83	4		T501	1
values[6]	998	1			T82	14		T83	11		T501	1
values[7]	670	1			T82	8		T83	9		T501	1
values[8]	414	1			T82	8		T83	5		T501	1
values[9]	379	1			T82	9		T83	5		T501	1
values[10]	343	1			T82	7		T83	1		T501	1
values[11]	296	1			T82	10		T83	3		T501	1
values[12]	285	1			T82	2		T83	6		T501	1
values[13]	271	1			T82	9		T83	7		T501	1
values[14]	295	1			T82	15		T83	6		T501	1
values[15]	319	1			T82	5		T83	5		T501	1
values[16]	327	1			T82	5		T83	4		T501	1
values[17]	234	1			T82	4		T83	3		T501	1
values[18]	235	1			T82	9		T83	1		T501	1
values[19]	291	1			T82	17		T83	7		T501	1
values[20]	263	1			T82	10		T83	6		T501	1
values[21]	243	1			T82	3		T83	1		T501	1
values[22]	309	1			T82	3		T83	3		T501	1
values[23]	219	1			T82	3		T83	4		T501	1
values[24]	245	1			T82	8		T83	6		T501	1
values[25]	238	1			T82	13		T83	4		T501	1
values[26]	268	1			T82	9		T83	4		T501	1
values[27]	233	1			T82	4		T83	5		T501	1
values[28]	269	1			T82	4		T83	3		T501	1
values[29]	322	1			T82	3		T83	4		T501	1
values[30]	305	1			T82	8		T83	4		T501	1
values[31]	252	1			T82	12		T83	6		T501	1
values[32]	264	1			T82	19		T83	2		T501	1
values[33]	220	1			T82	5		T83	1		T501	1
values[34]	264	1			T82	12		T83	2		T501	1
values[35]	268	1			T82	15		T83	4		T501	1
values[36]	223	1			T82	7		T83	4		T501	1
values[37]	227	1			T82	10		T83	7		T501	1
values[38]	247	1			T82	12		T83	5		T501	1
values[39]	206	1			T82	4		T83	1		T501	1
values[40]	239	1			T82	11		T83	2		T501	1
values[41]	256	1			T82	10		T83	2		T501	1
values[42]	223	1			T82	3		T83	2		T501	1
values[43]	299	1			T82	8		T83	1		T501	1
values[44]	281	1			T82	15		T83	5		T501	1
values[45]	227	1			T82	4		T83	3		T501	1
values[46]	261	1			T82	2		T83	4		T501	1
values[47]	233	1			T83	3		T501	1		T431	1
values[48]	248	1			T83	6		T501	1		T431	6
values[49]	260	1			T83	5		T501	1		T431	7
values[50]	189	1			T83	1		T501	1		T431	4
values[51]	232	1			T83	7		T501	1		T431	3
values[52]	196	1			T83	3		T501	1		T431	2
values[53]	202	1			T83	5		T501	1		T431	3
values[54]	224	1			T83	5		T501	1		T431	5
values[55]	200	1			T83	4		T501	1		T431	3
values[56]	188	1			T83	2		T501	1		T431	3
values[57]	199	1			T83	1		T501	1		T431	3
values[58]	231	1			T83	6		T501	1		T431	3
values[59]	222	1			T83	4		T501	1		T431	1
values[60]	216	1			T83	3		T501	1		T431	1
values[61]	184	1			T83	3		T501	1		T431	2
values[62]	165	1			T83	3		T501	1		T431	1
values[63]	160	1			T83	1		T501	1		T431	3
values[64]	165	1			T83	3		T501	1		T431	1
values[65]	163	1			T83	2		T501	1		T431	4
values[66]	178	1			T83	2		T501	1		T431	4
values[67]	177	1			T83	1		T501	1		T431	3
values[68]	154	1			T83	5		T501	1		T431	3
values[69]	134	1			T83	1		T501	1		T431	5
values[70]	134	1			T83	1		T501	1		T431	11
values[71]	154	1			T83	3		T501	2		T431	10
values[72]	124	1			T83	2		T501	1		T431	12
values[73]	130	1			T83	3		T501	1		T431	17
values[74]	129	1			T83	7		T501	1		T431	7
values[75]	123	1			T83	4		T501	1		T431	15
values[76]	116	1			T83	7		T501	1		T431	16
values[77]	93	1			T83	3		T501	1		T431	9
values[78]	96	1			T501	1		T431	2		T604	5
values[79]	91	1			T501	1		T604	8		T787	1
values[80]	93	1			T501	1		T604	9		T787	2
values[81]	86	1			T501	1		T604	9		T787	3
values[82]	70	1			T501	1		T604	5		T787	2
values[83]	77	1			T501	1		T604	16		T787	2
values[84]	88	1			T501	1		T604	8		T787	4
values[85]	80	1			T501	1		T604	7		T787	3
values[86]	79	1			T501	1		T604	8		T787	1
values[87]	53	1			T501	1		T604	2		T787	1
values[88]	73	1			T501	1		T604	2		T787	2
values[89]	63	1			T501	1		T604	1		T787	10
values[90]	79	1			T501	1		T787	1		T428	7
values[91]	79	1			T501	1		T787	4		T428	1
values[92]	68	1			T501	1		T787	7		T772	1
values[93]	59	1			T501	1		T787	9		T772	1
values[94]	61	1			T501	1		T787	6		T772	1
values[95]	74	1			T501	1		T787	1		T772	1
values[96]	47	1			T501	1		T787	2		T772	1
values[97]	64	1			T501	1		T787	7		T772	3
values[98]	63	1			T501	1		T787	4		T772	3
values[99]	82	1			T501	1		T787	6		T772	1
values[100]	59	1			T501	1		T787	2		T772	3
values[101]	81	1			T501	1		T787	2		T772	6
values[102]	68	1			T501	2		T787	2		T772	2
values[103]	74	1			T501	2		T787	6		T772	3
values[104]	63	1			T501	2		T787	1		T772	4
values[105]	70	1			T501	2		T787	2		T772	3
values[106]	63	1			T501	1		T787	3		T772	1
values[107]	71	1			T501	1		T787	1		T772	4
values[108]	55	1			T501	7		T787	1		T772	5
values[109]	56	1			T501	3		T787	7		T772	2
values[110]	66	1			T501	3		T787	2		T772	11
values[111]	59	1			T501	1		T787	2		T772	2
values[112]	90	1			T501	2		T787	1		T772	1
values[113]	71	1			T501	2		T787	2		T772	1
values[114]	77	1			T501	6		T787	2		T772	4
values[115]	56	1			T501	1		T787	2		T772	3
values[116]	47	1			T501	1		T787	1		T772	1
values[117]	60	1			T501	1		T787	3		T772	2
values[118]	37	1			T501	1		T787	2		T772	1
values[119]	46	1			T501	3		T787	1		T772	1
values[120]	50	1			T501	1		T787	1		T772	1
values[121]	72	1			T501	1		T787	2		T772	2
values[122]	61	1			T501	1		T787	1		T772	1
values[123]	56	1			T501	5		T787	2		T772	1
values[124]	58	1			T501	1		T787	1		T772	2
values[125]	69	1			T501	3		T787	3		T772	1
values[126]	107	1			T501	1		T787	2		T772	2
values[127]	771	1			T501	35		T787	16		T772	37
values[128]	7014	1			T501	293		T787	233		T772	339