Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.29	93.69	95.62		94.41	97.38	99.59

Total tests in report: 2800

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.49	40.49	45.69	45.69	43.18	43.18	32.41	32.41			58.30	58.30	63.03	63.03	0.34	0.34	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1063558036
50.31	9.82	51.27	5.58	58.30	15.12	32.85	0.43			68.39	10.10	89.65	26.62	1.40	1.06	/workspace/coverage/cover_reg_top/4.chip_csr_rw.3133491307
57.02	6.72	62.10	10.83	60.25	1.95	35.39	2.54			69.02	0.63	89.65	0.00	25.74	24.34	/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.294875808
62.66	5.64	73.93	11.83	68.13	7.88	39.02	3.63			79.50	10.47	89.65	0.00	25.74	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3144776940
66.17	3.51	73.93	0.00	68.13	0.00	39.02	0.00			79.50	0.00	89.65	0.00	46.80	21.06	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4291846188
69.28	3.11	76.15	2.22	69.16	1.02	53.13	14.11			80.10	0.60	89.83	0.18	47.34	0.54	/workspace/coverage/default/2.chip_jtag_csr_rw.1777613864
71.76	2.48	76.41	0.26	70.41	1.26	56.46	3.33			80.63	0.54	89.83	0.00	56.81	9.47	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3854141005
74.09	2.34	81.65	5.24	74.18	3.77	59.93	3.47			82.17	1.53	89.83	0.00	56.81	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648900379
75.94	1.85	83.81	2.16	77.04	2.86	62.54	2.61			84.26	2.09	90.02	0.18	57.98	1.17	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1164460542
77.47	1.53	83.81	0.00	77.23	0.19	62.54	0.00			84.28	0.02	90.02	0.00	66.94	8.95	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1230291626
78.86	1.39	85.80	1.99	80.42	3.19	62.89	0.35			87.09	2.81	90.02	0.00	66.94	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2089418735
80.21	1.36	85.83	0.03	80.42	0.00	70.99	8.10			87.09	0.00	90.02	0.00	66.94	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4214517602
81.50	1.28	85.83	0.00	80.42	0.00	70.99	0.00			87.09	0.00	90.02	0.00	74.63	7.70	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2203995242
82.69	1.19	85.83	0.00	80.42	0.00	78.13	7.14			87.09	0.00	90.02	0.00	74.63	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.608900024
83.68	1.00	85.83	0.00	80.42	0.00	78.13	0.00			87.09	0.00	90.02	0.00	80.61	5.98	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2865215774
84.60	0.92	87.23	1.40	81.46	1.03	78.33	0.20			88.32	1.24	91.68	1.66	80.61	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4167087056
85.52	0.91	88.01	0.78	81.74	0.28	78.35	0.03			88.64	0.32	95.75	4.07	80.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3517706305
86.29	0.77	88.15	0.15	81.90	0.16	81.93	3.58			88.68	0.03	95.93	0.18	81.14	0.53	/workspace/coverage/default/1.chip_sw_alert_test.3532814995
86.97	0.68	88.15	0.00	81.90	0.00	81.93	0.00			88.68	0.00	95.93	0.00	85.23	4.09	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1652464892
87.60	0.62	89.26	1.10	82.83	0.93	82.59	0.66			89.74	1.06	95.93	0.00	85.23	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.195628479
88.21	0.61	89.26	0.00	83.15	0.33	82.59	0.00			89.75	0.01	95.93	0.00	88.58	3.35	/workspace/coverage/cover_reg_top/76.xbar_stress_all.132261605
88.75	0.54	89.29	0.03	83.15	0.00	85.81	3.23			89.75	0.00	95.93	0.00	88.58	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4233279492
89.25	0.50	90.27	0.98	84.06	0.90	86.21	0.40			90.47	0.73	95.93	0.00	88.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.326860761
89.72	0.46	90.95	0.67	84.57	0.52	86.99	0.78			91.28	0.81	95.93	0.00	88.58	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.866574257
90.17	0.46	90.95	0.00	84.57	0.00	86.99	0.00			91.28	0.00	95.93	0.00	91.32	2.74	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3647584853
90.62	0.44	90.95	0.00	84.73	0.16	86.99	0.00			91.28	0.00	95.93	0.00	93.82	2.50	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1270084001
91.04	0.43	90.96	0.01	86.87	2.14	86.99	0.00			91.28	0.00	95.93	0.00	94.22	0.40	/workspace/coverage/cover_reg_top/18.chip_tl_errors.563358748
91.45	0.40	91.85	0.89	86.94	0.06	88.35	1.36			91.28	0.00	95.93	0.00	94.32	0.11	/workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3466599599
91.79	0.34	92.36	0.52	87.43	0.49	88.91	0.56			91.78	0.49	95.93	0.00	94.32	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.4121995055
92.13	0.34	92.93	0.56	88.46	1.03	88.97	0.06			92.17	0.40	95.93	0.00	94.32	0.00	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2498550004
92.44	0.31	92.93	0.00	88.47	0.01	88.97	0.00			92.17	0.00	95.93	0.00	96.17	1.84	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3382567657
92.69	0.25	93.13	0.20	88.63	0.16	89.75	0.78			92.35	0.18	96.12	0.18	96.17	0.00	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.863258327
92.88	0.18	93.13	0.00	88.69	0.06	89.75	0.00			92.35	0.00	96.12	0.00	97.22	1.05	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.977259933
93.05	0.17	93.39	0.26	88.87	0.18	90.27	0.51			92.42	0.07	96.12	0.00	97.22	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.86848616
93.21	0.16	93.67	0.28	89.13	0.26	90.36	0.09			92.74	0.32	96.12	0.00	97.22	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1201286475
93.36	0.15	93.72	0.05	89.53	0.40	90.41	0.05			93.16	0.42	96.12	0.00	97.22	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2145704406
93.49	0.13	93.72	0.00	89.60	0.07	90.41	0.00			93.18	0.02	96.12	0.00	97.93	0.72	/workspace/coverage/cover_reg_top/88.xbar_random_large_delays.609677492
93.61	0.12	93.72	0.00	90.32	0.72	90.41	0.00			93.18	0.00	96.12	0.00	97.93	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.2973768505
93.73	0.12	93.89	0.17	90.58	0.26	90.69	0.28			93.18	0.00	96.12	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1890421765
93.84	0.11	93.91	0.02	90.58	0.00	91.34	0.65			93.18	0.00	96.12	0.00	97.93	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2790899281
93.95	0.10	93.92	0.01	90.61	0.03	91.90	0.56			93.20	0.02	96.12	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1637571178
94.05	0.10	93.97	0.04	90.68	0.08	92.17	0.27			93.23	0.03	96.30	0.18	97.93	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1244685670
94.14	0.09	93.97	0.00	90.94	0.26	92.17	0.00			93.53	0.30	96.30	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1342482314
94.23	0.09	93.98	0.01	90.95	0.01	92.70	0.53			93.53	0.00	96.30	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3294553716
94.32	0.08	93.98	0.00	90.95	0.00	93.21	0.50			93.53	0.00	96.30	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.408940100
94.39	0.08	94.12	0.14	91.10	0.16	93.24	0.03			93.68	0.15	96.30	0.00	97.93	0.00	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2559199685
94.46	0.07	94.21	0.10	91.25	0.15	93.34	0.10			93.74	0.07	96.30	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3484456918
94.53	0.07	94.27	0.06	91.28	0.02	93.63	0.29			93.77	0.02	96.30	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2122979195
94.59	0.06	94.36	0.09	91.45	0.17	93.63	0.00			93.87	0.10	96.30	0.00	97.93	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4222207965
94.65	0.06	94.43	0.07	91.62	0.17	93.63	0.00			93.98	0.12	96.30	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.107221561
94.71	0.06	94.47	0.04	91.64	0.03	93.70	0.07			94.02	0.03	96.49	0.18	97.93	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2948706096
94.77	0.06	94.47	0.00	91.91	0.26	93.70	0.00			94.07	0.05	96.49	0.00	97.97	0.04	/workspace/coverage/cover_reg_top/50.xbar_stress_all.385470893
94.82	0.05	94.47	0.00	91.91	0.00	94.02	0.32			94.07	0.00	96.49	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.712962036
94.87	0.05	94.47	0.00	91.91	0.00	94.02	0.00			94.07	0.00	96.49	0.00	98.27	0.31	/workspace/coverage/cover_reg_top/90.xbar_access_same_device.3173278164
94.92	0.05	94.47	0.00	92.19	0.28	94.02	0.00			94.07	0.00	96.49	0.00	98.28	0.01	/workspace/coverage/cover_reg_top/5.chip_tl_errors.2156044350
94.97	0.05	94.49	0.02	92.23	0.04	94.02	0.00			94.09	0.02	96.67	0.18	98.30	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1952422390
95.01	0.04	94.50	0.01	92.24	0.01	94.02	0.00			94.12	0.02	96.86	0.18	98.31	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917235610
95.05	0.04	94.50	0.01	92.26	0.01	94.02	0.01			94.12	0.01	97.04	0.18	98.32	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2587284742
95.08	0.04	94.51	0.01	92.27	0.01	94.03	0.01			94.13	0.01	97.23	0.18	98.33	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1743624511
95.12	0.04	94.53	0.03	92.32	0.05	94.13	0.10			94.17	0.04	97.23	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_usbdev_stream.1157956132
95.15	0.03	94.53	0.00	92.32	0.00	94.33	0.20			94.17	0.00	97.23	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3963860435
95.19	0.03	94.53	0.00	92.32	0.00	94.34	0.01			94.17	0.00	97.41	0.18	98.33	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.414046825
95.22	0.03	94.53	0.00	92.32	0.00	94.34	0.00			94.17	0.00	97.41	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1585186275
95.25	0.03	94.53	0.00	92.50	0.18	94.34	0.00			94.17	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3713998389
95.28	0.03	94.53	0.00	92.50	0.00	94.51	0.17			94.17	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.1492665793
95.30	0.03	94.61	0.08	92.50	0.00	94.60	0.08			94.18	0.01	97.41	0.00	98.52	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.232408917
95.33	0.03	94.61	0.00	92.61	0.12	94.60	0.00			94.20	0.02	97.41	0.00	98.54	0.02	/workspace/coverage/cover_reg_top/0.xbar_stress_all.1243998699
95.35	0.03	94.68	0.07	92.66	0.05	94.60	0.01			94.23	0.03	97.41	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2403204736
95.38	0.03	94.74	0.07	92.71	0.05	94.60	0.00			94.26	0.03	97.41	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3644032216
95.40	0.02	94.78	0.04	92.74	0.03	94.67	0.07			94.27	0.01	97.41	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3372695076
95.43	0.02	94.78	0.00	92.74	0.00	94.82	0.14			94.27	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.486895711
95.45	0.02	94.78	0.00	92.86	0.12	94.82	0.00			94.27	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3278281831
95.47	0.02	94.80	0.02	92.88	0.02	94.89	0.08			94.27	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1650891229
95.49	0.02	94.81	0.01	92.90	0.01	94.97	0.08			94.28	0.01	97.41	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1552317933
95.50	0.02	94.88	0.06	92.92	0.02	94.98	0.01			94.29	0.01	97.41	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3791769866
95.52	0.01	94.88	0.00	92.92	0.00	95.07	0.09			94.29	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2260704687
95.53	0.01	94.88	0.00	92.98	0.06	95.07	0.00			94.31	0.02	97.41	0.00	98.54	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2455481997
95.55	0.01	94.88	0.01	92.98	0.00	95.13	0.07			94.31	0.00	97.41	0.00	98.55	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.747638373
95.56	0.01	94.88	0.00	93.03	0.05	95.13	0.00			94.35	0.03	97.41	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all.2773821179
95.57	0.01	94.89	0.01	93.07	0.04	95.15	0.02			94.35	0.00	97.41	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2842537246
95.58	0.01	94.89	0.00	93.07	0.01	95.15	0.00			94.35	0.00	97.41	0.00	98.61	0.06	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3275931999
95.59	0.01	94.89	0.00	93.14	0.06	95.15	0.00			94.35	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1845510749
95.60	0.01	94.89	0.00	93.19	0.06	95.15	0.00			94.35	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4261781258
95.61	0.01	94.91	0.03	93.20	0.01	95.16	0.01			94.36	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1227169991
95.62	0.01	94.93	0.02	93.21	0.01	95.17	0.01			94.38	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2642504340
95.63	0.01	94.93	0.00	93.26	0.05	95.17	0.00			94.38	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.4054021963
95.64	0.01	94.93	0.00	93.26	0.00	95.22	0.05			94.38	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1862573591
95.64	0.01	94.96	0.03	93.28	0.02	95.23	0.01			94.38	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.3382275973
95.65	0.01	94.96	0.01	93.29	0.02	95.24	0.01			94.39	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2700582113
95.66	0.01	94.96	0.00	93.29	0.00	95.24	0.00			94.39	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.275277338
95.67	0.01	94.97	0.01	93.31	0.01	95.26	0.02			94.40	0.01	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3623789652
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95.90	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.752773173
95.90	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020330562
95.91	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4195054137
95.91	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.880397519
95.91	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208958706
95.91	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157433369
95.91	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.258138258
95.92	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3316705975
95.92	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119868347
95.92	0.01	94.98	0.00	93.59	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.59	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4200403812
95.92	0.01	94.98	0.00	93.60	0.01	95.55	0.00			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.4168817990
95.92	0.01	94.98	0.00	93.61	0.01	95.55	0.00			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all.1403065191
95.93	0.01	94.98	0.00	93.62	0.01	95.55	0.00			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.757048340
95.93	0.01	95.00	0.01	93.62	0.00	95.55	0.00			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3125464508
95.93	0.01	95.00	0.01	93.62	0.00	95.56	0.01			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/10.chip_sw_all_escalation_resets.406620571
95.93	0.01	95.00	0.00	93.62	0.00	95.57	0.01			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4156302757
95.93	0.01	95.00	0.00	93.62	0.00	95.58	0.01			94.40	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2209664971
95.93	0.01	95.00	0.00	93.62	0.00	95.58	0.00			94.40	0.01	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1215731891
95.94	0.01	95.00	0.00	93.62	0.00	95.58	0.00			94.41	0.01	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3892632968
95.94	0.01	95.00	0.00	93.63	0.01	95.58	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/10.xbar_random.2230963226
95.94	0.01	95.00	0.00	93.64	0.01	95.58	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1776622213
95.94	0.01	95.00	0.00	93.64	0.00	95.58	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.310847810
95.94	0.01	95.00	0.00	93.64	0.00	95.59	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2199662721
95.94	0.01	95.00	0.00	93.64	0.00	95.59	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1257687648
95.94	0.01	95.00	0.00	93.64	0.00	95.60	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.981121596
95.94	0.01	95.00	0.00	93.64	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all.3243093415
95.94	0.01	95.00	0.00	93.64	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.4178726594
95.94	0.01	95.00	0.00	93.65	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.324950341
95.94	0.01	95.00	0.00	93.65	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1004391827
95.94	0.01	95.00	0.00	93.66	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3510105686
95.95	0.01	95.00	0.00	93.66	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2825388256
95.95	0.01	95.00	0.00	93.66	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2061664343
95.95	0.01	95.00	0.00	93.67	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.662258549
95.95	0.01	95.00	0.00	93.67	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1753427776
95.95	0.01	95.00	0.00	93.67	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.548806150
95.95	0.01	95.00	0.00	93.68	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1405813216
95.95	0.01	95.00	0.00	93.68	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3729043734
95.95	0.01	95.00	0.00	93.68	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.167668277
95.95	0.01	95.00	0.00	93.69	0.01	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_gpio.682214575
95.95	0.01	95.00	0.01	93.69	0.00	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.4104504628
95.95	0.01	95.01	0.01	93.69	0.00	95.60	0.00			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2728117955
95.95	0.01	95.01	0.00	93.69	0.00	95.60	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3442712233
95.95	0.01	95.01	0.00	93.69	0.00	95.61	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1721525604
95.95	0.01	95.01	0.00	93.69	0.00	95.61	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.485798662
95.95	0.01	95.01	0.00	93.69	0.00	95.61	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1796165560
95.95	0.01	95.01	0.00	93.69	0.00	95.61	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3780442541
95.95	0.01	95.01	0.00	93.69	0.00	95.62	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1693135089
95.95	0.01	95.01	0.00	93.69	0.00	95.62	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.175171024
95.95	0.01	95.01	0.00	93.69	0.00	95.62	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.147967084
95.95	0.01	95.01	0.00	93.69	0.00	95.62	0.01			94.41	0.00	97.41	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2620942729

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.198076743
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.427532414
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2734536016
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2749091267
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.159135512
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1271472194
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3316259599
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3115310823
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3706171790
/workspace/coverage/cover_reg_top/0.xbar_error_random.382404633
/workspace/coverage/cover_reg_top/0.xbar_random.1282974268
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1821680943
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.737208325
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3734550272
/workspace/coverage/cover_reg_top/0.xbar_same_source.2515914515
/workspace/coverage/cover_reg_top/0.xbar_smoke.2895320944
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2438712087
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3849454605
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4135082483
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.210051087
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.590491685
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3167378389
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3726774480
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.372328237
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1889508459
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3562846426
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.52897348
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.422747033
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1835618817
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1121650732
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1513877975
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3096473777
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4156990901
/workspace/coverage/cover_reg_top/1.xbar_error_random.2908256370
/workspace/coverage/cover_reg_top/1.xbar_random.1318612951
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.13456924
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3737847294
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1453568709
/workspace/coverage/cover_reg_top/1.xbar_same_source.4027916335
/workspace/coverage/cover_reg_top/1.xbar_smoke.3247842966
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1976593673
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3775365273
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1253712239
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1149253298
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2927994189
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2579679409
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2753118123
/workspace/coverage/cover_reg_top/10.chip_csr_rw.592470922
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2465651986
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3012310973
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2025551116
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.411035289
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.402828360
/workspace/coverage/cover_reg_top/10.xbar_error_random.581902216
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.884749579
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2232436772
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2034111928
/workspace/coverage/cover_reg_top/10.xbar_same_source.3181435508
/workspace/coverage/cover_reg_top/10.xbar_smoke.3555389754
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3810198994
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1786241868
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.57737954
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3633712074
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3027871952
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2959716526
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1833298580
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1694494861
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2643171159
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3732717675
/workspace/coverage/cover_reg_top/11.chip_tl_errors.168295439
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3823157319
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1299979791
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4230793865
/workspace/coverage/cover_reg_top/11.xbar_error_random.3669870760
/workspace/coverage/cover_reg_top/11.xbar_random.4013711726
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4017114032
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2830222454
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1530705574
/workspace/coverage/cover_reg_top/11.xbar_same_source.48623160
/workspace/coverage/cover_reg_top/11.xbar_smoke.3088840608
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.886140915
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3604638626
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2511865903
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3657788796
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.447738092
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1095198286
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.97737655
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1735246514
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3752065720
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.135433826
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2768716118
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2358588992
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1594478518
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3722153350
/workspace/coverage/cover_reg_top/12.xbar_error_random.1206991721
/workspace/coverage/cover_reg_top/12.xbar_random.2500521086
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3340079126
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3347525146
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.117145287
/workspace/coverage/cover_reg_top/12.xbar_same_source.1820856427
/workspace/coverage/cover_reg_top/12.xbar_smoke.4203765408
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3160100234
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1203087955
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3873079821
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2130004162
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1078035488
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1781931203
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1510052933
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3488597732
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.112780159
/workspace/coverage/cover_reg_top/13.chip_tl_errors.740320225
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4039819405
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1082381628
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2606218525
/workspace/coverage/cover_reg_top/13.xbar_error_random.2424897451
/workspace/coverage/cover_reg_top/13.xbar_random.2689368088
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3140216817
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3255652170
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1701508367
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/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.108908157
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2547098604
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200429258
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2871552824
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1950434987
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3201563678
/workspace/coverage/default/5.chip_sw_all_escalation_resets.870059838
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1117450241
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2604113901
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1374783010
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3247655403
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.229489280
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087852066
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1176955382
/workspace/coverage/default/53.chip_sw_all_escalation_resets.603841974
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3563022380
/workspace/coverage/default/54.chip_sw_all_escalation_resets.54809679
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350536747
/workspace/coverage/default/56.chip_sw_all_escalation_resets.4188552896
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442419689
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1734081409
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3645143719
/workspace/coverage/default/58.chip_sw_all_escalation_resets.477001892
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102090563
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1882030773
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3688754667
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3671424764
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1124459787
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1725839943
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.401969489
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239546169
/workspace/coverage/default/63.chip_sw_all_escalation_resets.881828445
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1950743943
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828533230
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3681538567
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238325542
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4210166057
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594993776
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2676006804
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2872847499
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2877453330
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2564792484
/workspace/coverage/default/70.chip_sw_all_escalation_resets.613329672
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185456361
/workspace/coverage/default/71.chip_sw_all_escalation_resets.902987867
/workspace/coverage/default/72.chip_sw_all_escalation_resets.679373310
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1745128909
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1985353989
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1204111325
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3992115950
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848037085
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1302092986
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1994997520
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3231991920
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1960906832
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2991265457
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1598074245
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570876830
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1005605302
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.663088579
/workspace/coverage/default/80.chip_sw_all_escalation_resets.102383282
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2429521875
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3000338181
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2972735925
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514881626
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2413113675
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1808415202
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3599671775
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1356723818
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.244625262
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1821632277
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.476549646
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3565994203
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756254041
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2599948826
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1365108938
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054038136
/workspace/coverage/default/9.chip_sw_all_escalation_resets.446472133
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2620416921
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3067000475
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3831315905
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1432638633
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2395712830
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1556082462
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3797800597
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2178182138
/workspace/coverage/default/96.chip_sw_all_escalation_resets.863482999
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2483835885
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3003198019
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2789086550
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.858610949
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.35651055
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3183999799
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2074662544
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3030938053
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2432755227
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3312009108

---

Total test records in report: 2800

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.608900024			Apr 23 04:23:01 PM PDT 24	Apr 23 04:30:31 PM PDT 24	4280879650 ps
T2	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416455129			Apr 23 04:32:43 PM PDT 24	Apr 23 04:40:44 PM PDT 24	4293165780 ps
T3	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2617019396			Apr 23 04:11:00 PM PDT 24	Apr 23 04:18:55 PM PDT 24	5728450136 ps
T60	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4286704650			Apr 23 03:54:22 PM PDT 24	Apr 23 04:00:01 PM PDT 24	3093407976 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_stream.1157956132			Apr 23 03:51:01 PM PDT 24	Apr 23 05:11:12 PM PDT 24	19674274200 ps
T61	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4233279492			Apr 23 04:11:34 PM PDT 24	Apr 23 05:12:19 PM PDT 24	24164430833 ps
T90	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3793827775			Apr 23 04:22:39 PM PDT 24	Apr 23 04:27:14 PM PDT 24	3297093672 ps
T91	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4035786339			Apr 23 04:25:03 PM PDT 24	Apr 23 04:42:34 PM PDT 24	7140586931 ps
T31	/workspace/coverage/default/24.chip_sw_all_escalation_resets.269926408			Apr 23 04:29:17 PM PDT 24	Apr 23 04:38:52 PM PDT 24	4143029660 ps
T32	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1063558036			Apr 23 04:28:17 PM PDT 24	Apr 23 04:37:53 PM PDT 24	5108334968 ps
T158	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.699425082			Apr 23 04:13:23 PM PDT 24	Apr 23 04:16:10 PM PDT 24	2371470320 ps
T200	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3610816004			Apr 23 04:28:38 PM PDT 24	Apr 23 04:37:51 PM PDT 24	3393158250 ps
T70	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1447894073			Apr 23 04:32:27 PM PDT 24	Apr 23 04:40:27 PM PDT 24	4758254534 ps
T66	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2608207430			Apr 23 04:21:53 PM PDT 24	Apr 23 04:29:34 PM PDT 24	3843456680 ps
T173	/workspace/coverage/default/46.chip_sw_all_escalation_resets.747638373			Apr 23 04:29:49 PM PDT 24	Apr 23 04:39:09 PM PDT 24	5123284938 ps
T132	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2942751352			Apr 23 04:01:52 PM PDT 24	Apr 23 04:08:24 PM PDT 24	3590309088 ps
T191	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2122979195			Apr 23 04:18:50 PM PDT 24	Apr 23 04:24:53 PM PDT 24	3233242264 ps
T159	/workspace/coverage/default/2.chip_sw_power_idle_load.4070746468			Apr 23 04:25:31 PM PDT 24	Apr 23 04:38:21 PM PDT 24	3873716200 ps
T177	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1584227785			Apr 23 04:29:05 PM PDT 24	Apr 23 04:38:13 PM PDT 24	4159135500 ps
T121	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3171004721			Apr 23 04:11:02 PM PDT 24	Apr 23 04:27:37 PM PDT 24	7700213825 ps
T4	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4189335231			Apr 23 04:23:45 PM PDT 24	Apr 23 04:32:49 PM PDT 24	8843718732 ps
T5	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.866574257			Apr 23 04:05:18 PM PDT 24	Apr 23 07:51:38 PM PDT 24	77836926444 ps
T179	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2948706096			Apr 23 03:50:54 PM PDT 24	Apr 23 03:57:15 PM PDT 24	6499326632 ps
T13	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2842537246			Apr 23 03:52:56 PM PDT 24	Apr 23 04:05:25 PM PDT 24	3724334620 ps
T160	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1637571178			Apr 23 03:53:01 PM PDT 24	Apr 23 04:06:44 PM PDT 24	5357333220 ps
T235	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1753427776			Apr 23 03:52:35 PM PDT 24	Apr 23 04:01:07 PM PDT 24	3788579720 ps
T6	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3730829933			Apr 23 04:06:00 PM PDT 24	Apr 23 04:14:40 PM PDT 24	5504539605 ps
T245	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3930298457			Apr 23 03:52:20 PM PDT 24	Apr 23 04:00:25 PM PDT 24	5309209130 ps
T164	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1950067289			Apr 23 04:30:44 PM PDT 24	Apr 23 04:37:42 PM PDT 24	3500428032 ps
T246	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3621030525			Apr 23 04:10:36 PM PDT 24	Apr 23 04:15:13 PM PDT 24	3171426910 ps
T195	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.636652430			Apr 23 04:27:30 PM PDT 24	Apr 23 05:07:21 PM PDT 24	13160711316 ps
T247	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.473020119			Apr 23 04:00:43 PM PDT 24	Apr 23 04:16:22 PM PDT 24	5327915696 ps
T282	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3229846329			Apr 23 04:20:32 PM PDT 24	Apr 23 04:26:54 PM PDT 24	4010191196 ps
T616	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959927969			Apr 23 04:30:21 PM PDT 24	Apr 23 04:35:24 PM PDT 24	3727557080 ps
T87	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1164460542			Apr 23 04:09:23 PM PDT 24	Apr 23 04:31:38 PM PDT 24	10181733248 ps
T371	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223094493			Apr 23 04:31:36 PM PDT 24	Apr 23 04:38:16 PM PDT 24	4562831980 ps
T17	/workspace/coverage/default/1.chip_jtag_csr_rw.2790899281			Apr 23 04:03:29 PM PDT 24	Apr 23 04:25:01 PM PDT 24	11132375786 ps
T150	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.637943472			Apr 23 03:52:24 PM PDT 24	Apr 23 07:17:26 PM PDT 24	64635840507 ps
T122	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2199662721			Apr 23 03:54:49 PM PDT 24	Apr 23 04:01:20 PM PDT 24	5358720038 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1241842405			Apr 23 04:11:58 PM PDT 24	Apr 23 04:32:35 PM PDT 24	17350544020 ps
T107	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.946607461			Apr 23 04:22:41 PM PDT 24	Apr 23 04:31:18 PM PDT 24	4468339168 ps
T108	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2271014548			Apr 23 04:23:25 PM PDT 24	Apr 23 04:29:26 PM PDT 24	2947772058 ps
T109	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3201563678			Apr 23 04:33:08 PM PDT 24	Apr 23 04:46:08 PM PDT 24	5689225262 ps
T110	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3915712128			Apr 23 03:51:59 PM PDT 24	Apr 23 04:08:44 PM PDT 24	6202598644 ps
T111	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3205375078			Apr 23 04:31:25 PM PDT 24	Apr 23 04:42:11 PM PDT 24	5749538978 ps
T112	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3700931531			Apr 23 04:27:59 PM PDT 24	Apr 23 04:38:33 PM PDT 24	3826513798 ps
T113	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3517706305			Apr 23 03:54:51 PM PDT 24	Apr 23 03:58:56 PM PDT 24	2797519974 ps
T114	/workspace/coverage/default/0.chip_sw_example_rom.2994055950			Apr 23 03:49:23 PM PDT 24	Apr 23 03:51:19 PM PDT 24	2354895768 ps
T49	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3323752805			Apr 23 03:54:25 PM PDT 24	Apr 23 04:03:25 PM PDT 24	4659408432 ps
T222	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1151756288			Apr 23 04:26:21 PM PDT 24	Apr 23 04:35:46 PM PDT 24	6819402664 ps
T133	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3376418002			Apr 23 04:22:35 PM PDT 24	Apr 23 05:20:04 PM PDT 24	16972640112 ps
T78	/workspace/coverage/default/3.chip_tap_straps_prod.1338029294			Apr 23 04:25:18 PM PDT 24	Apr 23 04:42:06 PM PDT 24	11671600051 ps
T265	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.134735882			Apr 23 04:31:17 PM PDT 24	Apr 23 04:36:52 PM PDT 24	3749631630 ps
T180	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3350232702			Apr 23 03:56:50 PM PDT 24	Apr 23 04:04:41 PM PDT 24	4807876004 ps
T250	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3292395271			Apr 23 04:09:42 PM PDT 24	Apr 23 04:17:54 PM PDT 24	9391221669 ps
T266	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3043989000			Apr 23 04:30:18 PM PDT 24	Apr 23 04:36:25 PM PDT 24	3181764552 ps
T69	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3484309475			Apr 23 03:51:14 PM PDT 24	Apr 23 03:52:59 PM PDT 24	2704725119 ps
T128	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2793771579			Apr 23 04:23:51 PM PDT 24	Apr 23 04:35:05 PM PDT 24	6658128128 ps
T62	/workspace/coverage/default/1.chip_sw_alert_test.3532814995			Apr 23 04:07:57 PM PDT 24	Apr 23 04:12:21 PM PDT 24	2558040768 ps
T192	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2474108696			Apr 23 04:07:17 PM PDT 24	Apr 23 04:11:32 PM PDT 24	3131593607 ps
T48	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.863258327			Apr 23 04:29:22 PM PDT 24	Apr 23 04:44:03 PM PDT 24	12261382017 ps
T74	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1218370355			Apr 23 04:21:30 PM PDT 24	Apr 23 04:31:16 PM PDT 24	5613330992 ps
T67	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3963860435			Apr 23 03:53:34 PM PDT 24	Apr 23 03:55:36 PM PDT 24	2251405423 ps
T225	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.949965196			Apr 23 04:24:16 PM PDT 24	Apr 23 04:31:43 PM PDT 24	4696851910 ps
T126	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4249823539			Apr 23 04:15:06 PM PDT 24	Apr 23 04:25:25 PM PDT 24	4918098900 ps
T197	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4210336069			Apr 23 04:03:59 PM PDT 24	Apr 23 04:16:40 PM PDT 24	4513800696 ps
T353	/workspace/coverage/default/61.chip_sw_all_escalation_resets.3287223778			Apr 23 04:35:10 PM PDT 24	Apr 23 04:43:33 PM PDT 24	5238821882 ps
T155	/workspace/coverage/default/2.chip_sw_otbn_smoketest.909429153			Apr 23 04:29:01 PM PDT 24	Apr 23 05:12:03 PM PDT 24	10792673532 ps
T338	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.746203900			Apr 23 04:14:58 PM PDT 24	Apr 23 04:26:17 PM PDT 24	5757971492 ps
T10	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3484456918			Apr 23 04:16:56 PM PDT 24	Apr 23 04:29:39 PM PDT 24	7739287396 ps
T831	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3383326855			Apr 23 04:12:25 PM PDT 24	Apr 23 04:20:52 PM PDT 24	3339378848 ps
T182	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2986892252			Apr 23 03:53:32 PM PDT 24	Apr 23 03:56:50 PM PDT 24	3118699526 ps
T832	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2805272164			Apr 23 03:51:26 PM PDT 24	Apr 23 03:59:34 PM PDT 24	6369044894 ps
T190	/workspace/coverage/default/0.chip_sw_power_idle_load.2411498473			Apr 23 03:57:55 PM PDT 24	Apr 23 04:07:22 PM PDT 24	4226086296 ps
T833	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2725261009			Apr 23 04:21:58 PM PDT 24	Apr 23 04:25:28 PM PDT 24	3081465208 ps
T637	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.814687097			Apr 23 03:51:15 PM PDT 24	Apr 23 04:03:06 PM PDT 24	6341135447 ps
T14	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3323925048			Apr 23 04:27:26 PM PDT 24	Apr 23 04:52:20 PM PDT 24	7768215186 ps
T127	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3561616092			Apr 23 04:09:44 PM PDT 24	Apr 23 04:18:38 PM PDT 24	3916982120 ps
T15	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.556841982			Apr 23 04:05:00 PM PDT 24	Apr 23 04:15:27 PM PDT 24	4431337432 ps
T46	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.86848616			Apr 23 04:02:49 PM PDT 24	Apr 23 08:31:24 PM PDT 24	77863136698 ps
T174	/workspace/coverage/default/0.chip_sw_flash_init.1332416101			Apr 23 03:50:13 PM PDT 24	Apr 23 04:21:20 PM PDT 24	23343734850 ps
T226	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.449261437			Apr 23 04:09:01 PM PDT 24	Apr 23 04:48:00 PM PDT 24	28416204940 ps
T668	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.752773173			Apr 23 04:31:16 PM PDT 24	Apr 23 04:37:59 PM PDT 24	4133078404 ps
T834	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1757983656			Apr 23 04:14:13 PM PDT 24	Apr 23 04:17:27 PM PDT 24	2582203276 ps
T68	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3406050235			Apr 23 04:23:05 PM PDT 24	Apr 23 04:29:51 PM PDT 24	5334775712 ps
T196	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2178428514			Apr 23 03:50:30 PM PDT 24	Apr 23 03:58:10 PM PDT 24	4543567272 ps
T636	/workspace/coverage/default/0.chip_sw_aes_entropy.2273837699			Apr 23 03:52:52 PM PDT 24	Apr 23 03:56:31 PM PDT 24	2443704744 ps
T662	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3231991920			Apr 23 04:33:37 PM PDT 24	Apr 23 04:39:12 PM PDT 24	3610974270 ps
T364	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2620942729			Apr 23 04:29:01 PM PDT 24	Apr 23 04:31:36 PM PDT 24	2506050700 ps
T75	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1871518195			Apr 23 04:12:30 PM PDT 24	Apr 23 04:22:20 PM PDT 24	5171630534 ps
T835	/workspace/coverage/default/1.chip_sw_flash_crash_alert.3239979358			Apr 23 04:14:03 PM PDT 24	Apr 23 04:24:39 PM PDT 24	5116045432 ps
T76	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1605389102			Apr 23 04:12:18 PM PDT 24	Apr 23 04:23:18 PM PDT 24	6030849072 ps
T304	/workspace/coverage/default/2.chip_sw_hmac_enc.3088393319			Apr 23 04:21:23 PM PDT 24	Apr 23 04:25:50 PM PDT 24	3442699854 ps
T328	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1176955382			Apr 23 04:33:16 PM PDT 24	Apr 23 04:42:46 PM PDT 24	5673710568 ps
T283	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2158537450			Apr 23 04:31:55 PM PDT 24	Apr 23 04:38:18 PM PDT 24	3623529356 ps
T290	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4146440032			Apr 23 04:27:55 PM PDT 24	Apr 23 04:38:00 PM PDT 24	6123868992 ps
T47	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.455959986			Apr 23 04:29:15 PM PDT 24	Apr 23 09:30:53 PM PDT 24	79246461421 ps
T291	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2096108674			Apr 23 03:50:58 PM PDT 24	Apr 23 04:04:03 PM PDT 24	5605138680 ps
T292	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.107267808			Apr 23 04:24:39 PM PDT 24	Apr 23 04:29:57 PM PDT 24	3589459525 ps
T293	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4210422116			Apr 23 04:25:24 PM PDT 24	Apr 23 04:32:49 PM PDT 24	7378461706 ps
T201	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1650891229			Apr 23 04:27:37 PM PDT 24	Apr 23 04:53:59 PM PDT 24	8552898049 ps
T294	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1785133671			Apr 23 04:10:03 PM PDT 24	Apr 23 04:17:51 PM PDT 24	4461996610 ps
T147	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1524362359			Apr 23 04:10:25 PM PDT 24	Apr 23 04:14:45 PM PDT 24	2826546459 ps
T295	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.976421112			Apr 23 04:05:40 PM PDT 24	Apr 23 04:14:07 PM PDT 24	6358735840 ps
T134	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3786350108			Apr 23 04:25:06 PM PDT 24	Apr 23 04:32:48 PM PDT 24	4391918120 ps
T701	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054038136			Apr 23 04:28:18 PM PDT 24	Apr 23 04:33:35 PM PDT 24	3596332024 ps
T203	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3703087053			Apr 23 03:52:04 PM PDT 24	Apr 23 04:11:28 PM PDT 24	6793689286 ps
T746	/workspace/coverage/default/70.chip_sw_all_escalation_resets.613329672			Apr 23 04:32:02 PM PDT 24	Apr 23 04:41:23 PM PDT 24	5043334970 ps
T125	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.742033453			Apr 23 04:27:15 PM PDT 24	Apr 23 04:43:49 PM PDT 24	10963548116 ps
T188	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.474284193			Apr 23 03:58:46 PM PDT 24	Apr 23 04:02:13 PM PDT 24	2516230990 ps
T24	/workspace/coverage/default/0.chip_sw_gpio.326860761			Apr 23 03:52:02 PM PDT 24	Apr 23 03:58:06 PM PDT 24	3549082554 ps
T135	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1201286475			Apr 23 03:55:27 PM PDT 24	Apr 23 04:06:07 PM PDT 24	7572897300 ps
T339	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2084558570			Apr 23 04:30:52 PM PDT 24	Apr 23 04:41:52 PM PDT 24	6225507710 ps
T370	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3351621598			Apr 23 04:04:22 PM PDT 24	Apr 23 04:19:01 PM PDT 24	5460318512 ps
T198	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1111840784			Apr 23 04:15:27 PM PDT 24	Apr 23 04:24:47 PM PDT 24	3815353764 ps
T50	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.101175976			Apr 23 04:25:07 PM PDT 24	Apr 23 04:50:16 PM PDT 24	21637672626 ps
T626	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050403671			Apr 23 04:27:58 PM PDT 24	Apr 23 04:35:34 PM PDT 24	3858881820 ps
T129	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3294553716			Apr 23 04:09:01 PM PDT 24	Apr 23 04:22:57 PM PDT 24	4264930988 ps
T189	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1124459787			Apr 23 04:27:32 PM PDT 24	Apr 23 05:12:57 PM PDT 24	13031487192 ps
T642	/workspace/coverage/default/2.chip_sw_uart_smoketest.723593233			Apr 23 04:27:10 PM PDT 24	Apr 23 04:30:56 PM PDT 24	2230064142 ps
T63	/workspace/coverage/default/2.chip_jtag_csr_rw.1777613864			Apr 23 04:16:33 PM PDT 24	Apr 23 04:48:48 PM PDT 24	16839078985 ps
T175	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.408940100			Apr 23 04:03:35 PM PDT 24	Apr 23 05:23:33 PM PDT 24	43352889406 ps
T284	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2872847499			Apr 23 04:28:52 PM PDT 24	Apr 23 04:39:38 PM PDT 24	4695423926 ps
T723	/workspace/coverage/default/34.chip_sw_all_escalation_resets.938987418			Apr 23 04:30:20 PM PDT 24	Apr 23 04:38:54 PM PDT 24	4510294200 ps
T84	/workspace/coverage/default/0.chip_jtag_mem_access.2169238024			Apr 23 03:45:56 PM PDT 24	Apr 23 04:09:29 PM PDT 24	13284494728 ps
T726	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2395712830			Apr 23 04:34:09 PM PDT 24	Apr 23 04:43:05 PM PDT 24	4412346696 ps
T228	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3113316710			Apr 23 04:29:13 PM PDT 24	Apr 23 04:33:34 PM PDT 24	3653209654 ps
T270	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1776622213			Apr 23 03:52:39 PM PDT 24	Apr 23 04:01:42 PM PDT 24	4114427916 ps
T271	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2423627848			Apr 23 04:19:05 PM PDT 24	Apr 23 04:26:38 PM PDT 24	7380069520 ps
T272	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743727240			Apr 23 04:28:44 PM PDT 24	Apr 23 04:34:32 PM PDT 24	3453515832 ps
T273	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3831315905			Apr 23 04:32:40 PM PDT 24	Apr 23 04:43:29 PM PDT 24	5758596640 ps
T274	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1556082462			Apr 23 04:32:54 PM PDT 24	Apr 23 04:41:44 PM PDT 24	4473246624 ps
T194	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3001283484			Apr 23 04:03:48 PM PDT 24	Apr 23 04:16:47 PM PDT 24	5464886340 ps
T181	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2545059133			Apr 23 04:10:01 PM PDT 24	Apr 23 04:18:36 PM PDT 24	4002703146 ps
T275	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4088168626			Apr 23 03:52:26 PM PDT 24	Apr 23 04:01:28 PM PDT 24	5912868460 ps
T77	/workspace/coverage/default/4.chip_tap_straps_rma.1199613250			Apr 23 04:26:13 PM PDT 24	Apr 23 04:28:04 PM PDT 24	1974502422 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1450289521			Apr 23 04:21:30 PM PDT 24	Apr 23 04:40:48 PM PDT 24	10361031556 ps
T89	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4126409283			Apr 23 03:52:03 PM PDT 24	Apr 23 04:07:47 PM PDT 24	9392213920 ps
T211	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1161225779			Apr 23 04:08:36 PM PDT 24	Apr 23 04:16:11 PM PDT 24	3717699860 ps
T665	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087852066			Apr 23 04:30:27 PM PDT 24	Apr 23 04:35:17 PM PDT 24	3763954980 ps
T708	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052214153			Apr 23 04:32:35 PM PDT 24	Apr 23 04:39:54 PM PDT 24	4392211750 ps
T130	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2433364696			Apr 23 04:21:17 PM PDT 24	Apr 23 04:38:01 PM PDT 24	4787700530 ps
T178	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3945367890			Apr 23 04:05:29 PM PDT 24	Apr 23 04:08:43 PM PDT 24	2713883864 ps
T412	/workspace/coverage/default/2.chip_sw_kmac_smoketest.684808102			Apr 23 04:25:41 PM PDT 24	Apr 23 04:30:33 PM PDT 24	3310880434 ps
T365	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.906184419			Apr 23 04:07:31 PM PDT 24	Apr 23 04:16:44 PM PDT 24	5165413496 ps
T657	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3978933851			Apr 23 04:30:32 PM PDT 24	Apr 23 04:36:30 PM PDT 24	3443716428 ps
T92	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1743624511			Apr 23 04:27:38 PM PDT 24	Apr 23 04:36:29 PM PDT 24	4133863788 ps
T96	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2855125977			Apr 23 04:32:13 PM PDT 24	Apr 23 04:39:24 PM PDT 24	4308368256 ps
T97	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.713254188			Apr 23 04:09:28 PM PDT 24	Apr 23 04:18:44 PM PDT 24	4271746000 ps
T98	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3947261551			Apr 23 04:25:19 PM PDT 24	Apr 23 04:28:16 PM PDT 24	2794017850 ps
T99	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3892632968			Apr 23 03:53:19 PM PDT 24	Apr 23 04:01:00 PM PDT 24	5520194881 ps
T100	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1015516043			Apr 23 04:23:48 PM PDT 24	Apr 23 04:43:12 PM PDT 24	7870534386 ps
T101	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1489551424			Apr 23 03:51:45 PM PDT 24	Apr 23 03:54:26 PM PDT 24	2987406718 ps
T102	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1222072209			Apr 23 03:52:01 PM PDT 24	Apr 23 03:56:16 PM PDT 24	2658934139 ps
T103	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1950743943			Apr 23 04:35:18 PM PDT 24	Apr 23 04:47:37 PM PDT 24	6482437240 ps
T104	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3448173768			Apr 23 04:32:10 PM PDT 24	Apr 23 04:41:29 PM PDT 24	4415038088 ps
T299	/workspace/coverage/default/1.chip_plic_all_irqs_0.3144776940			Apr 23 04:11:05 PM PDT 24	Apr 23 04:29:07 PM PDT 24	6222728798 ps
T37	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3372695076			Apr 23 04:18:46 PM PDT 24	Apr 23 04:27:01 PM PDT 24	5505230140 ps
T697	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3992115950			Apr 23 04:33:13 PM PDT 24	Apr 23 04:42:33 PM PDT 24	4807969180 ps
T676	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.767670101			Apr 23 04:30:15 PM PDT 24	Apr 23 04:38:02 PM PDT 24	3875222152 ps
T176	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.712962036			Apr 23 03:53:56 PM PDT 24	Apr 23 04:00:25 PM PDT 24	3897544472 ps
T148	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1895262695			Apr 23 04:06:37 PM PDT 24	Apr 23 04:11:35 PM PDT 24	7355063196 ps
T312	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1374783010			Apr 23 04:28:25 PM PDT 24	Apr 23 04:54:12 PM PDT 24	8107934098 ps
T285	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3559812675			Apr 23 03:52:54 PM PDT 24	Apr 23 03:58:11 PM PDT 24	3299463984 ps
T334	/workspace/coverage/default/1.chip_sw_hmac_enc.3079473409			Apr 23 04:09:19 PM PDT 24	Apr 23 04:13:50 PM PDT 24	2796453000 ps
T414	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.861822756			Apr 23 03:51:56 PM PDT 24	Apr 23 04:58:50 PM PDT 24	17256480796 ps
T663	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2178182138			Apr 23 04:32:55 PM PDT 24	Apr 23 04:41:23 PM PDT 24	4456300258 ps
T322	/workspace/coverage/default/53.chip_sw_all_escalation_resets.603841974			Apr 23 04:30:37 PM PDT 24	Apr 23 04:42:58 PM PDT 24	4959862952 ps
T836	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.121601149			Apr 23 04:27:45 PM PDT 24	Apr 23 04:31:53 PM PDT 24	2310502550 ps
T336	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3307502182			Apr 23 04:31:59 PM PDT 24	Apr 23 04:43:54 PM PDT 24	5794207256 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1569019657			Apr 23 03:51:46 PM PDT 24	Apr 23 03:59:24 PM PDT 24	3222870272 ps
T837	/workspace/coverage/default/0.chip_sw_aes_idle.395076904			Apr 23 03:51:43 PM PDT 24	Apr 23 03:55:51 PM PDT 24	2520761880 ps
T838	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3861406459			Apr 23 04:08:41 PM PDT 24	Apr 23 04:11:19 PM PDT 24	2807833492 ps
T675	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1365108938			Apr 23 04:32:28 PM PDT 24	Apr 23 04:44:20 PM PDT 24	5985836328 ps
T233	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1167977683			Apr 23 04:10:03 PM PDT 24	Apr 23 04:14:04 PM PDT 24	3193919808 ps
T323	/workspace/coverage/default/10.chip_sw_all_escalation_resets.406620571			Apr 23 04:28:34 PM PDT 24	Apr 23 04:37:36 PM PDT 24	4936341922 ps
T666	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1380019396			Apr 23 04:28:23 PM PDT 24	Apr 23 04:34:53 PM PDT 24	3514097538 ps
T839	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1644463978			Apr 23 04:14:37 PM PDT 24	Apr 23 04:22:52 PM PDT 24	4332104792 ps
T167	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4214517602			Apr 23 04:16:16 PM PDT 24	Apr 23 05:54:49 PM PDT 24	48938807334 ps
T341	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4156302757			Apr 23 03:52:38 PM PDT 24	Apr 23 04:49:34 PM PDT 24	36110690518 ps
T65	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2700582113			Apr 23 03:50:14 PM PDT 24	Apr 23 03:57:53 PM PDT 24	3406777836 ps
T123	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2158392329			Apr 23 04:25:59 PM PDT 24	Apr 23 04:34:52 PM PDT 24	4422113718 ps
T202	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2245121205			Apr 23 04:04:16 PM PDT 24	Apr 23 04:14:16 PM PDT 24	4335079970 ps
T840	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4129998991			Apr 23 03:56:06 PM PDT 24	Apr 23 04:03:38 PM PDT 24	5376009396 ps
T841	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.388346223			Apr 23 04:14:39 PM PDT 24	Apr 23 04:17:29 PM PDT 24	2196925280 ps
T667	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452451143			Apr 23 04:30:28 PM PDT 24	Apr 23 04:36:58 PM PDT 24	3575812040 ps
T842	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1951316050			Apr 23 04:13:57 PM PDT 24	Apr 23 04:19:33 PM PDT 24	3711646656 ps
T367	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3261374227			Apr 23 04:10:14 PM PDT 24	Apr 23 04:33:36 PM PDT 24	12530992790 ps
T325	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.233688566			Apr 23 04:30:04 PM PDT 24	Apr 23 04:55:06 PM PDT 24	8345037688 ps
T229	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2972735925			Apr 23 04:33:36 PM PDT 24	Apr 23 04:39:08 PM PDT 24	4198776744 ps
T335	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.407194338			Apr 23 04:08:53 PM PDT 24	Apr 23 04:13:10 PM PDT 24	3216023311 ps
T843	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1927284500			Apr 23 04:06:37 PM PDT 24	Apr 23 04:12:04 PM PDT 24	3796481400 ps
T844	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1305285188			Apr 23 04:14:10 PM PDT 24	Apr 23 04:19:48 PM PDT 24	5422900000 ps
T845	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2559199685			Apr 23 04:28:25 PM PDT 24	Apr 23 04:38:09 PM PDT 24	3978209720 ps
T846	/workspace/coverage/default/0.chip_sw_uart_smoketest.908532888			Apr 23 04:02:42 PM PDT 24	Apr 23 04:05:55 PM PDT 24	2558223286 ps
T847	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2449972101			Apr 23 03:50:31 PM PDT 24	Apr 23 03:54:31 PM PDT 24	2857521888 ps
T7	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2089418735			Apr 23 04:15:57 PM PDT 24	Apr 23 04:20:04 PM PDT 24	3386249252 ps
T848	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4189367543			Apr 23 04:01:45 PM PDT 24	Apr 23 04:05:06 PM PDT 24	3139847390 ps
T33	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.962027705			Apr 23 04:15:09 PM PDT 24	Apr 23 04:19:54 PM PDT 24	3266015834 ps
T849	/workspace/coverage/default/2.chip_sw_aes_entropy.611513214			Apr 23 04:22:16 PM PDT 24	Apr 23 04:26:16 PM PDT 24	2410425800 ps
T223	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1906487897			Apr 23 04:28:35 PM PDT 24	Apr 23 04:40:13 PM PDT 24	5057231128 ps
T850	/workspace/coverage/default/0.chip_sw_hmac_enc.1667335875			Apr 23 03:52:57 PM PDT 24	Apr 23 03:56:52 PM PDT 24	2972040368 ps
T851	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3773179845			Apr 23 04:25:13 PM PDT 24	Apr 23 04:33:06 PM PDT 24	6325360456 ps
T131	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2915005254			Apr 23 03:53:58 PM PDT 24	Apr 23 04:19:22 PM PDT 24	8010137908 ps
T352	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.666030627			Apr 23 03:54:17 PM PDT 24	Apr 23 03:59:50 PM PDT 24	5374557720 ps
T614	/workspace/coverage/default/1.chip_sw_edn_sw_mode.2812586381			Apr 23 04:09:09 PM PDT 24	Apr 23 04:41:18 PM PDT 24	9415535330 ps
T168	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3360067441			Apr 23 04:06:42 PM PDT 24	Apr 23 04:42:26 PM PDT 24	20681904111 ps
T852	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.768652063			Apr 23 03:56:05 PM PDT 24	Apr 23 04:00:56 PM PDT 24	2787521561 ps
T725	/workspace/coverage/default/60.chip_sw_all_escalation_resets.1725839943			Apr 23 04:31:26 PM PDT 24	Apr 23 04:43:48 PM PDT 24	5145943520 ps
T224	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3173614761			Apr 23 04:31:16 PM PDT 24	Apr 23 04:41:26 PM PDT 24	4855080328 ps
T172	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1723109136			Apr 23 03:52:34 PM PDT 24	Apr 23 04:13:21 PM PDT 24	7535863392 ps
T305	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.203482920			Apr 23 04:15:48 PM PDT 24	Apr 23 04:25:25 PM PDT 24	3558233899 ps
T853	/workspace/coverage/default/2.chip_sw_csrng_smoketest.1311379321			Apr 23 04:26:54 PM PDT 24	Apr 23 04:30:16 PM PDT 24	2340729424 ps
T854	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4089107678			Apr 23 04:27:06 PM PDT 24	Apr 23 04:50:50 PM PDT 24	8410495200 ps
T855	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2770533259			Apr 23 04:02:03 PM PDT 24	Apr 23 04:21:45 PM PDT 24	6298420468 ps
T234	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3125464508			Apr 23 03:54:23 PM PDT 24	Apr 23 03:57:58 PM PDT 24	3052569912 ps
T413	/workspace/coverage/default/1.chip_sw_kmac_entropy.1492665793			Apr 23 04:06:36 PM PDT 24	Apr 23 04:10:25 PM PDT 24	2818260344 ps
T856	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4291139979			Apr 23 03:53:10 PM PDT 24	Apr 23 03:59:42 PM PDT 24	4787516328 ps
T693	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756254041			Apr 23 04:32:22 PM PDT 24	Apr 23 04:37:59 PM PDT 24	3237403468 ps
T171	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3111769093			Apr 23 04:16:53 PM PDT 24	Apr 23 04:58:51 PM PDT 24	28419468174 ps
T857	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1375042895			Apr 23 04:15:12 PM PDT 24	Apr 23 04:25:11 PM PDT 24	4025212130 ps
T858	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2604113901			Apr 23 04:26:21 PM PDT 24	Apr 23 04:32:52 PM PDT 24	5178286121 ps
T71	/workspace/coverage/default/1.chip_tap_straps_rma.232408917			Apr 23 04:10:30 PM PDT 24	Apr 23 04:13:10 PM PDT 24	2896539615 ps
T859	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1353417044			Apr 23 04:01:42 PM PDT 24	Apr 23 04:06:05 PM PDT 24	2674414044 ps
T860	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2933438687			Apr 23 04:14:44 PM PDT 24	Apr 23 04:22:31 PM PDT 24	4874342590 ps
T861	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2210991706			Apr 23 04:21:52 PM PDT 24	Apr 23 04:29:21 PM PDT 24	3964486360 ps
T119	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1929616168			Apr 23 03:55:14 PM PDT 24	Apr 23 04:06:13 PM PDT 24	4725719866 ps
T337	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1335506972			Apr 23 04:31:17 PM PDT 24	Apr 23 04:39:38 PM PDT 24	4272288440 ps
T638	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2480683238			Apr 23 04:18:56 PM PDT 24	Apr 23 04:37:40 PM PDT 24	8008935000 ps
T136	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1890421765			Apr 23 03:52:14 PM PDT 24	Apr 23 03:58:20 PM PDT 24	4896527224 ps
T651	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3426579641			Apr 23 04:30:44 PM PDT 24	Apr 23 04:41:25 PM PDT 24	6186324866 ps
T212	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2081172145			Apr 23 03:51:14 PM PDT 24	Apr 23 05:24:20 PM PDT 24	48372306261 ps
T674	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330046636			Apr 23 04:33:09 PM PDT 24	Apr 23 04:42:47 PM PDT 24	3171179680 ps
T43	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.347673249			Apr 23 04:04:23 PM PDT 24	Apr 23 08:31:00 PM PDT 24	80202122715 ps
T673	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976943208			Apr 23 04:31:01 PM PDT 24	Apr 23 04:36:30 PM PDT 24	3186773036 ps
T862	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3179379493			Apr 23 03:52:15 PM PDT 24	Apr 23 03:59:22 PM PDT 24	4716888086 ps
T863	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1851309101			Apr 23 04:14:39 PM PDT 24	Apr 23 04:23:58 PM PDT 24	4108886368 ps
T864	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3671424764			Apr 23 04:28:27 PM PDT 24	Apr 23 04:34:43 PM PDT 24	6493285488 ps
T865	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1856483562			Apr 23 04:07:09 PM PDT 24	Apr 23 04:18:27 PM PDT 24	5093710208 ps
T115	/workspace/coverage/default/1.chip_sw_power_sleep_load.3382275973			Apr 23 04:13:10 PM PDT 24	Apr 23 04:19:38 PM PDT 24	4333472120 ps
T324	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3151345181			Apr 23 04:10:13 PM PDT 24	Apr 23 04:18:25 PM PDT 24	5321714000 ps
T648	/workspace/coverage/default/0.chip_tap_straps_prod.7749872			Apr 23 03:54:21 PM PDT 24	Apr 23 03:56:38 PM PDT 24	3026407453 ps
T310	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2471860222			Apr 23 04:22:53 PM PDT 24	Apr 23 04:45:42 PM PDT 24	5642446510 ps
T866	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3500776206			Apr 23 03:49:46 PM PDT 24	Apr 23 03:57:18 PM PDT 24	3974699292 ps
T664	/workspace/coverage/default/73.chip_sw_all_escalation_resets.880397519			Apr 23 04:31:57 PM PDT 24	Apr 23 04:42:21 PM PDT 24	6138924544 ps
T137	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1149447402			Apr 23 04:24:42 PM PDT 24	Apr 23 04:35:15 PM PDT 24	5693953320 ps
T867	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.112210993			Apr 23 04:08:03 PM PDT 24	Apr 23 04:21:19 PM PDT 24	5163766308 ps
T868	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1598571664			Apr 23 04:08:54 PM PDT 24	Apr 23 04:12:57 PM PDT 24	2462507418 ps
T869	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1465178897			Apr 23 04:25:28 PM PDT 24	Apr 23 04:30:05 PM PDT 24	3058116742 ps
T652	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614186391			Apr 23 04:30:13 PM PDT 24	Apr 23 04:36:15 PM PDT 24	2970690340 ps