Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147927	1			T81	27		T83	7		T85	32
values[2]	5269	1			T83	7		T85	1		T86	3
values[3]	2810	1			T83	7		T502	104		T445	25
values[4]	2029	1			T83	3		T502	68		T445	11
values[5]	1592	1			T83	6		T502	24		T445	24
values[6]	1388	1			T83	12		T502	14		T445	19
values[7]	1176	1			T83	19		T502	10		T445	17
values[8]	970	1			T83	14		T502	12		T445	4
values[9]	792	1			T83	19		T502	8		T445	10
values[10]	588	1			T83	24		T445	15		T754	18
values[11]	526	1			T83	33		T445	23		T754	39
values[12]	468	1			T83	35		T445	30		T754	19
values[13]	357	1			T83	39		T445	20		T754	6
values[14]	297	1			T83	18		T445	11		T492	1
values[15]	266	1			T83	13		T445	7		T492	1
values[16]	212	1			T83	17		T445	5		T492	1
values[17]	172	1			T83	9		T445	1		T492	1
values[18]	173	1			T83	7		T445	1		T492	1
values[19]	176	1			T83	6		T445	1		T492	1
values[20]	163	1			T83	7		T445	5		T492	1
values[21]	187	1			T83	11		T445	6		T492	1
values[22]	194	1			T83	10		T445	3		T492	1
values[23]	207	1			T83	3		T445	11		T492	1
values[24]	169	1			T83	4		T445	13		T492	1
values[25]	181	1			T83	5		T445	23		T492	1
values[26]	183	1			T83	14		T445	7		T492	1
values[27]	199	1			T83	19		T445	11		T492	1
values[28]	219	1			T83	32		T445	19		T492	1
values[29]	143	1			T83	13		T445	13		T492	1
values[30]	127	1			T83	8		T445	17		T492	1
values[31]	120	1			T83	12		T445	14		T492	1
values[32]	112	1			T83	23		T445	22		T492	1
values[33]	118	1			T83	7		T445	21		T492	1
values[34]	121	1			T83	4		T445	16		T492	1
values[35]	132	1			T83	3		T445	28		T492	1
values[36]	103	1			T83	11		T445	13		T492	1
values[37]	112	1			T83	10		T445	22		T492	1
values[38]	119	1			T83	6		T445	35		T492	1
values[39]	78	1			T83	2		T445	16		T492	1
values[40]	68	1			T83	4		T445	2		T492	1
values[41]	67	1			T83	11		T492	1		T795	1
values[42]	52	1			T83	2		T492	1		T795	1
values[43]	64	1			T492	1		T795	1		T796	1
values[44]	61	1			T492	1		T795	1		T796	1
values[45]	52	1			T492	1		T795	1		T796	1
values[46]	62	1			T492	1		T795	1		T796	1
values[47]	67	1			T492	1		T795	1		T796	1
values[48]	73	1			T492	1		T795	1		T796	1
values[49]	59	1			T492	1		T795	1		T796	1
values[50]	72	1			T492	1		T795	1		T796	1
values[51]	64	1			T492	1		T795	1		T796	1
values[52]	60	1			T492	1		T795	1		T796	1
values[53]	80	1			T492	1		T795	2		T796	1
values[54]	60	1			T492	1		T795	1		T796	1
values[55]	48	1			T492	1		T795	1		T796	1
values[56]	53	1			T492	1		T795	1		T796	1
values[57]	45	1			T492	1		T795	1		T796	1
values[58]	42	1			T492	1		T795	1		T796	1
values[59]	50	1			T492	1		T795	1		T796	1
values[60]	48	1			T492	1		T795	1		T796	1
values[61]	42	1			T492	1		T795	1		T796	1
values[62]	47	1			T492	1		T795	1		T796	1
values[63]	43	1			T492	1		T795	1		T796	1
values[64]	53	1			T492	1		T795	1		T796	1
values[65]	50	1			T492	1		T795	1		T796	1
values[66]	51	1			T492	1		T795	1		T796	1
values[67]	47	1			T492	1		T795	1		T796	1
values[68]	55	1			T492	1		T795	1		T796	1
values[69]	51	1			T492	1		T795	1		T796	1
values[70]	50	1			T492	1		T795	1		T796	1
values[71]	56	1			T492	1		T795	1		T796	1
values[72]	52	1			T492	1		T795	1		T796	1
values[73]	55	1			T492	1		T795	1		T796	1
values[74]	61	1			T492	1		T795	1		T796	1
values[75]	58	1			T492	1		T795	1		T796	1
values[76]	72	1			T492	1		T795	1		T796	1
values[77]	59	1			T492	1		T795	1		T796	1
values[78]	57	1			T492	1		T795	1		T796	1
values[79]	58	1			T492	1		T795	1		T796	1
values[80]	63	1			T492	1		T795	1		T796	1
values[81]	48	1			T492	1		T795	1		T796	1
values[82]	70	1			T492	1		T795	1		T796	1
values[83]	66	1			T492	1		T795	1		T796	1
values[84]	70	1			T492	1		T795	1		T796	1
values[85]	58	1			T492	1		T795	1		T796	1
values[86]	80	1			T492	1		T795	1		T796	2
values[87]	68	1			T492	1		T795	1		T796	5
values[88]	54	1			T492	1		T795	1		T796	4
values[89]	60	1			T492	1		T795	1		T796	9
values[90]	73	1			T492	1		T795	3		T796	2
values[91]	76	1			T492	1		T795	1		T796	6
values[92]	78	1			T492	1		T795	2		T796	2
values[93]	78	1			T492	1		T795	4		T796	2
values[94]	71	1			T492	1		T795	3		T796	2
values[95]	77	1			T492	1		T795	3		T796	3
values[96]	75	1			T492	1		T795	5		T796	8
values[97]	81	1			T492	1		T795	2		T796	5
values[98]	91	1			T492	1		T795	4		T796	2
values[99]	78	1			T492	1		T795	1		T796	3
values[100]	79	1			T492	1		T795	1		T796	2
values[101]	53	1			T492	1		T795	2		T796	1
values[102]	80	1			T492	1		T795	4		T796	4
values[103]	79	1			T492	1		T795	6		T796	2
values[104]	68	1			T492	1		T795	1		T796	3
values[105]	83	1			T492	1		T795	4		T796	3
values[106]	90	1			T492	1		T795	1		T796	1
values[107]	81	1			T492	1		T795	3		T796	1
values[108]	71	1			T492	1		T795	1		T796	2
values[109]	80	1			T492	1		T795	3		T796	3
values[110]	72	1			T492	1		T795	1		T796	1
values[111]	79	1			T492	1		T795	3		T796	3
values[112]	65	1			T492	1		T795	1		T796	3
values[113]	90	1			T492	1		T795	2		T796	6
values[114]	75	1			T492	1		T795	1		T796	7
values[115]	90	1			T492	1		T795	3		T796	3
values[116]	76	1			T492	1		T795	3		T796	3
values[117]	95	1			T492	1		T795	3		T796	2
values[118]	80	1			T492	1		T795	2		T796	2
values[119]	81	1			T492	3		T795	5		T796	1
values[120]	81	1			T492	1		T795	1		T796	1
values[121]	106	1			T492	1		T795	1		T796	2
values[122]	103	1			T492	2		T795	2		T796	1
values[123]	140	1			T492	2		T795	4		T796	3
values[124]	206	1			T492	2		T795	1		T796	2
values[125]	402	1			T492	1		T795	1		T796	1
values[126]	777	1			T492	12		T795	13		T796	18
values[127]	2144	1			T492	108		T795	120		T796	92
values[128]	3576	1			T492	248		T795	176		T796	178