Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137742	1			T81	28		T85	41		T86	96
values[2]	10067	1			T81	1		T85	1		T86	2
values[3]	4240	1			T501	1		T677	87		T504	114
values[4]	2678	1			T501	1		T677	79		T504	70
values[5]	1664	1			T501	1		T677	34		T504	20
values[6]	1102	1			T501	1		T677	14		T504	14
values[7]	797	1			T501	1		T677	3		T504	7
values[8]	649	1			T501	1		T504	4		T511	2
values[9]	487	1			T501	1		T511	4		T763	3
values[10]	395	1			T501	1		T511	6		T763	19
values[11]	330	1			T501	1		T511	10		T763	6
values[12]	320	1			T501	1		T511	16		T763	8
values[13]	341	1			T501	1		T511	19		T763	5
values[14]	315	1			T501	1		T511	15		T763	6
values[15]	329	1			T501	1		T511	11		T763	2
values[16]	327	1			T501	1		T511	3		T763	8
values[17]	339	1			T501	1		T511	1		T763	2
values[18]	338	1			T501	1		T763	14		T777	3
values[19]	281	1			T501	1		T763	12		T777	1
values[20]	252	1			T501	1		T763	7		T777	5
values[21]	248	1			T501	1		T763	5		T777	3
values[22]	281	1			T501	1		T763	9		T777	6
values[23]	280	1			T501	1		T763	16		T777	2
values[24]	249	1			T501	1		T763	10		T777	1
values[25]	223	1			T501	1		T763	4		T777	5
values[26]	245	1			T501	2		T763	10		T777	2
values[27]	230	1			T501	1		T763	15		T777	5
values[28]	281	1			T501	1		T763	8		T777	2
values[29]	286	1			T501	1		T763	9		T777	2
values[30]	255	1			T501	1		T763	4		T777	3
values[31]	259	1			T501	1		T763	6		T777	1
values[32]	254	1			T501	1		T763	14		T777	2
values[33]	246	1			T501	1		T763	4		T777	1
values[34]	267	1			T501	1		T763	5		T777	3
values[35]	245	1			T501	1		T763	10		T777	2
values[36]	241	1			T501	1		T763	10		T777	1
values[37]	207	1			T501	1		T763	8		T421	12
values[38]	184	1			T501	1		T763	12		T421	6
values[39]	217	1			T501	1		T763	4		T421	16
values[40]	227	1			T501	1		T763	2		T421	13
values[41]	200	1			T501	1		T763	9		T421	4
values[42]	209	1			T501	1		T763	2		T421	6
values[43]	226	1			T501	1		T763	10		T421	6
values[44]	236	1			T501	1		T763	5		T421	7
values[45]	207	1			T501	1		T763	6		T421	9
values[46]	230	1			T501	1		T763	6		T421	5
values[47]	205	1			T501	1		T763	9		T421	2
values[48]	171	1			T501	1		T763	9		T421	5
values[49]	214	1			T501	1		T763	17		T421	6
values[50]	209	1			T501	1		T763	8		T421	10
values[51]	196	1			T501	1		T763	7		T421	6
values[52]	182	1			T501	1		T763	7		T421	13
values[53]	237	1			T501	1		T763	7		T421	7
values[54]	174	1			T501	1		T763	5		T421	5
values[55]	179	1			T501	1		T763	8		T421	6
values[56]	184	1			T501	1		T763	4		T421	5
values[57]	158	1			T501	1		T763	4		T421	5
values[58]	171	1			T501	1		T763	5		T421	3
values[59]	187	1			T501	1		T763	6		T421	5
values[60]	173	1			T501	1		T763	2		T421	2
values[61]	158	1			T501	1		T763	2		T421	8
values[62]	162	1			T501	1		T421	8		T756	1
values[63]	165	1			T501	1		T421	16		T756	1
values[64]	163	1			T501	1		T421	4		T756	1
values[65]	195	1			T501	1		T756	1		T792	16
values[66]	156	1			T501	1		T756	1		T792	10
values[67]	161	1			T501	1		T756	1		T792	11
values[68]	146	1			T501	1		T756	1		T792	11
values[69]	103	1			T501	1		T756	1		T792	18
values[70]	113	1			T501	1		T756	1		T792	18
values[71]	138	1			T501	1		T756	1		T792	9
values[72]	104	1			T501	1		T756	1		T792	14
values[73]	138	1			T501	1		T756	1		T792	17
values[74]	97	1			T501	1		T756	1		T792	15
values[75]	94	1			T501	1		T756	1		T792	22
values[76]	92	1			T501	1		T756	1		T792	14
values[77]	76	1			T501	1		T756	1		T792	16
values[78]	65	1			T501	1		T756	1		T792	6
values[79]	56	1			T501	1		T756	1		T792	10
values[80]	76	1			T501	1		T756	1		T792	13
values[81]	78	1			T501	1		T756	2		T792	23
values[82]	91	1			T501	1		T756	1		T792	25
values[83]	73	1			T501	1		T756	2		T792	19
values[84]	64	1			T501	1		T756	1		T792	12
values[85]	78	1			T501	1		T756	1		T792	18
values[86]	75	1			T501	1		T756	1		T792	19
values[87]	79	1			T501	1		T756	1		T792	18
values[88]	73	1			T501	1		T756	1		T792	13
values[89]	87	1			T501	1		T756	1		T792	12
values[90]	87	1			T501	1		T756	1		T792	15
values[91]	81	1			T501	1		T756	1		T792	12
values[92]	91	1			T501	1		T756	1		T792	10
values[93]	72	1			T501	1		T756	1		T792	11
values[94]	85	1			T501	1		T756	1		T792	22
values[95]	82	1			T501	1		T756	1		T792	23
values[96]	82	1			T501	1		T756	1		T792	17
values[97]	67	1			T501	1		T756	1		T792	12
values[98]	69	1			T501	1		T756	1		T792	4
values[99]	59	1			T501	1		T756	1		T792	4
values[100]	81	1			T501	1		T756	1		T792	12
values[101]	79	1			T501	1		T756	1		T792	8
values[102]	88	1			T501	1		T756	1		T792	8
values[103]	69	1			T501	1		T756	1		T792	2
values[104]	65	1			T501	1		T756	1		T792	3
values[105]	77	1			T501	1		T756	1		T792	4
values[106]	70	1			T501	1		T756	1		T792	4
values[107]	75	1			T501	1		T756	1		T792	3
values[108]	82	1			T501	1		T756	1		T792	3
values[109]	73	1			T501	1		T756	1		T792	6
values[110]	58	1			T501	1		T756	1		T792	4
values[111]	71	1			T501	2		T756	1		T792	5
values[112]	61	1			T501	2		T756	1		T792	1
values[113]	70	1			T501	2		T756	1		T760	1
values[114]	70	1			T501	1		T756	1		T760	1
values[115]	87	1			T501	1		T756	3		T760	2
values[116]	69	1			T501	3		T756	4		T760	2
values[117]	81	1			T501	2		T756	3		T760	2
values[118]	69	1			T501	2		T756	2		T760	2
values[119]	93	1			T501	2		T756	3		T760	2
values[120]	78	1			T501	2		T756	1		T760	2
values[121]	69	1			T501	4		T756	1		T760	1
values[122]	89	1			T501	1		T756	2		T760	3
values[123]	80	1			T501	1		T756	2		T760	2
values[124]	101	1			T501	5		T756	4		T760	5
values[125]	119	1			T501	1		T756	2		T760	2
values[126]	231	1			T501	3		T756	2		T760	4
values[127]	1031	1			T501	42		T756	30		T760	32
values[128]	6372	1			T501	397		T756	318		T760	367