Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	437	1			T83	1		T403	1		T510	4
all_values[1]	477	1			T510	4		T504	11		T508	3
all_values[2]	470	1			T510	2		T504	6		T508	3
all_values[3]	458	1			T83	1		T510	1		T504	6
all_values[4]	485	1			T510	5		T504	3		T508	5
all_values[5]	469	1			T501	3		T403	1		T510	2
all_values[6]	427	1			T510	1		T504	3		T508	7
all_values[7]	443	1			T82	1		T510	4		T504	2
all_values[8]	485	1			T510	2		T504	7		T508	5
all_values[9]	486	1			T82	1		T83	2		T501	1
all_values[10]	473	1			T83	2		T510	2		T504	1
all_values[11]	493	1			T83	1		T403	2		T510	2
all_values[12]	486	1			T82	1		T501	1		T510	4
all_values[13]	481	1			T501	1		T510	6		T504	2
all_values[14]	434	1			T501	1		T510	3		T504	2
all_values[15]	497	1			T510	3		T504	4		T508	3
all_values[16]	466	1			T510	1		T504	2		T508	2
all_values[17]	441	1			T83	2		T510	4		T504	5
all_values[18]	481	1			T510	1		T504	4		T508	4
all_values[19]	459	1			T510	3		T504	5		T508	5
all_values[20]	448	1			T403	1		T510	1		T504	5
all_values[21]	507	1			T83	1		T403	1		T510	3
all_values[22]	490	1			T510	3		T677	1		T504	4
all_values[23]	479	1			T501	1		T510	1		T504	6
all_values[24]	484	1			T82	1		T510	2		T504	5
all_values[25]	500	1			T83	1		T510	4		T504	2
all_values[26]	451	1			T83	1		T403	1		T504	3
all_values[27]	470	1			T510	3		T504	4		T508	2
all_values[28]	484	1			T403	2		T510	5		T504	1
all_values[29]	482	1			T82	1		T83	1		T501	1
all_values[30]	453	1			T501	1		T510	2		T504	3
all_values[31]	477	1			T510	1		T504	3		T502	1
all_values[32]	476	1			T83	1		T510	6		T677	1
all_values[33]	454	1			T82	1		T510	4		T504	6
all_values[34]	495	1			T403	1		T510	3		T504	2
all_values[35]	454	1			T510	2		T677	1		T504	3
all_values[36]	435	1			T510	6		T677	1		T504	2
all_values[37]	474	1			T510	5		T504	4		T508	1
all_values[38]	477	1			T403	1		T510	2		T504	2
all_values[39]	485	1			T403	1		T510	1		T504	6
all_values[40]	454	1			T501	1		T403	1		T510	1
all_values[41]	462	1			T510	2		T504	6		T502	1
all_values[42]	407	1			T83	1		T403	1		T504	6
all_values[43]	492	1			T510	2		T504	5		T508	4
all_values[44]	478	1			T82	1		T83	2		T510	2
all_values[45]	466	1			T501	2		T510	3		T504	3
all_values[46]	464	1			T510	5		T504	7		T508	4
all_values[47]	510	1			T501	1		T510	3		T677	1
all_values[48]	433	1			T510	6		T504	4		T508	2
all_values[49]	462	1			T510	2		T504	3		T508	4