Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3562	1			T510	18		T504	25		T502	8
all_values[1]	3593	1			T510	26		T504	30		T502	2
all_values[2]	3662	1			T510	31		T504	31		T502	6
all_values[3]	3635	1			T510	33		T504	22		T502	4
all_values[4]	3584	1			T510	27		T504	26		T502	2
all_values[5]	3571	1			T510	25		T504	28		T502	4
all_values[6]	3598	1			T510	20		T504	29		T502	4
all_values[7]	3552	1			T510	16		T504	38		T502	4
all_values[8]	3726	1			T510	15		T504	23		T502	2
all_values[9]	3527	1			T510	23		T504	39		T502	4
all_values[10]	3586	1			T510	20		T504	36		T502	8
all_values[11]	3537	1			T510	21		T504	28		T502	1
all_values[12]	3512	1			T510	21		T504	30		T502	3
all_values[13]	3605	1			T510	22		T504	20		T502	4
all_values[14]	3544	1			T510	26		T504	29		T502	7
all_values[15]	3660	1			T510	20		T504	31		T502	6
all_values[16]	3606	1			T510	28		T504	24		T502	8
all_values[17]	3609	1			T510	27		T504	26		T502	5
all_values[18]	3523	1			T510	29		T504	18		T502	4
all_values[19]	3513	1			T510	28		T504	18		T502	8
all_values[20]	3617	1			T510	24		T504	24		T502	5
all_values[21]	3589	1			T510	18		T504	35		T502	5
all_values[22]	3522	1			T510	22		T504	31		T502	5
all_values[23]	3544	1			T510	34		T504	16		T502	5
all_values[24]	3565	1			T510	20		T504	26		T502	4
all_values[25]	3609	1			T510	29		T504	29		T502	8
all_values[26]	3559	1			T510	19		T504	21		T502	3
all_values[27]	3611	1			T510	23		T504	22		T502	1
all_values[28]	3608	1			T510	27		T504	37		T502	5
all_values[29]	3635	1			T510	21		T504	22		T502	6
all_values[30]	3654	1			T510	32		T504	37		T502	4
all_values[31]	3577	1			T510	24		T504	29		T502	3
all_values[32]	3603	1			T510	22		T504	19		T502	5
all_values[33]	3632	1			T510	23		T504	21		T502	8
all_values[34]	3621	1			T510	21		T504	28		T502	9
all_values[35]	3612	1			T510	25		T504	26		T502	3
all_values[36]	3644	1			T510	32		T504	37		T502	4
all_values[37]	3519	1			T510	23		T504	29		T502	4
all_values[38]	3482	1			T510	24		T504	30		T502	6
all_values[39]	3582	1			T510	18		T504	28		T502	9
all_values[40]	3574	1			T510	27		T504	31		T502	7
all_values[41]	3672	1			T510	32		T504	35		T502	8
all_values[42]	3602	1			T510	19		T504	40		T502	9
all_values[43]	3656	1			T510	29		T504	39		T502	6
all_values[44]	3528	1			T510	18		T504	37		T502	9
all_values[45]	3496	1			T510	24		T504	30		T502	2
all_values[46]	3702	1			T510	27		T504	26		T502	5
all_values[47]	3562	1			T510	26		T504	22		T502	9
all_values[48]	3661	1			T510	31		T504	26		T502	7
all_values[49]	3575	1			T510	20		T504	30		T502	5
all_values[50]	3546	1			T510	22		T504	27		T502	4
all_values[51]	3565	1			T510	31		T504	37		T502	2
all_values[52]	3693	1			T510	31		T504	23		T502	5
all_values[53]	3527	1			T510	17		T504	30		T502	4
all_values[54]	3656	1			T510	20		T504	26		T502	8
all_values[55]	3655	1			T510	27		T504	26		T502	5
all_values[56]	3645	1			T510	19		T504	35		T502	4
all_values[57]	3573	1			T510	31		T504	29		T502	2
all_values[58]	3636	1			T510	27		T504	27		T502	3
all_values[59]	3607	1			T510	28		T504	25		T502	2
all_values[60]	3545	1			T510	23		T504	25		T502	1
all_values[61]	3613	1			T510	27		T504	37		T502	6
all_values[62]	3669	1			T510	32		T504	28		T502	4
all_values[63]	3505	1			T510	15		T504	21		T502	1