Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1635 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1637 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1635 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
123498 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
123570 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
123498 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
8656 |
1 |
|
|
T94 |
1 |
|
T106 |
36 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
8658 |
1 |
|
|
T94 |
1 |
|
T106 |
36 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
8656 |
1 |
|
|
T94 |
1 |
|
T106 |
36 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
205 |
1 |
|
|
T94 |
1 |
|
T106 |
58 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
205 |
1 |
|
|
T94 |
1 |
|
T106 |
58 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
205 |
1 |
|
|
T94 |
1 |
|
T106 |
58 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
3061 |
1 |
|
|
T94 |
1 |
|
T106 |
54 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
3062 |
1 |
|
|
T94 |
1 |
|
T106 |
54 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
3061 |
1 |
|
|
T94 |
1 |
|
T106 |
54 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
200 |
1 |
|
|
T94 |
1 |
|
T106 |
53 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
200 |
1 |
|
|
T94 |
1 |
|
T106 |
53 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
200 |
1 |
|
|
T94 |
1 |
|
T106 |
53 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
8331 |
1 |
|
|
T4 |
198 |
|
T94 |
1 |
|
T239 |
1733 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
8340 |
1 |
|
|
T4 |
199 |
|
T94 |
1 |
|
T239 |
1733 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
8331 |
1 |
|
|
T4 |
198 |
|
T94 |
1 |
|
T239 |
1733 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
8143 |
1 |
|
|
T94 |
1 |
|
T106 |
23 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
8146 |
1 |
|
|
T94 |
1 |
|
T106 |
23 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
8143 |
1 |
|
|
T94 |
1 |
|
T106 |
23 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
7030 |
1 |
|
|
T94 |
1 |
|
T106 |
32 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
7033 |
1 |
|
|
T94 |
1 |
|
T106 |
32 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
7030 |
1 |
|
|
T94 |
1 |
|
T106 |
32 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
381 |
1 |
|
|
T67 |
2 |
|
T4 |
10 |
|
T238 |
36 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
381 |
1 |
|
|
T67 |
2 |
|
T4 |
10 |
|
T238 |
36 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
381 |
1 |
|
|
T67 |
2 |
|
T4 |
10 |
|
T238 |
36 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
184 |
1 |
|
|
T94 |
1 |
|
T106 |
43 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
184 |
1 |
|
|
T94 |
1 |
|
T106 |
43 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
184 |
1 |
|
|
T94 |
1 |
|
T106 |
43 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
4493 |
1 |
|
|
T66 |
526 |
|
T94 |
1 |
|
T430 |
522 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
4494 |
1 |
|
|
T66 |
526 |
|
T94 |
1 |
|
T430 |
522 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
4493 |
1 |
|
|
T66 |
526 |
|
T94 |
1 |
|
T430 |
522 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
416 |
1 |
|
|
T180 |
68 |
|
T94 |
1 |
|
T106 |
38 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
416 |
1 |
|
|
T180 |
68 |
|
T94 |
1 |
|
T106 |
38 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
416 |
1 |
|
|
T180 |
68 |
|
T94 |
1 |
|
T106 |
38 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
9630 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
9631 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
9630 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1032 |
1 |
|
|
T94 |
1 |
|
T104 |
2 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1032 |
1 |
|
|
T94 |
1 |
|
T104 |
2 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1032 |
1 |
|
|
T94 |
1 |
|
T104 |
2 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1029 |
1 |
|
|
T218 |
514 |
|
T94 |
1 |
|
T104 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1029 |
1 |
|
|
T218 |
514 |
|
T94 |
1 |
|
T104 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1029 |
1 |
|
|
T218 |
514 |
|
T94 |
1 |
|
T104 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1335 |
1 |
|
|
T94 |
1 |
|
T225 |
508 |
|
T104 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1336 |
1 |
|
|
T94 |
1 |
|
T225 |
508 |
|
T104 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1335 |
1 |
|
|
T94 |
1 |
|
T225 |
508 |
|
T104 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
4583 |
1 |
|
|
T94 |
1 |
|
T106 |
42 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
4583 |
1 |
|
|
T94 |
1 |
|
T106 |
42 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
4583 |
1 |
|
|
T94 |
1 |
|
T106 |
42 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
178 |
1 |
|
|
T161 |
2 |
|
T168 |
2 |
|
T94 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
178 |
1 |
|
|
T161 |
2 |
|
T168 |
2 |
|
T94 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
178 |
1 |
|
|
T161 |
2 |
|
T168 |
2 |
|
T94 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
123701 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
123779 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
123701 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
435 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
435 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
435 |
1 |
|
|
T180 |
86 |
|
T94 |
1 |
|
T106 |
40 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
2669 |
1 |
|
|
T344 |
809 |
|
T345 |
806 |
|
T94 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
2671 |
1 |
|
|
T344 |
810 |
|
T345 |
807 |
|
T94 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
2669 |
1 |
|
|
T344 |
809 |
|
T345 |
806 |
|
T94 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
3113 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
3115 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
3113 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
4069 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
4072 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
4069 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1388699 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1388777 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1388699 |
1 |
|
|
T3 |
580 |
|
T31 |
1206 |
|
T99 |
1447 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
506 |
1 |
|
|
T46 |
1 |
|
T180 |
114 |
|
T94 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
506 |
1 |
|
|
T46 |
1 |
|
T180 |
114 |
|
T94 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
506 |
1 |
|
|
T46 |
1 |
|
T180 |
114 |
|
T94 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1645 |
1 |
|
|
T94 |
1 |
|
T104 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1647 |
1 |
|
|
T94 |
1 |
|
T104 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1645 |
1 |
|
|
T94 |
1 |
|
T104 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
52839 |
1 |
|
|
T3 |
275 |
|
T31 |
570 |
|
T99 |
687 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
52944 |
1 |
|
|
T3 |
275 |
|
T31 |
571 |
|
T99 |
687 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
52839 |
1 |
|
|
T3 |
275 |
|
T31 |
570 |
|
T99 |
687 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
820 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
821 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
820 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
3773 |
1 |
|
|
T188 |
811 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
3775 |
1 |
|
|
T188 |
811 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
3773 |
1 |
|
|
T188 |
811 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
4 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
1876 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
1876 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
1876 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
3993 |
1 |
|
|
T94 |
1 |
|
T105 |
817 |
|
T95 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
3996 |
1 |
|
|
T94 |
1 |
|
T105 |
818 |
|
T95 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
3993 |
1 |
|
|
T94 |
1 |
|
T105 |
817 |
|
T95 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
2165 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
2166 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
2165 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
2443 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
2448 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
2443 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
6251 |
1 |
|
|
T99 |
1 |
|
T275 |
1 |
|
T335 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
6274 |
1 |
|
|
T99 |
1 |
|
T275 |
1 |
|
T335 |
1 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
6251 |
1 |
|
|
T99 |
1 |
|
T275 |
1 |
|
T335 |
1 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
3012 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T106 |
36 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
3014 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T106 |
36 |
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
alert_triggered |
3012 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T106 |
36 |
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
2437 |
1 |
|
|
T143 |
811 |
|
T46 |
1 |
|
T94 |
1 |
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| alert_triggered |
2439 |
1 |
|
|
T143 |
812 |
|
T46 |
1 |
|
T94 |
1 |