| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 41.61 |
41.61 |
45.93 |
45.93 |
43.21 |
43.21 |
31.74 |
31.74 |
|
|
58.33 |
58.33 |
63.22 |
63.22 |
7.24 |
7.24 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3545476222 |
| 56.12 |
14.51 |
58.68 |
12.75 |
58.30 |
15.09 |
38.39 |
6.65 |
|
|
71.59 |
13.26 |
91.13 |
27.91 |
18.64 |
11.40 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3936657662 |
| 64.42 |
8.29 |
59.19 |
0.51 |
58.84 |
0.54 |
43.68 |
5.29 |
|
|
71.85 |
0.26 |
91.31 |
0.18 |
61.62 |
42.98 |
/workspace/coverage/default/2.chip_sw_alert_test.879841633 |
| 70.15 |
5.74 |
71.88 |
12.70 |
67.21 |
8.36 |
45.81 |
2.13 |
|
|
83.08 |
11.23 |
91.31 |
0.00 |
61.62 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1598633054 |
| 74.51 |
4.36 |
82.00 |
10.12 |
72.30 |
5.10 |
49.78 |
3.97 |
|
|
85.43 |
2.35 |
91.31 |
0.00 |
66.23 |
4.61 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4162415641 |
| 76.48 |
1.98 |
82.01 |
0.01 |
72.33 |
0.03 |
61.39 |
11.62 |
|
|
85.45 |
0.02 |
91.50 |
0.18 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.680043722 |
| 77.94 |
1.45 |
84.20 |
2.19 |
75.49 |
3.15 |
61.67 |
0.27 |
|
|
88.54 |
3.09 |
91.50 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2287649009 |
| 79.17 |
1.24 |
84.20 |
0.00 |
75.49 |
0.00 |
69.09 |
7.42 |
|
|
88.54 |
0.00 |
91.50 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1853237913 |
| 80.28 |
1.10 |
85.82 |
1.62 |
76.90 |
1.41 |
71.35 |
2.26 |
|
|
89.65 |
1.11 |
91.50 |
0.00 |
66.45 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2210009423 |
| 81.22 |
0.95 |
86.64 |
0.83 |
77.17 |
0.28 |
71.53 |
0.18 |
|
|
89.98 |
0.33 |
95.56 |
4.07 |
66.45 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1063761444 |
| 82.00 |
0.78 |
87.92 |
1.27 |
78.16 |
0.98 |
72.74 |
1.21 |
|
|
91.17 |
1.19 |
95.56 |
0.00 |
66.45 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1581551248 |
| 82.68 |
0.68 |
88.55 |
0.63 |
78.76 |
0.60 |
74.83 |
2.09 |
|
|
91.94 |
0.77 |
95.56 |
0.00 |
66.45 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1831381747 |
| 83.22 |
0.54 |
88.55 |
0.00 |
78.78 |
0.02 |
77.80 |
2.97 |
|
|
91.96 |
0.02 |
95.56 |
0.00 |
66.67 |
0.22 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4235733168 |
| 83.62 |
0.40 |
89.13 |
0.58 |
79.30 |
0.52 |
78.59 |
0.79 |
|
|
92.45 |
0.49 |
95.56 |
0.00 |
66.67 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1925485339 |
| 83.97 |
0.36 |
89.57 |
0.43 |
79.76 |
0.46 |
78.87 |
0.29 |
|
|
92.85 |
0.40 |
96.12 |
0.55 |
66.67 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1579008835 |
| 84.27 |
0.30 |
89.60 |
0.03 |
79.76 |
0.01 |
78.89 |
0.02 |
|
|
92.85 |
0.01 |
96.30 |
0.18 |
68.20 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4065228227 |
| 84.56 |
0.29 |
89.60 |
0.00 |
79.76 |
0.00 |
79.56 |
0.67 |
|
|
92.85 |
0.00 |
96.49 |
0.18 |
69.08 |
0.88 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2092295046 |
| 84.84 |
0.28 |
89.60 |
0.00 |
79.76 |
0.00 |
81.26 |
1.70 |
|
|
92.85 |
0.00 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3391839201 |
| 85.11 |
0.27 |
89.60 |
0.00 |
79.76 |
0.00 |
82.87 |
1.61 |
|
|
92.85 |
0.00 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2996170307 |
| 85.37 |
0.26 |
90.08 |
0.48 |
80.29 |
0.53 |
83.19 |
0.32 |
|
|
93.08 |
0.22 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2795831804 |
| 85.59 |
0.23 |
90.08 |
0.00 |
80.29 |
0.00 |
84.55 |
1.36 |
|
|
93.08 |
0.00 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.215601848 |
| 85.80 |
0.21 |
90.48 |
0.40 |
80.57 |
0.28 |
84.91 |
0.35 |
|
|
93.29 |
0.21 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.71472193 |
| 85.97 |
0.16 |
90.57 |
0.09 |
80.58 |
0.01 |
85.79 |
0.88 |
|
|
93.30 |
0.01 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4224747072 |
| 86.11 |
0.14 |
90.60 |
0.04 |
80.94 |
0.36 |
85.84 |
0.05 |
|
|
93.70 |
0.40 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3560964867 |
| 86.23 |
0.13 |
91.09 |
0.48 |
81.01 |
0.07 |
86.03 |
0.20 |
|
|
93.70 |
0.01 |
96.49 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2268778909 |
| 86.34 |
0.11 |
91.09 |
0.01 |
81.02 |
0.02 |
86.46 |
0.43 |
|
|
93.70 |
0.00 |
96.67 |
0.18 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3103181043 |
| 86.43 |
0.09 |
91.14 |
0.05 |
81.25 |
0.22 |
86.50 |
0.03 |
|
|
93.92 |
0.21 |
96.67 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1535916768 |
| 86.51 |
0.09 |
91.14 |
0.00 |
81.25 |
0.00 |
87.01 |
0.52 |
|
|
93.92 |
0.00 |
96.67 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3912665601 |
| 86.59 |
0.08 |
91.17 |
0.04 |
81.27 |
0.03 |
87.02 |
0.01 |
|
|
93.93 |
0.02 |
96.86 |
0.18 |
69.30 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.641927857 |
| 86.67 |
0.08 |
91.17 |
0.00 |
81.27 |
0.00 |
87.50 |
0.48 |
|
|
93.93 |
0.00 |
96.86 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.172280039 |
| 86.75 |
0.08 |
91.31 |
0.14 |
81.41 |
0.14 |
87.61 |
0.11 |
|
|
94.03 |
0.09 |
96.86 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3482828072 |
| 86.83 |
0.07 |
91.32 |
0.01 |
81.43 |
0.03 |
87.61 |
0.00 |
|
|
94.03 |
0.01 |
97.04 |
0.18 |
69.52 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898572566 |
| 86.90 |
0.07 |
91.33 |
0.01 |
81.44 |
0.01 |
87.61 |
0.01 |
|
|
94.04 |
0.01 |
97.23 |
0.18 |
69.74 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957832724 |
| 86.97 |
0.07 |
91.33 |
0.00 |
81.44 |
0.00 |
87.81 |
0.20 |
|
|
94.04 |
0.00 |
97.23 |
0.00 |
69.96 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1501888895 |
| 87.03 |
0.06 |
91.34 |
0.02 |
81.49 |
0.04 |
87.83 |
0.02 |
|
|
94.09 |
0.05 |
97.23 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1290023813 |
| 87.07 |
0.05 |
91.34 |
0.00 |
81.49 |
0.00 |
87.89 |
0.06 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2865624759 |
| 87.12 |
0.04 |
91.39 |
0.04 |
81.49 |
0.01 |
88.11 |
0.22 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.39 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.957885400 |
| 87.16 |
0.04 |
91.39 |
0.00 |
81.49 |
0.00 |
88.36 |
0.25 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.39 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.775779050 |
| 87.20 |
0.04 |
91.39 |
0.00 |
81.49 |
0.00 |
88.40 |
0.03 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078954480 |
| 87.24 |
0.04 |
91.39 |
0.00 |
81.49 |
0.00 |
88.65 |
0.25 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.61 |
0.00 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1823721225 |
| 87.28 |
0.04 |
91.39 |
0.00 |
81.49 |
0.00 |
88.66 |
0.02 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2273988304 |
| 87.32 |
0.04 |
91.39 |
0.00 |
81.49 |
0.00 |
88.68 |
0.01 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1146095714 |
| 87.36 |
0.04 |
91.39 |
0.00 |
81.50 |
0.01 |
88.68 |
0.01 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.375257686 |
| 87.40 |
0.04 |
91.39 |
0.00 |
81.50 |
0.01 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.695774629 |
| 87.43 |
0.04 |
91.39 |
0.00 |
81.50 |
0.01 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3890493115 |
| 87.47 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.01 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1533417287 |
| 87.51 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.702216247 |
| 87.54 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2929270834 |
| 87.58 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.883032190 |
| 87.62 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2419801460 |
| 87.65 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087013949 |
| 87.69 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.2105581529 |
| 87.73 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750645193 |
| 87.76 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086778911 |
| 87.80 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930270190 |
| 87.84 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2248346991 |
| 87.87 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727258403 |
| 87.91 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2881781473 |
| 87.94 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230044178 |
| 87.98 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3896407323 |
| 88.02 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.856386995 |
| 88.05 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590674722 |
| 88.09 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3083853358 |
| 88.13 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3498314104 |
| 88.16 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333616745 |
| 88.20 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.264715036 |
| 88.24 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952883225 |
| 88.27 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.586999766 |
| 88.31 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092986414 |
| 88.35 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2136684959 |
| 88.38 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2603997822 |
| 88.42 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085341409 |
| 88.46 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4179886265 |
| 88.49 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2735496793 |
| 88.53 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2689380568 |
| 88.57 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1191590639 |
| 88.60 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716665439 |
| 88.64 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.4057682460 |
| 88.68 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230116645 |
| 88.71 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3664196284 |
| 88.75 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553917484 |
| 88.79 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3075546970 |
| 88.82 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1439025298 |
| 88.86 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.928220118 |
| 88.90 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.48820476 |
| 88.93 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.909938805 |
| 88.97 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3205938429 |
| 89.00 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.211920226 |
| 89.04 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.888562350 |
| 89.08 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3837209852 |
| 89.11 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278730558 |
| 89.15 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2412495854 |
| 89.19 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2319700474 |
| 89.22 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.695424758 |
| 89.26 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3052070169 |
| 89.30 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153283558 |
| 89.33 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1873961815 |
| 89.37 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1230883156 |
| 89.41 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.378992672 |
| 89.44 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.377243220 |
| 89.48 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3729702881 |
| 89.52 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1973819704 |
| 89.55 |
0.04 |
91.39 |
0.00 |
81.50 |
0.00 |
88.68 |
0.00 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.196162113 |
| 89.59 |
0.03 |
91.39 |
0.00 |
81.50 |
0.00 |
88.89 |
0.21 |
|
|
94.09 |
0.00 |
97.23 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4194262740 |
| 89.62 |
0.03 |
91.39 |
0.00 |
81.50 |
0.00 |
88.89 |
0.01 |
|
|
94.09 |
0.00 |
97.41 |
0.18 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3550182172 |
| 89.65 |
0.03 |
91.46 |
0.08 |
81.53 |
0.03 |
88.91 |
0.02 |
|
|
94.14 |
0.05 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2597437280 |
| 89.68 |
0.03 |
91.51 |
0.05 |
81.56 |
0.03 |
88.98 |
0.07 |
|
|
94.17 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1786614332 |
| 89.71 |
0.03 |
91.59 |
0.08 |
81.56 |
0.00 |
89.07 |
0.09 |
|
|
94.17 |
0.01 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1784797322 |
| 89.73 |
0.03 |
91.64 |
0.06 |
81.61 |
0.05 |
89.08 |
0.01 |
|
|
94.23 |
0.06 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1193807092 |
| 89.76 |
0.03 |
91.67 |
0.02 |
81.61 |
0.01 |
89.22 |
0.14 |
|
|
94.23 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.711577430 |
| 89.79 |
0.03 |
91.67 |
0.00 |
81.78 |
0.17 |
89.22 |
0.00 |
|
|
94.23 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1724585601 |
| 89.82 |
0.03 |
91.73 |
0.06 |
81.84 |
0.06 |
89.23 |
0.01 |
|
|
94.26 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2574187370 |
| 89.84 |
0.02 |
91.84 |
0.11 |
81.85 |
0.01 |
89.23 |
0.01 |
|
|
94.26 |
0.01 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3070414290 |
| 89.86 |
0.02 |
91.84 |
0.00 |
81.85 |
0.00 |
89.35 |
0.12 |
|
|
94.26 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2765554341 |
| 89.88 |
0.02 |
91.84 |
0.00 |
81.85 |
0.00 |
89.46 |
0.11 |
|
|
94.26 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3770699177 |
| 89.89 |
0.02 |
91.84 |
0.00 |
81.85 |
0.00 |
89.56 |
0.10 |
|
|
94.26 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238396047 |
| 89.91 |
0.02 |
91.84 |
0.00 |
81.86 |
0.01 |
89.66 |
0.09 |
|
|
94.26 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2930763209 |
| 89.93 |
0.02 |
91.84 |
0.00 |
81.95 |
0.10 |
89.66 |
0.00 |
|
|
94.26 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3360541314 |
| 89.94 |
0.02 |
91.85 |
0.01 |
81.97 |
0.02 |
89.71 |
0.05 |
|
|
94.28 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2441130646 |
| 89.96 |
0.01 |
91.85 |
0.00 |
81.97 |
0.00 |
89.80 |
0.09 |
|
|
94.28 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2249023822 |
| 89.97 |
0.01 |
91.86 |
0.01 |
82.01 |
0.04 |
89.84 |
0.05 |
|
|
94.28 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.743723122 |
| 89.98 |
0.01 |
91.92 |
0.06 |
82.01 |
0.01 |
89.85 |
0.01 |
|
|
94.28 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1632628870 |
| 90.00 |
0.01 |
91.92 |
0.00 |
82.06 |
0.05 |
89.85 |
0.00 |
|
|
94.31 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.803666441 |
| 90.01 |
0.01 |
91.95 |
0.03 |
82.08 |
0.02 |
89.85 |
0.01 |
|
|
94.33 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.71439584 |
| 90.02 |
0.01 |
91.95 |
0.00 |
82.15 |
0.07 |
89.85 |
0.00 |
|
|
94.33 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.4082783122 |
| 90.03 |
0.01 |
91.97 |
0.02 |
82.16 |
0.01 |
89.89 |
0.03 |
|
|
94.33 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.414482701 |
| 90.04 |
0.01 |
91.97 |
0.01 |
82.20 |
0.04 |
89.90 |
0.01 |
|
|
94.33 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2265903556 |
| 90.05 |
0.01 |
92.00 |
0.03 |
82.21 |
0.01 |
89.90 |
0.01 |
|
|
94.35 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.569641559 |
| 90.06 |
0.01 |
92.02 |
0.03 |
82.22 |
0.01 |
89.91 |
0.01 |
|
|
94.36 |
0.02 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1682855778 |
| 90.07 |
0.01 |
92.02 |
0.00 |
82.22 |
0.00 |
89.95 |
0.04 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_jtag_mem_access.2241695484 |
| 90.07 |
0.01 |
92.02 |
0.00 |
82.22 |
0.00 |
90.00 |
0.04 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_init.2549243197 |
| 90.08 |
0.01 |
92.02 |
0.00 |
82.26 |
0.04 |
90.00 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3198782779 |
| 90.09 |
0.01 |
92.02 |
0.00 |
82.26 |
0.00 |
90.03 |
0.04 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3903708317 |
| 90.09 |
0.01 |
92.03 |
0.01 |
82.27 |
0.02 |
90.05 |
0.02 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3054206872 |
| 90.10 |
0.01 |
92.06 |
0.03 |
82.28 |
0.01 |
90.05 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.675059001 |
| 90.10 |
0.01 |
92.06 |
0.00 |
82.28 |
0.00 |
90.08 |
0.04 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1240008314 |
| 90.11 |
0.01 |
92.06 |
0.00 |
82.31 |
0.03 |
90.08 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4142457049 |
| 90.11 |
0.01 |
92.06 |
0.00 |
82.31 |
0.00 |
90.11 |
0.03 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3179850751 |
| 90.12 |
0.01 |
92.06 |
0.00 |
82.32 |
0.01 |
90.13 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3930422662 |
| 90.12 |
0.01 |
92.06 |
0.01 |
82.33 |
0.01 |
90.13 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4270678167 |
| 90.13 |
0.01 |
92.06 |
0.00 |
82.35 |
0.02 |
90.13 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3796347495 |
| 90.13 |
0.01 |
92.07 |
0.01 |
82.36 |
0.01 |
90.14 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1252401985 |
| 90.13 |
0.01 |
92.07 |
0.00 |
82.36 |
0.00 |
90.16 |
0.02 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3463158658 |
| 90.13 |
0.01 |
92.07 |
0.00 |
82.36 |
0.00 |
90.17 |
0.02 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1007202586 |
| 90.14 |
0.01 |
92.07 |
0.00 |
82.36 |
0.00 |
90.19 |
0.02 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1949176582 |
| 90.14 |
0.01 |
92.07 |
0.00 |
82.38 |
0.02 |
90.19 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1122380307 |
| 90.14 |
0.01 |
92.08 |
0.01 |
82.38 |
0.01 |
90.20 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.44498760 |
| 90.15 |
0.01 |
92.08 |
0.01 |
82.38 |
0.00 |
90.21 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2958737574 |
| 90.15 |
0.01 |
92.08 |
0.00 |
82.38 |
0.00 |
90.22 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2469947662 |
| 90.15 |
0.01 |
92.08 |
0.00 |
82.38 |
0.00 |
90.24 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3029895520 |
| 90.15 |
0.01 |
92.08 |
0.00 |
82.38 |
0.00 |
90.25 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1862725771 |
| 90.16 |
0.01 |
92.09 |
0.01 |
82.38 |
0.00 |
90.26 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3347235843 |
| 90.16 |
0.01 |
92.09 |
0.00 |
82.38 |
0.00 |
90.27 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.4276646941 |
| 90.16 |
0.01 |
92.09 |
0.00 |
82.38 |
0.00 |
90.28 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.rom_keymgr_functest.2991332923 |
| 90.16 |
0.01 |
92.09 |
0.00 |
82.39 |
0.01 |
90.28 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.1399449260 |
| 90.16 |
0.01 |
92.09 |
0.01 |
82.39 |
0.00 |
90.29 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4101343835 |
| 90.16 |
0.01 |
92.09 |
0.00 |
82.39 |
0.00 |
90.30 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4215656563 |
| 90.17 |
0.01 |
92.09 |
0.00 |
82.39 |
0.00 |
90.31 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2869656840 |
| 90.17 |
0.01 |
92.09 |
0.00 |
82.40 |
0.01 |
90.31 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3305407035 |
| 90.17 |
0.01 |
92.09 |
0.00 |
82.41 |
0.01 |
90.31 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1437296401 |
| 90.17 |
0.01 |
92.09 |
0.00 |
82.41 |
0.00 |
90.31 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.84119081 |
| 90.17 |
0.01 |
92.09 |
0.00 |
82.41 |
0.00 |
90.32 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1232780537 |
| 90.17 |
0.01 |
92.09 |
0.01 |
82.41 |
0.00 |
90.32 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.324330388 |
| 90.17 |
0.01 |
92.10 |
0.01 |
82.41 |
0.00 |
90.33 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2833566963 |
| 90.17 |
0.01 |
92.10 |
0.00 |
82.41 |
0.00 |
90.33 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2304593650 |
| 90.17 |
0.01 |
92.10 |
0.00 |
82.41 |
0.00 |
90.33 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3129683286 |
| 90.17 |
0.01 |
92.10 |
0.00 |
82.41 |
0.00 |
90.34 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4034214213 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.41 |
0.00 |
90.34 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3702332169 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.41 |
0.01 |
90.34 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1410935206 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.41 |
0.01 |
90.34 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3907208816 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.01 |
90.34 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3394218812 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.01 |
90.34 |
0.00 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4261394448 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.00 |
90.35 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.1872087067 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.00 |
90.35 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1546934325 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.00 |
90.35 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.949250729 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.00 |
90.35 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4126543360 |
| 90.18 |
0.01 |
92.10 |
0.00 |
82.42 |
0.00 |
90.36 |
0.01 |
|
|
94.36 |
0.00 |
97.41 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3986822418 |
| Name |
| /workspace/coverage/default/0.chip_jtag_csr_rw.2298359894 |
| /workspace/coverage/default/0.chip_jtag_mem_access.40842085 |
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1089740096 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.2177536550 |
| /workspace/coverage/default/0.chip_sw_aes_enc.141877625 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2756476256 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1256058131 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.691692188 |
| /workspace/coverage/default/0.chip_sw_aes_idle.1497470645 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.1123487258 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.3018204076 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1517072800 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3786048316 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2183913580 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.315494643 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.642664532 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1821310819 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1420843390 |
| /workspace/coverage/default/0.chip_sw_alert_test.247541015 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.3448508743 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1971848787 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2113742405 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.942865528 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3289213097 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.60838868 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2370113781 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2951429704 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1118548815 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1976762522 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3693034515 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4216391319 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1102566248 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.443834911 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3586160098 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3612522163 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.137036590 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1489786841 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1356750699 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.534959611 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3434428100 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.471019599 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2097344565 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.714776520 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2232294232 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1887709849 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.1760848102 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.1271000539 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4144764773 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.678203386 |
| /workspace/coverage/default/0.chip_sw_edn_kat.3125637483 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.3003700193 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3571444189 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3951610709 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3598331645 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.1152514682 |
| /workspace/coverage/default/0.chip_sw_example_flash.1909208310 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.3143865431 |
| /workspace/coverage/default/0.chip_sw_example_rom.2957117550 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1471051889 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.1944261095 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1805650931 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3066599420 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3587008666 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2890369488 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.149590192 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1728984833 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1144975977 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1064308247 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4242569211 |
| /workspace/coverage/default/0.chip_sw_flash_init.184417493 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1514805294 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.3845169188 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2593161855 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2667949814 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1499885604 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.643061838 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2895422104 |
| /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2053861059 |
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| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2878008868 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3392241197 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.3301638003 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.605288482 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2967281619 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3793486056 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1656616330 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3672064821 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.239758261 |
| /workspace/coverage/default/2.chip_tap_straps_dev.3100945935 |
| /workspace/coverage/default/2.chip_tap_straps_prod.784620518 |
| /workspace/coverage/default/2.chip_tap_straps_rma.2192099316 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.3334911908 |
| /workspace/coverage/default/2.rom_keymgr_functest.1184732506 |
| /workspace/coverage/default/21.chip_sw_all_escalation_resets.859789647 |
| /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755246317 |
| /workspace/coverage/default/23.chip_sw_all_escalation_resets.810040006 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.3640129168 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3322378300 |
| /workspace/coverage/default/28.chip_sw_all_escalation_resets.720592534 |
| /workspace/coverage/default/29.chip_sw_all_escalation_resets.712817725 |
| /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2772701687 |
| /workspace/coverage/default/3.chip_sw_all_escalation_resets.1639764698 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3976653387 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3775476430 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3392133410 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1873595554 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.748281863 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3556167680 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2504244934 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2385974120 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2055146364 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2181605730 |
| /workspace/coverage/default/3.chip_tap_straps_dev.3505208384 |
| /workspace/coverage/default/3.chip_tap_straps_prod.2977578919 |
| /workspace/coverage/default/3.chip_tap_straps_rma.1413185957 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.2453715731 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.96871997 |
| /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1222147628 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249126051 |
| /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2474064 |
| /workspace/coverage/default/34.chip_sw_all_escalation_resets.3576587180 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195181533 |
| /workspace/coverage/default/35.chip_sw_all_escalation_resets.2705130 |
| /workspace/coverage/default/36.chip_sw_all_escalation_resets.2165057961 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3624629728 |
| /workspace/coverage/default/37.chip_sw_all_escalation_resets.1055425672 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665703130 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.2468688537 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911728353 |
| /workspace/coverage/default/39.chip_sw_all_escalation_resets.2009550570 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4103711449 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3920334639 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1042237383 |
| /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2997898106 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.172562832 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.149397608 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.910394431 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2043754523 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.172224010 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3317894758 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.970113168 |
| /workspace/coverage/default/4.chip_tap_straps_dev.1581943895 |
| /workspace/coverage/default/4.chip_tap_straps_prod.895437081 |
| /workspace/coverage/default/4.chip_tap_straps_rma.3557027953 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.924646039 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.3501689353 |
| /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933088141 |
| /workspace/coverage/default/41.chip_sw_all_escalation_resets.2136436147 |
| /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4140791929 |
| /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992507326 |
| /workspace/coverage/default/43.chip_sw_all_escalation_resets.3089092126 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3374364238 |
| /workspace/coverage/default/45.chip_sw_all_escalation_resets.2090715244 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4067881177 |
| /workspace/coverage/default/46.chip_sw_all_escalation_resets.1836977825 |
| /workspace/coverage/default/48.chip_sw_all_escalation_resets.3785214216 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4199679901 |
| /workspace/coverage/default/5.chip_sw_all_escalation_resets.1185881002 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1715003013 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.836527366 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2406479890 |
| /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001552477 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3745576913 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.1965040448 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306737979 |
| /workspace/coverage/default/52.chip_sw_all_escalation_resets.1819974023 |
| /workspace/coverage/default/53.chip_sw_all_escalation_resets.3966335171 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.728965620 |
| /workspace/coverage/default/55.chip_sw_all_escalation_resets.3120213786 |
| /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420200691 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.2598958171 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2064465669 |
| /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1177197227 |
| /workspace/coverage/default/58.chip_sw_all_escalation_resets.4154025284 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4080822972 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.1448796799 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3147969283 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3242540329 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383567997 |
| /workspace/coverage/default/60.chip_sw_all_escalation_resets.2643049256 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.1748291132 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.2168952348 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2057238009 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.346462745 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.2654557524 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.912012676 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.1307687007 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195675458 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2351836471 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.3452612876 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.3153742890 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.1462585945 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027150182 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.508761682 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.135364163 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2136028491 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.632758816 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522710084 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.1530721427 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874257715 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.3457949859 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280855604 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.1265812134 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1680702891 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2071259649 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.140522907 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3885699348 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196678167 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.3444237364 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1135682338 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.1511140029 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2942852428 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.2013436389 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385328690 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.215760152 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.506150755 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1006154774 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.3727317022 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373815047 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.621027596 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.587289436 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1681777476 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.1881311269 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871378923 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.117730466 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441411711 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.4022450614 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.605770733 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1546882630 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.2873606021 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.663869260 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.3128554224 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052839652 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604915032 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.439272731 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1669843710 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.4018896609 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2262888012 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3834912502 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.3597098919 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.1812768227 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.1932497638 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4137369448 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1921769573 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3249629333 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2128257108 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.15117493 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2722045545 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2333357405 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3531947533 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.414482701 |
|
|
Apr 25 03:27:52 PM PDT 24 |
Apr 25 03:33:02 PM PDT 24 |
4306199340 ps |
| T2 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3626261834 |
|
|
Apr 25 03:35:30 PM PDT 24 |
Apr 25 03:47:29 PM PDT 24 |
7096566120 ps |
| T3 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3545476222 |
|
|
Apr 25 03:59:42 PM PDT 24 |
Apr 25 04:10:24 PM PDT 24 |
5977235200 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3066599420 |
|
|
Apr 25 03:25:04 PM PDT 24 |
Apr 25 03:40:41 PM PDT 24 |
5655035357 ps |
| T31 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4235733168 |
|
|
Apr 25 03:37:08 PM PDT 24 |
Apr 25 03:45:34 PM PDT 24 |
5000833743 ps |
| T99 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.835924288 |
|
|
Apr 25 03:30:30 PM PDT 24 |
Apr 25 03:43:06 PM PDT 24 |
5530122228 ps |
| T65 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078954480 |
|
|
Apr 25 03:58:02 PM PDT 24 |
Apr 25 04:05:54 PM PDT 24 |
4071109740 ps |
| T66 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2210009423 |
|
|
Apr 25 03:55:57 PM PDT 24 |
Apr 25 04:01:28 PM PDT 24 |
4058160220 ps |
| T63 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3571640258 |
|
|
Apr 25 03:41:20 PM PDT 24 |
Apr 25 04:04:21 PM PDT 24 |
9262961352 ps |
| T108 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2895422104 |
|
|
Apr 25 03:23:19 PM PDT 24 |
Apr 25 03:33:11 PM PDT 24 |
4453762136 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3273937028 |
|
|
Apr 25 03:34:28 PM PDT 24 |
Apr 25 03:38:02 PM PDT 24 |
2901209304 ps |
| T244 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3054206872 |
|
|
Apr 25 03:39:27 PM PDT 24 |
Apr 25 03:50:16 PM PDT 24 |
3817518952 ps |
| T133 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1501888895 |
|
|
Apr 25 03:53:46 PM PDT 24 |
Apr 25 04:01:30 PM PDT 24 |
4384307984 ps |
| T64 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2812798720 |
|
|
Apr 25 03:36:59 PM PDT 24 |
Apr 25 03:53:33 PM PDT 24 |
7344418444 ps |
| T157 |
/workspace/coverage/default/0.rom_keymgr_functest.2991332923 |
|
|
Apr 25 03:28:32 PM PDT 24 |
Apr 25 03:37:11 PM PDT 24 |
5366623320 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1138760127 |
|
|
Apr 25 03:44:34 PM PDT 24 |
Apr 25 04:07:07 PM PDT 24 |
7449420480 ps |
| T4 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3391839201 |
|
|
Apr 25 03:25:54 PM PDT 24 |
Apr 25 04:02:45 PM PDT 24 |
24733317311 ps |
| T163 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2865624759 |
|
|
Apr 25 03:56:56 PM PDT 24 |
Apr 25 04:07:31 PM PDT 24 |
4712924520 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4144657692 |
|
|
Apr 25 03:37:31 PM PDT 24 |
Apr 25 03:54:27 PM PDT 24 |
5342890080 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1783905764 |
|
|
Apr 25 03:24:34 PM PDT 24 |
Apr 25 03:38:57 PM PDT 24 |
4619785940 ps |
| T17 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3561390008 |
|
|
Apr 25 03:25:08 PM PDT 24 |
Apr 25 03:58:17 PM PDT 24 |
7963463056 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.4252637167 |
|
|
Apr 25 03:50:37 PM PDT 24 |
Apr 25 03:55:10 PM PDT 24 |
3122864500 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.547929882 |
|
|
Apr 25 03:43:22 PM PDT 24 |
Apr 25 03:47:04 PM PDT 24 |
3343400660 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1579008835 |
|
|
Apr 25 03:40:13 PM PDT 24 |
Apr 25 03:47:04 PM PDT 24 |
3578893632 ps |
| T124 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3727317022 |
|
|
Apr 25 03:59:29 PM PDT 24 |
Apr 25 04:08:50 PM PDT 24 |
5013130024 ps |
| T125 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.149397608 |
|
|
Apr 25 03:49:34 PM PDT 24 |
Apr 25 03:58:32 PM PDT 24 |
4253399190 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1940907359 |
|
|
Apr 25 03:27:04 PM PDT 24 |
Apr 25 03:29:32 PM PDT 24 |
2322315592 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3626294086 |
|
|
Apr 25 03:48:10 PM PDT 24 |
Apr 25 03:51:32 PM PDT 24 |
2313938011 ps |
| T45 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2360858216 |
|
|
Apr 25 03:31:28 PM PDT 24 |
Apr 25 03:32:59 PM PDT 24 |
2397857909 ps |
| T127 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.680043722 |
|
|
Apr 25 03:33:57 PM PDT 24 |
Apr 25 03:43:05 PM PDT 24 |
5449614296 ps |
| T128 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874257715 |
|
|
Apr 25 03:57:01 PM PDT 24 |
Apr 25 04:02:58 PM PDT 24 |
3176274190 ps |
| T129 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2765554341 |
|
|
Apr 25 03:32:47 PM PDT 24 |
Apr 25 03:37:52 PM PDT 24 |
2531189315 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.277363125 |
|
|
Apr 25 03:48:35 PM PDT 24 |
Apr 25 03:51:54 PM PDT 24 |
3151446372 ps |
| T5 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3806380291 |
|
|
Apr 25 03:45:49 PM PDT 24 |
Apr 25 04:26:04 PM PDT 24 |
19468462757 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1614735608 |
|
|
Apr 25 03:48:32 PM PDT 24 |
Apr 25 03:52:55 PM PDT 24 |
2924859800 ps |
| T15 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2332861605 |
|
|
Apr 25 03:34:57 PM PDT 24 |
Apr 25 03:41:33 PM PDT 24 |
4543467600 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3882567899 |
|
|
Apr 25 03:27:23 PM PDT 24 |
Apr 25 03:31:42 PM PDT 24 |
3075891952 ps |
| T69 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3567188804 |
|
|
Apr 25 03:37:19 PM PDT 24 |
Apr 25 03:40:37 PM PDT 24 |
2486571604 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1063761444 |
|
|
Apr 25 03:28:25 PM PDT 24 |
Apr 25 03:34:24 PM PDT 24 |
2977948392 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4242569211 |
|
|
Apr 25 03:25:40 PM PDT 24 |
Apr 25 03:36:18 PM PDT 24 |
4903499602 ps |
| T178 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.912012676 |
|
|
Apr 25 03:58:07 PM PDT 24 |
Apr 25 04:06:17 PM PDT 24 |
3879435736 ps |
| T179 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4067881177 |
|
|
Apr 25 03:56:16 PM PDT 24 |
Apr 25 04:04:06 PM PDT 24 |
3689858856 ps |
| T312 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1144975977 |
|
|
Apr 25 03:27:11 PM PDT 24 |
Apr 25 03:45:27 PM PDT 24 |
5624704030 ps |
| T265 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.387680228 |
|
|
Apr 25 03:34:29 PM PDT 24 |
Apr 25 03:45:32 PM PDT 24 |
5198488888 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3067092436 |
|
|
Apr 25 03:43:37 PM PDT 24 |
Apr 25 04:12:36 PM PDT 24 |
11969094693 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1363233824 |
|
|
Apr 25 03:36:13 PM PDT 24 |
Apr 25 03:43:52 PM PDT 24 |
4626822360 ps |
| T299 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1781653563 |
|
|
Apr 25 03:36:51 PM PDT 24 |
Apr 25 03:45:46 PM PDT 24 |
4272480240 ps |
| T182 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1146095714 |
|
|
Apr 25 03:55:50 PM PDT 24 |
Apr 25 04:06:51 PM PDT 24 |
5496736544 ps |
| T70 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3103181043 |
|
|
Apr 25 03:37:26 PM PDT 24 |
Apr 25 03:47:38 PM PDT 24 |
5818111174 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_power_idle_load.195522153 |
|
|
Apr 25 03:40:05 PM PDT 24 |
Apr 25 03:52:03 PM PDT 24 |
4728202372 ps |
| T188 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2654557524 |
|
|
Apr 25 03:56:30 PM PDT 24 |
Apr 25 04:08:08 PM PDT 24 |
5397182376 ps |
| T181 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1290023813 |
|
|
Apr 25 03:53:33 PM PDT 24 |
Apr 25 04:02:51 PM PDT 24 |
4301215652 ps |
| T300 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2890369488 |
|
|
Apr 25 03:25:46 PM PDT 24 |
Apr 25 03:45:41 PM PDT 24 |
5840878509 ps |
| T512 |
/workspace/coverage/default/1.chip_sw_aes_entropy.418991214 |
|
|
Apr 25 03:33:14 PM PDT 24 |
Apr 25 03:36:21 PM PDT 24 |
2758567940 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3031161677 |
|
|
Apr 25 03:27:59 PM PDT 24 |
Apr 25 03:32:29 PM PDT 24 |
2888070040 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4224747072 |
|
|
Apr 25 03:28:08 PM PDT 24 |
Apr 25 03:30:12 PM PDT 24 |
3212168416 ps |
| T513 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.75373084 |
|
|
Apr 25 03:37:27 PM PDT 24 |
Apr 25 03:41:27 PM PDT 24 |
2925277031 ps |
| T16 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1697398947 |
|
|
Apr 25 03:47:53 PM PDT 24 |
Apr 25 03:52:18 PM PDT 24 |
2221700134 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3915028756 |
|
|
Apr 25 03:24:32 PM PDT 24 |
Apr 25 03:46:16 PM PDT 24 |
8287471036 ps |
| T357 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.375257686 |
|
|
Apr 25 03:59:27 PM PDT 24 |
Apr 25 04:09:48 PM PDT 24 |
4698343220 ps |
| T78 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2495384607 |
|
|
Apr 25 03:45:57 PM PDT 24 |
Apr 25 04:54:32 PM PDT 24 |
24878666259 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3693034515 |
|
|
Apr 25 03:26:27 PM PDT 24 |
Apr 25 03:36:43 PM PDT 24 |
4235856246 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2574187370 |
|
|
Apr 25 03:29:50 PM PDT 24 |
Apr 25 03:37:28 PM PDT 24 |
4840231896 ps |
| T335 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.447942350 |
|
|
Apr 25 03:42:18 PM PDT 24 |
Apr 25 04:13:59 PM PDT 24 |
12363128639 ps |
| T73 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2935655340 |
|
|
Apr 25 03:36:03 PM PDT 24 |
Apr 25 03:46:02 PM PDT 24 |
3824806036 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2370113781 |
|
|
Apr 25 03:26:46 PM PDT 24 |
Apr 25 03:41:02 PM PDT 24 |
11385443066 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2690303109 |
|
|
Apr 25 03:27:16 PM PDT 24 |
Apr 25 03:35:10 PM PDT 24 |
3449815400 ps |
| T247 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.172562832 |
|
|
Apr 25 03:49:17 PM PDT 24 |
Apr 25 04:21:41 PM PDT 24 |
7974308484 ps |
| T386 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3901102601 |
|
|
Apr 25 03:25:29 PM PDT 24 |
Apr 25 03:28:37 PM PDT 24 |
2317380320 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1507569981 |
|
|
Apr 25 03:39:44 PM PDT 24 |
Apr 25 03:48:53 PM PDT 24 |
5852919000 ps |
| T151 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1581551248 |
|
|
Apr 25 03:26:57 PM PDT 24 |
Apr 25 03:38:32 PM PDT 24 |
4618830424 ps |
| T218 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3374364238 |
|
|
Apr 25 03:55:35 PM PDT 24 |
Apr 25 04:00:33 PM PDT 24 |
2815552590 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1751847870 |
|
|
Apr 25 03:44:59 PM PDT 24 |
Apr 25 04:12:19 PM PDT 24 |
11020282440 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2538007051 |
|
|
Apr 25 03:36:45 PM PDT 24 |
Apr 25 03:44:39 PM PDT 24 |
4488800772 ps |
| T338 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3128554224 |
|
|
Apr 25 04:00:23 PM PDT 24 |
Apr 25 04:10:28 PM PDT 24 |
5415308056 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1542065031 |
|
|
Apr 25 03:40:32 PM PDT 24 |
Apr 25 03:52:49 PM PDT 24 |
4328511670 ps |
| T46 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3936657662 |
|
|
Apr 25 03:29:43 PM PDT 24 |
Apr 25 04:09:41 PM PDT 24 |
18827965454 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3179850751 |
|
|
Apr 25 03:24:22 PM PDT 24 |
Apr 25 03:33:54 PM PDT 24 |
4291424958 ps |
| T344 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3597098919 |
|
|
Apr 25 03:59:01 PM PDT 24 |
Apr 25 04:08:30 PM PDT 24 |
4219559120 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3236244800 |
|
|
Apr 25 03:25:09 PM PDT 24 |
Apr 25 03:29:12 PM PDT 24 |
2815793624 ps |
| T211 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2242599965 |
|
|
Apr 25 03:45:06 PM PDT 24 |
Apr 25 03:51:43 PM PDT 24 |
4775075142 ps |
| T403 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2597419356 |
|
|
Apr 25 03:39:56 PM PDT 24 |
Apr 25 03:43:48 PM PDT 24 |
2037924008 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1720938690 |
|
|
Apr 25 03:44:40 PM PDT 24 |
Apr 25 04:21:21 PM PDT 24 |
8074124490 ps |
| T134 |
/workspace/coverage/default/0.chip_tap_straps_dev.2760830787 |
|
|
Apr 25 03:24:20 PM PDT 24 |
Apr 25 03:28:54 PM PDT 24 |
3432865414 ps |
| T79 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3598331645 |
|
|
Apr 25 03:29:30 PM PDT 24 |
Apr 25 03:37:56 PM PDT 24 |
3859599020 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2666049220 |
|
|
Apr 25 03:23:35 PM PDT 24 |
Apr 25 03:43:48 PM PDT 24 |
7251062616 ps |
| T514 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1735791087 |
|
|
Apr 25 03:47:35 PM PDT 24 |
Apr 25 04:06:10 PM PDT 24 |
5552726958 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1590410660 |
|
|
Apr 25 03:32:38 PM PDT 24 |
Apr 25 03:48:05 PM PDT 24 |
5699970588 ps |
| T435 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755246317 |
|
|
Apr 25 03:52:44 PM PDT 24 |
Apr 25 03:59:41 PM PDT 24 |
3708748824 ps |
| T249 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.239758261 |
|
|
Apr 25 03:40:47 PM PDT 24 |
Apr 25 03:52:17 PM PDT 24 |
4094887664 ps |
| T334 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2958737574 |
|
|
Apr 25 03:23:34 PM PDT 24 |
Apr 25 03:35:13 PM PDT 24 |
7513681124 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.743723122 |
|
|
Apr 25 03:34:24 PM PDT 24 |
Apr 25 04:24:17 PM PDT 24 |
13071767865 ps |
| T343 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1191590639 |
|
|
Apr 25 03:54:12 PM PDT 24 |
Apr 25 04:06:19 PM PDT 24 |
6422352146 ps |
| T345 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1973819704 |
|
|
Apr 25 04:00:57 PM PDT 24 |
Apr 25 04:12:43 PM PDT 24 |
6342468408 ps |
| T389 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2733654278 |
|
|
Apr 25 03:31:16 PM PDT 24 |
Apr 25 03:36:57 PM PDT 24 |
2778521136 ps |
| T339 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1533417287 |
|
|
Apr 25 03:54:43 PM PDT 24 |
Apr 25 04:04:57 PM PDT 24 |
4825939702 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4144764773 |
|
|
Apr 25 03:25:27 PM PDT 24 |
Apr 25 03:37:45 PM PDT 24 |
5060233990 ps |
| T196 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.58355302 |
|
|
Apr 25 03:40:30 PM PDT 24 |
Apr 25 03:53:10 PM PDT 24 |
4630423544 ps |
| T362 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2009550570 |
|
|
Apr 25 03:54:48 PM PDT 24 |
Apr 25 04:08:05 PM PDT 24 |
6483781008 ps |
| T515 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4247608821 |
|
|
Apr 25 03:40:45 PM PDT 24 |
Apr 25 03:57:37 PM PDT 24 |
5522686960 ps |
| T248 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1873595554 |
|
|
Apr 25 03:48:54 PM PDT 24 |
Apr 25 04:18:51 PM PDT 24 |
7965050760 ps |
| T276 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.215601848 |
|
|
Apr 25 03:33:56 PM PDT 24 |
Apr 25 03:52:38 PM PDT 24 |
4960350920 ps |
| T432 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2689380568 |
|
|
Apr 25 03:53:18 PM PDT 24 |
Apr 25 04:03:43 PM PDT 24 |
5684027620 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2042887852 |
|
|
Apr 25 03:40:27 PM PDT 24 |
Apr 25 03:53:52 PM PDT 24 |
4946008238 ps |
| T47 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1089740096 |
|
|
Apr 25 03:27:02 PM PDT 24 |
Apr 25 03:33:31 PM PDT 24 |
3990842872 ps |
| T93 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.374172595 |
|
|
Apr 25 03:35:32 PM PDT 24 |
Apr 25 03:50:46 PM PDT 24 |
11461830883 ps |
| T137 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3912665601 |
|
|
Apr 25 03:28:49 PM PDT 24 |
Apr 25 05:05:28 PM PDT 24 |
43056368751 ps |
| T94 |
/workspace/coverage/default/2.chip_sw_alert_test.879841633 |
|
|
Apr 25 03:44:38 PM PDT 24 |
Apr 25 03:50:06 PM PDT 24 |
2782642664 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3948199703 |
|
|
Apr 25 03:45:29 PM PDT 24 |
Apr 25 03:55:38 PM PDT 24 |
4694979740 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1670632805 |
|
|
Apr 25 03:43:03 PM PDT 24 |
Apr 25 04:51:12 PM PDT 24 |
17145557576 ps |
| T378 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3314037640 |
|
|
Apr 25 03:29:41 PM PDT 24 |
Apr 25 03:39:37 PM PDT 24 |
4553250568 ps |
| T315 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.284975258 |
|
|
Apr 25 03:43:29 PM PDT 24 |
Apr 25 03:49:40 PM PDT 24 |
3866450256 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3913033188 |
|
|
Apr 25 03:47:08 PM PDT 24 |
Apr 25 04:04:14 PM PDT 24 |
7650268520 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4137373013 |
|
|
Apr 25 03:47:39 PM PDT 24 |
Apr 25 03:56:29 PM PDT 24 |
4597073760 ps |
| T381 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1524613403 |
|
|
Apr 25 03:44:07 PM PDT 24 |
Apr 25 03:49:00 PM PDT 24 |
2998480373 ps |
| T225 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553917484 |
|
|
Apr 25 03:54:39 PM PDT 24 |
Apr 25 03:59:56 PM PDT 24 |
3359678392 ps |
| T71 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4285513458 |
|
|
Apr 25 03:43:48 PM PDT 24 |
Apr 25 03:51:09 PM PDT 24 |
5146534809 ps |
| T363 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2667653183 |
|
|
Apr 25 03:25:18 PM PDT 24 |
Apr 25 04:14:42 PM PDT 24 |
25599782120 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3415010419 |
|
|
Apr 25 03:41:18 PM PDT 24 |
Apr 25 04:05:28 PM PDT 24 |
13395888296 ps |
| T400 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306737979 |
|
|
Apr 25 04:02:32 PM PDT 24 |
Apr 25 04:09:39 PM PDT 24 |
4067489210 ps |
| T72 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1831381747 |
|
|
Apr 25 03:39:42 PM PDT 24 |
Apr 25 04:25:15 PM PDT 24 |
18344768186 ps |
| T152 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1598633054 |
|
|
Apr 25 03:26:31 PM PDT 24 |
Apr 25 03:50:12 PM PDT 24 |
6666596024 ps |
| T100 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1784797322 |
|
|
Apr 25 03:36:44 PM PDT 24 |
Apr 25 03:43:02 PM PDT 24 |
4448641183 ps |
| T342 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3311543745 |
|
|
Apr 25 03:51:39 PM PDT 24 |
Apr 25 04:20:53 PM PDT 24 |
9191545456 ps |
| T516 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1125929205 |
|
|
Apr 25 03:46:30 PM PDT 24 |
Apr 25 03:49:53 PM PDT 24 |
2358372392 ps |
| T153 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3024331646 |
|
|
Apr 25 03:38:59 PM PDT 24 |
Apr 25 03:42:57 PM PDT 24 |
2888650250 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1944261095 |
|
|
Apr 25 03:26:14 PM PDT 24 |
Apr 25 03:34:34 PM PDT 24 |
4028224166 ps |
| T517 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.970113168 |
|
|
Apr 25 03:49:09 PM PDT 24 |
Apr 25 03:59:10 PM PDT 24 |
4280718846 ps |
| T518 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3129683286 |
|
|
Apr 25 03:24:21 PM PDT 24 |
Apr 25 03:30:22 PM PDT 24 |
6597974770 ps |
| T251 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3070414290 |
|
|
Apr 25 03:30:57 PM PDT 24 |
Apr 25 03:34:49 PM PDT 24 |
3481351514 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.229860885 |
|
|
Apr 25 03:33:25 PM PDT 24 |
Apr 25 03:41:39 PM PDT 24 |
4964320920 ps |
| T340 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.695424758 |
|
|
Apr 25 03:56:50 PM PDT 24 |
Apr 25 04:03:49 PM PDT 24 |
4045996344 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.44498760 |
|
|
Apr 25 03:23:43 PM PDT 24 |
Apr 25 03:34:25 PM PDT 24 |
4511857674 ps |
| T353 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3576587180 |
|
|
Apr 25 03:55:48 PM PDT 24 |
Apr 25 04:05:29 PM PDT 24 |
5487141552 ps |
| T55 |
/workspace/coverage/default/1.chip_jtag_mem_access.2241695484 |
|
|
Apr 25 03:29:40 PM PDT 24 |
Apr 25 03:56:21 PM PDT 24 |
13823578759 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2795831804 |
|
|
Apr 25 03:25:51 PM PDT 24 |
Apr 25 03:33:37 PM PDT 24 |
5346443844 ps |
| T519 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.692710243 |
|
|
Apr 25 03:43:06 PM PDT 24 |
Apr 25 03:53:15 PM PDT 24 |
5802927410 ps |
| T520 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3500750014 |
|
|
Apr 25 03:54:06 PM PDT 24 |
Apr 25 04:03:18 PM PDT 24 |
3479514864 ps |
| T246 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1656616330 |
|
|
Apr 25 03:40:19 PM PDT 24 |
Apr 25 03:49:14 PM PDT 24 |
4410388540 ps |
| T521 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1236498027 |
|
|
Apr 25 03:29:37 PM PDT 24 |
Apr 25 03:49:24 PM PDT 24 |
5202311020 ps |
| T207 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3628452067 |
|
|
Apr 25 03:29:13 PM PDT 24 |
Apr 25 03:34:21 PM PDT 24 |
3429768950 ps |
| T7 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2287649009 |
|
|
Apr 25 03:35:00 PM PDT 24 |
Apr 25 03:39:06 PM PDT 24 |
3213586787 ps |
| T522 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2534347188 |
|
|
Apr 25 03:27:31 PM PDT 24 |
Apr 25 03:32:06 PM PDT 24 |
2584205892 ps |
| T56 |
/workspace/coverage/default/2.chip_jtag_mem_access.2299087091 |
|
|
Apr 25 03:38:12 PM PDT 24 |
Apr 25 04:01:22 PM PDT 24 |
13562711200 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1181111549 |
|
|
Apr 25 03:26:59 PM PDT 24 |
Apr 25 03:47:20 PM PDT 24 |
21986141568 ps |
| T155 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2930763209 |
|
|
Apr 25 03:24:01 PM PDT 24 |
Apr 25 03:28:01 PM PDT 24 |
2272353352 ps |
| T85 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.569641559 |
|
|
Apr 25 03:25:13 PM PDT 24 |
Apr 25 03:34:44 PM PDT 24 |
6176794792 ps |
| T220 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2029107971 |
|
|
Apr 25 03:40:15 PM PDT 24 |
Apr 25 03:51:05 PM PDT 24 |
4286155544 ps |
| T523 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3340801384 |
|
|
Apr 25 03:39:50 PM PDT 24 |
Apr 25 03:42:58 PM PDT 24 |
2022376900 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2192920735 |
|
|
Apr 25 03:42:24 PM PDT 24 |
Apr 25 03:52:22 PM PDT 24 |
4755108010 ps |
| T524 |
/workspace/coverage/default/0.chip_sw_aes_idle.1497470645 |
|
|
Apr 25 03:25:56 PM PDT 24 |
Apr 25 03:30:01 PM PDT 24 |
2521696190 ps |
| T525 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3055182524 |
|
|
Apr 25 03:46:54 PM PDT 24 |
Apr 25 03:51:47 PM PDT 24 |
2920010947 ps |
| T105 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.4022450614 |
|
|
Apr 25 04:04:42 PM PDT 24 |
Apr 25 04:15:43 PM PDT 24 |
4967624492 ps |
| T114 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1286071712 |
|
|
Apr 25 03:44:54 PM PDT 24 |
Apr 25 03:51:58 PM PDT 24 |
4573319118 ps |
| T115 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1997775439 |
|
|
Apr 25 03:26:32 PM PDT 24 |
Apr 25 03:37:26 PM PDT 24 |
5615282542 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.501030236 |
|
|
Apr 25 03:28:54 PM PDT 24 |
Apr 25 03:34:06 PM PDT 24 |
2639157996 ps |
| T117 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2514910359 |
|
|
Apr 25 03:43:39 PM PDT 24 |
Apr 25 03:46:29 PM PDT 24 |
2698429596 ps |
| T118 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3347235843 |
|
|
Apr 25 03:23:37 PM PDT 24 |
Apr 25 03:38:16 PM PDT 24 |
5332800098 ps |
| T119 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2239984189 |
|
|
Apr 25 03:29:38 PM PDT 24 |
Apr 25 03:40:53 PM PDT 24 |
4123875008 ps |
| T120 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.48820476 |
|
|
Apr 25 03:54:41 PM PDT 24 |
Apr 25 04:03:24 PM PDT 24 |
4160225628 ps |
| T121 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1680702891 |
|
|
Apr 25 03:58:01 PM PDT 24 |
Apr 25 04:04:54 PM PDT 24 |
4159262980 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1901861361 |
|
|
Apr 25 03:30:32 PM PDT 24 |
Apr 25 03:43:26 PM PDT 24 |
5379539240 ps |
| T526 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2506315298 |
|
|
Apr 25 03:44:19 PM PDT 24 |
Apr 25 03:48:00 PM PDT 24 |
2777790740 ps |
| T202 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2052510316 |
|
|
Apr 25 03:30:12 PM PDT 24 |
Apr 25 03:32:06 PM PDT 24 |
2515327115 ps |
| T240 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.277536578 |
|
|
Apr 25 03:36:22 PM PDT 24 |
Apr 25 03:43:01 PM PDT 24 |
4113159240 ps |
| T436 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3444237364 |
|
|
Apr 25 03:57:58 PM PDT 24 |
Apr 25 04:07:34 PM PDT 24 |
4947897196 ps |
| T260 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2043754523 |
|
|
Apr 25 03:50:06 PM PDT 24 |
Apr 25 03:58:07 PM PDT 24 |
4314276060 ps |
| T388 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1525711596 |
|
|
Apr 25 03:36:09 PM PDT 24 |
Apr 25 03:42:34 PM PDT 24 |
2813071478 ps |
| T76 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1823721225 |
|
|
Apr 25 03:48:34 PM PDT 24 |
Apr 25 05:14:33 PM PDT 24 |
28977971208 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_edn_kat.3125637483 |
|
|
Apr 25 03:24:08 PM PDT 24 |
Apr 25 03:32:22 PM PDT 24 |
3921839162 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2092295046 |
|
|
Apr 25 03:42:33 PM PDT 24 |
Apr 25 03:58:05 PM PDT 24 |
9733615636 ps |
| T527 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1658589439 |
|
|
Apr 25 03:27:23 PM PDT 24 |
Apr 25 03:32:47 PM PDT 24 |
2599474700 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.109835212 |
|
|
Apr 25 03:46:55 PM PDT 24 |
Apr 25 03:58:37 PM PDT 24 |
7685075240 ps |
| T528 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3487771397 |
|
|
Apr 25 03:33:35 PM PDT 24 |
Apr 25 03:37:44 PM PDT 24 |
3075669907 ps |
| T430 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1273952935 |
|
|
Apr 25 03:53:30 PM PDT 24 |
Apr 25 04:00:05 PM PDT 24 |
3557548104 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_alert_test.2312348322 |
|
|
Apr 25 03:32:18 PM PDT 24 |
Apr 25 03:37:52 PM PDT 24 |
3123505880 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3463158658 |
|
|
Apr 25 03:22:46 PM PDT 24 |
Apr 25 03:26:01 PM PDT 24 |
3325082980 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4065228227 |
|
|
Apr 25 03:24:05 PM PDT 24 |
Apr 25 03:33:14 PM PDT 24 |
4537357646 ps |
| T101 |
/workspace/coverage/default/2.chip_tap_straps_rma.2192099316 |
|
|
Apr 25 03:45:23 PM PDT 24 |
Apr 25 03:51:35 PM PDT 24 |
4487385884 ps |
| T529 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1180103081 |
|
|
Apr 25 03:44:28 PM PDT 24 |
Apr 25 03:47:39 PM PDT 24 |
2641866134 ps |
| T462 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.621027596 |
|
|
Apr 25 03:58:07 PM PDT 24 |
Apr 25 04:06:07 PM PDT 24 |
3921311832 ps |
| T464 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195181533 |
|
|
Apr 25 03:55:08 PM PDT 24 |
Apr 25 04:01:36 PM PDT 24 |
3789639676 ps |
| T135 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1438728535 |
|
|
Apr 25 03:47:07 PM PDT 24 |
Apr 25 03:56:36 PM PDT 24 |
5107332308 ps |
| T530 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2259218828 |
|
|
Apr 25 03:23:49 PM PDT 24 |
Apr 25 03:42:17 PM PDT 24 |
7553838786 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.303003816 |
|
|
Apr 25 03:40:33 PM PDT 24 |
Apr 25 03:48:51 PM PDT 24 |
4370109922 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3672064821 |
|
|
Apr 25 03:39:52 PM PDT 24 |
Apr 25 03:47:13 PM PDT 24 |
4377305856 ps |
| T19 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2862281872 |
|
|
Apr 25 03:52:18 PM PDT 24 |
Apr 25 04:00:36 PM PDT 24 |
4303498560 ps |
| T364 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.84102740 |
|
|
Apr 25 03:42:12 PM PDT 24 |
Apr 25 03:47:53 PM PDT 24 |
3511529502 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3903708317 |
|
|
Apr 25 03:23:38 PM PDT 24 |
Apr 25 04:54:07 PM PDT 24 |
43819700478 ps |
| T25 |
/workspace/coverage/default/2.chip_sw_gpio.71472193 |
|
|
Apr 25 03:41:05 PM PDT 24 |
Apr 25 03:47:41 PM PDT 24 |
3567891322 ps |
| T145 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1410935206 |
|
|
Apr 25 03:26:01 PM PDT 24 |
Apr 25 03:37:15 PM PDT 24 |
3757428646 ps |
| T531 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1152514682 |
|
|
Apr 25 03:24:54 PM PDT 24 |
Apr 25 03:29:01 PM PDT 24 |
2296018754 ps |
| T90 |
/workspace/coverage/default/0.chip_tap_straps_rma.1872087067 |
|
|
Apr 25 03:27:31 PM PDT 24 |
Apr 25 03:40:07 PM PDT 24 |
7357804560 ps |
| T532 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.369723293 |
|
|
Apr 25 03:29:12 PM PDT 24 |
Apr 25 03:51:41 PM PDT 24 |
7983547652 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4057660671 |
|
|
Apr 25 03:43:28 PM PDT 24 |
Apr 25 03:50:02 PM PDT 24 |
6407577184 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3796818052 |
|
|
Apr 25 03:35:21 PM PDT 24 |
Apr 25 03:42:50 PM PDT 24 |
4786924416 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1703211549 |
|
|
Apr 25 03:27:45 PM PDT 24 |
Apr 25 03:35:41 PM PDT 24 |
5382232129 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.137431711 |
|
|
Apr 25 03:23:51 PM PDT 24 |
Apr 25 03:29:59 PM PDT 24 |
6841837688 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2065615604 |
|
|
Apr 25 03:41:33 PM PDT 24 |
Apr 25 03:46:01 PM PDT 24 |
3010979400 ps |
| T535 |
/workspace/coverage/default/2.chip_sw_example_flash.3489794266 |
|
|
Apr 25 03:39:35 PM PDT 24 |
Apr 25 03:41:55 PM PDT 24 |
2625090650 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2833566963 |
|
|
Apr 25 03:34:32 PM PDT 24 |
Apr 25 03:39:24 PM PDT 24 |
2710947772 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1742544910 |
|
|
Apr 25 03:24:57 PM PDT 24 |
Apr 25 03:26:39 PM PDT 24 |
2120381251 ps |
| T267 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1328298004 |
|
|
Apr 25 03:41:17 PM PDT 24 |
Apr 25 03:52:23 PM PDT 24 |
5484898272 ps |
| T536 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2123195592 |
|
|
Apr 25 03:43:16 PM PDT 24 |
Apr 25 04:11:06 PM PDT 24 |
9496038976 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_hmac_enc.767862013 |
|
|
Apr 25 03:36:27 PM PDT 24 |
Apr 25 03:40:44 PM PDT 24 |
2696268536 ps |
| T174 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.3966808537 |
|
|
Apr 25 03:33:50 PM PDT 24 |
Apr 25 03:42:15 PM PDT 24 |
3145391376 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3284701790 |
|
|
Apr 25 03:29:12 PM PDT 24 |
Apr 25 03:35:13 PM PDT 24 |
3239892137 ps |
| T500 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.605770733 |
|
|
Apr 25 03:58:24 PM PDT 24 |
Apr 25 04:04:22 PM PDT 24 |
4305472842 ps |
| T537 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.748401561 |
|
|
Apr 25 03:52:07 PM PDT 24 |
Apr 25 04:24:19 PM PDT 24 |
8186385324 ps |
| T214 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3796347495 |
|
|
Apr 25 03:35:09 PM PDT 24 |
Apr 25 03:46:55 PM PDT 24 |
4704076352 ps |
| T538 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3516635892 |
|
|
Apr 25 03:52:18 PM PDT 24 |
Apr 25 04:05:37 PM PDT 24 |
5026303808 ps |
| T326 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.215760152 |
|
|
Apr 25 03:50:17 PM PDT 24 |
Apr 25 04:00:03 PM PDT 24 |
6861917190 ps |
| T169 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.298211569 |
|
|
Apr 25 03:34:35 PM PDT 24 |
Apr 25 03:44:33 PM PDT 24 |
4542902141 ps |
| T170 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2904401121 |
|
|
Apr 25 03:35:20 PM PDT 24 |
Apr 25 03:48:42 PM PDT 24 |
8596527948 ps |
| T221 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.741858225 |
|
|
Apr 25 03:28:58 PM PDT 24 |
Apr 25 03:43:00 PM PDT 24 |
4943677420 ps |
| T264 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2824117793 |
|
|
Apr 25 03:51:51 PM PDT 24 |
Apr 25 04:35:33 PM PDT 24 |
12457933214 ps |
| T539 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3002353960 |
|
|
Apr 25 03:46:14 PM PDT 24 |
Apr 25 03:58:29 PM PDT 24 |
4493748000 ps |
| T209 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3694951236 |
|
|
Apr 25 03:31:38 PM PDT 24 |
Apr 25 03:39:24 PM PDT 24 |
3622422360 ps |
| T540 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3527484640 |
|
|
Apr 25 03:36:02 PM PDT 24 |
Apr 25 03:40:57 PM PDT 24 |
2419871992 ps |
| T427 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3890493115 |
|
|
Apr 25 03:53:53 PM PDT 24 |
Apr 25 04:03:54 PM PDT 24 |
4963156020 ps |
| T96 |
/workspace/coverage/default/0.chip_sw_alert_test.247541015 |
|
|
Apr 25 03:24:54 PM PDT 24 |
Apr 25 03:32:04 PM PDT 24 |
3107463068 ps |
| T189 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3885699348 |
|
|
Apr 25 03:58:16 PM PDT 24 |
Apr 25 04:05:31 PM PDT 24 |
3723851018 ps |
| T438 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911728353 |
|
|
Apr 25 03:55:14 PM PDT 24 |
Apr 25 04:02:34 PM PDT 24 |
3319127682 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2414715648 |
|
|
Apr 25 03:34:43 PM PDT 24 |
Apr 25 03:52:47 PM PDT 24 |
4621003098 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.775779050 |
|
|
Apr 25 03:26:31 PM PDT 24 |
Apr 25 03:35:59 PM PDT 24 |
7005905763 ps |
| T541 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2301767416 |
|
|
Apr 25 03:41:06 PM PDT 24 |
Apr 25 03:49:09 PM PDT 24 |
8189764400 ps |
| T51 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1682471849 |
|
|
Apr 25 03:47:14 PM PDT 24 |
Apr 25 04:10:54 PM PDT 24 |
22042070500 ps |
| T542 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.506150755 |
|
|
Apr 25 03:51:26 PM PDT 24 |
Apr 25 03:59:40 PM PDT 24 |
4042989800 ps |
| T20 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1786614332 |
|
|
Apr 25 03:24:00 PM PDT 24 |
Apr 25 03:50:51 PM PDT 24 |
23454651620 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3680092695 |
|
|
Apr 25 03:35:01 PM PDT 24 |
Apr 25 03:40:00 PM PDT 24 |
3055848893 ps |
| T544 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.160373856 |
|
|
Apr 25 03:35:38 PM PDT 24 |
Apr 25 03:42:43 PM PDT 24 |
3886599176 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3482828072 |
|
|
Apr 25 03:48:01 PM PDT 24 |
Apr 25 04:10:57 PM PDT 24 |
17505344224 ps |
| T475 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2705130 |
|
|
Apr 25 03:54:39 PM PDT 24 |
Apr 25 04:03:42 PM PDT 24 |
4983390900 ps |
| T545 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3572649760 |
|
|
Apr 25 03:49:02 PM PDT 24 |
Apr 25 03:53:13 PM PDT 24 |
3157514836 ps |
| T350 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801491961 |
|
|
Apr 25 03:39:56 PM PDT 24 |
Apr 25 03:51:11 PM PDT 24 |
4664382929 ps |
| T277 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3083853358 |
|
|
Apr 25 03:53:28 PM PDT 24 |
Apr 25 04:04:49 PM PDT 24 |
6086434616 ps |
| T190 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2057238009 |
|
|
Apr 25 03:57:38 PM PDT 24 |
Apr 25 04:04:12 PM PDT 24 |
3258579240 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1977394844 |
|
|
Apr 25 03:41:34 PM PDT 24 |
Apr 25 04:00:29 PM PDT 24 |
8746403884 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3408454043 |
|
|
Apr 25 03:29:06 PM PDT 24 |
Apr 25 03:40:32 PM PDT 24 |
7625265532 ps |
| T499 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373815047 |
|
|
Apr 25 03:59:14 PM PDT 24 |
Apr 25 04:05:34 PM PDT 24 |
3280538300 ps |
| T546 |
/workspace/coverage/default/1.chip_tap_straps_prod.3295073690 |
|
|
Apr 25 03:37:55 PM PDT 24 |
Apr 25 04:11:27 PM PDT 24 |
15332949092 ps |
| T205 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3216756174 |
|
|
Apr 25 03:46:33 PM PDT 24 |
Apr 25 03:57:37 PM PDT 24 |
5733579159 ps |
| T547 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1673779184 |
|
|
Apr 25 03:42:54 PM PDT 24 |
Apr 25 03:47:42 PM PDT 24 |
3154019844 ps |
| T548 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.642421890 |
|
|
Apr 25 03:30:12 PM PDT 24 |
Apr 25 03:39:21 PM PDT 24 |
4132221320 ps |
| T549 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3587008666 |
|
|
Apr 25 03:26:49 PM PDT 24 |
Apr 25 03:47:24 PM PDT 24 |
7499146200 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1853237913 |
|
|
Apr 25 03:23:34 PM PDT 24 |
Apr 25 05:04:20 PM PDT 24 |
47947964322 ps |
| T397 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2117089558 |
|
|
Apr 25 03:33:12 PM PDT 24 |
Apr 25 03:50:22 PM PDT 24 |
4749255602 ps |
| T428 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3153742890 |
|
|
Apr 25 03:57:01 PM PDT 24 |
Apr 25 04:07:12 PM PDT 24 |
4734525864 ps |
| T109 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027150182 |
|
|
Apr 25 03:51:19 PM PDT 24 |
Apr 25 04:00:30 PM PDT 24 |
3752598990 ps |
| T476 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2598958171 |
|
|
Apr 25 03:55:34 PM PDT 24 |
Apr 25 04:03:59 PM PDT 24 |
4790159500 ps |