Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165105	1			T76	28		T77	105		T78	52
values[2]	4412	1			T76	3		T476	4		T235	1
values[3]	2234	1			T478	1		T386	25		T667	7
values[4]	1528	1			T386	8		T667	5		T391	43
values[5]	1312	1			T386	8		T667	4		T391	38
values[6]	1102	1			T386	2		T667	3		T391	19
values[7]	881	1			T667	2		T391	37		T668	1
values[8]	716	1			T667	1		T391	39		T668	1
values[9]	570	1			T667	3		T391	7		T668	1
values[10]	612	1			T667	2		T391	8		T668	1
values[11]	615	1			T667	1		T391	12		T668	1
values[12]	574	1			T667	1		T391	10		T668	1
values[13]	555	1			T667	2		T391	13		T668	1
values[14]	497	1			T667	4		T391	18		T668	1
values[15]	495	1			T667	3		T391	9		T668	1
values[16]	492	1			T667	1		T391	4		T668	1
values[17]	448	1			T667	3		T668	1		T547	2
values[18]	423	1			T667	1		T668	1		T547	1
values[19]	352	1			T667	2		T668	1		T547	2
values[20]	324	1			T667	1		T668	1		T547	1
values[21]	241	1			T667	2		T668	1		T547	3
values[22]	195	1			T667	1		T668	1		T547	4
values[23]	160	1			T667	2		T668	1		T547	3
values[24]	159	1			T667	1		T668	1		T547	1
values[25]	159	1			T667	5		T668	1		T547	3
values[26]	179	1			T667	4		T668	1		T547	3
values[27]	163	1			T667	2		T668	1		T547	2
values[28]	194	1			T667	3		T668	1		T547	1
values[29]	156	1			T667	1		T668	1		T547	2
values[30]	124	1			T667	1		T668	1		T547	5
values[31]	83	1			T667	4		T668	1		T547	3
values[32]	97	1			T667	4		T668	1		T547	1
values[33]	108	1			T667	4		T668	1		T547	4
values[34]	104	1			T667	1		T668	1		T547	4
values[35]	95	1			T667	3		T668	1		T547	2
values[36]	77	1			T667	2		T668	1		T547	1
values[37]	78	1			T667	2		T668	1		T547	2
values[38]	76	1			T667	1		T668	1		T547	2
values[39]	63	1			T667	2		T668	1		T547	3
values[40]	84	1			T667	2		T668	1		T547	5
values[41]	90	1			T667	7		T668	1		T547	2
values[42]	93	1			T667	8		T668	1		T547	2
values[43]	98	1			T667	4		T668	1		T547	3
values[44]	85	1			T667	1		T668	1		T547	2
values[45]	90	1			T667	3		T668	1		T547	2
values[46]	76	1			T667	1		T668	1		T547	1
values[47]	71	1			T667	1		T668	1		T547	2
values[48]	50	1			T667	3		T668	1		T547	1
values[49]	57	1			T667	1		T668	1		T547	5
values[50]	48	1			T667	1		T668	1		T547	2
values[51]	44	1			T667	2		T668	1		T547	3
values[52]	43	1			T667	5		T668	1		T547	2
values[53]	50	1			T667	2		T668	1		T547	2
values[54]	47	1			T667	2		T668	1		T547	5
values[55]	55	1			T667	4		T668	1		T547	2
values[56]	43	1			T667	3		T668	1		T547	3
values[57]	44	1			T667	3		T668	1		T547	2
values[58]	47	1			T667	2		T668	1		T547	3
values[59]	41	1			T667	1		T668	1		T547	1
values[60]	42	1			T667	2		T668	1		T547	2
values[61]	56	1			T667	7		T668	1		T547	3
values[62]	44	1			T667	4		T668	1		T547	2
values[63]	46	1			T667	4		T668	1		T547	2
values[64]	55	1			T667	9		T668	1		T547	2
values[65]	41	1			T667	1		T668	1		T547	3
values[66]	45	1			T667	4		T668	1		T547	3
values[67]	46	1			T667	5		T668	1		T547	2
values[68]	41	1			T667	5		T668	1		T547	3
values[69]	55	1			T667	6		T668	1		T547	4
values[70]	44	1			T667	4		T668	1		T547	3
values[71]	51	1			T667	6		T668	1		T547	6
values[72]	51	1			T667	3		T668	1		T547	5
values[73]	45	1			T667	2		T668	1		T547	4
values[74]	51	1			T667	1		T668	1		T547	5
values[75]	48	1			T667	1		T668	1		T547	2
values[76]	51	1			T667	2		T668	1		T547	2
values[77]	49	1			T667	2		T668	1		T547	3
values[78]	50	1			T667	1		T668	1		T547	2
values[79]	64	1			T667	3		T668	1		T547	5
values[80]	60	1			T667	1		T668	1		T547	2
values[81]	71	1			T667	2		T668	1		T547	3
values[82]	65	1			T667	3		T668	1		T547	3
values[83]	58	1			T667	4		T668	1		T547	4
values[84]	55	1			T667	3		T668	1		T547	1
values[85]	48	1			T667	1		T668	1		T547	3
values[86]	64	1			T667	1		T668	1		T547	2
values[87]	52	1			T667	2		T668	1		T547	2
values[88]	67	1			T667	3		T668	1		T547	1
values[89]	63	1			T667	2		T668	1		T547	2
values[90]	62	1			T667	1		T668	1		T547	1
values[91]	58	1			T667	1		T668	1		T547	2
values[92]	71	1			T667	2		T668	1		T547	4
values[93]	78	1			T667	5		T668	1		T547	3
values[94]	64	1			T667	6		T668	1		T547	2
values[95]	67	1			T667	8		T668	1		T547	1
values[96]	55	1			T667	2		T668	2		T547	2
values[97]	60	1			T667	1		T668	4		T547	1
values[98]	82	1			T667	4		T668	3		T547	3
values[99]	57	1			T667	2		T668	1		T547	1
values[100]	61	1			T667	3		T668	2		T547	3
values[101]	69	1			T667	2		T668	5		T547	2
values[102]	87	1			T667	3		T668	7		T547	2
values[103]	70	1			T667	6		T668	5		T547	2
values[104]	82	1			T667	4		T668	1		T547	7
values[105]	90	1			T667	6		T668	1		T547	4
values[106]	84	1			T667	6		T668	3		T547	5
values[107]	76	1			T667	3		T668	5		T547	3
values[108]	72	1			T667	6		T668	2		T547	7
values[109]	59	1			T667	3		T668	1		T547	6
values[110]	76	1			T667	4		T668	1		T547	7
values[111]	96	1			T667	3		T668	1		T547	5
values[112]	68	1			T667	2		T668	2		T547	5
values[113]	88	1			T667	4		T668	1		T547	3
values[114]	87	1			T667	8		T668	1		T547	4
values[115]	80	1			T667	8		T668	2		T547	3
values[116]	77	1			T667	6		T668	1		T547	6
values[117]	92	1			T667	8		T668	3		T547	3
values[118]	82	1			T667	5		T668	5		T547	2
values[119]	105	1			T667	3		T668	2		T547	3
values[120]	79	1			T667	3		T668	1		T547	2
values[121]	87	1			T667	4		T668	2		T547	3
values[122]	90	1			T667	10		T668	1		T547	9
values[123]	110	1			T667	4		T668	2		T547	20
values[124]	198	1			T667	8		T668	3		T547	39
values[125]	321	1			T667	29		T668	3		T547	49
values[126]	759	1			T667	56		T668	12		T547	49
values[127]	2520	1			T667	28		T668	110		T547	24
values[128]	4420	1			T667	3		T668	288		T547	1