Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	95.50	94.59	95.66		95.37	97.38	99.57

Total tests in report: 2792

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.50	40.50	45.68	45.68	44.24	44.24	32.02	32.02			58.51	58.51	62.11	62.11	0.43	0.43	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.69210117
51.63	11.13	57.29	11.61	57.62	13.39	34.74	2.72			70.57	12.06	88.72	26.62	0.82	0.39	/workspace/coverage/default/0.chip_jtag_csr_rw.3398484815
56.81	5.18	68.55	11.26	65.11	7.49	37.26	2.52			80.40	9.83	88.72	0.00	0.82	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.840581375
61.86	5.05	68.58	0.03	66.16	1.05	37.26	0.00			80.41	0.01	88.72	0.00	30.01	29.19	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1860438892
65.86	4.00	73.08	4.51	67.98	1.82	42.02	4.76			80.62	0.21	88.72	0.00	42.74	12.74	/workspace/coverage/cover_reg_top/48.xbar_stress_all.2574715435
69.08	3.22	73.08	0.00	68.67	0.70	42.02	0.00			80.86	0.25	88.72	0.00	61.13	18.39	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.699206914
72.03	2.95	73.08	0.00	68.67	0.00	59.53	17.51			80.86	0.00	88.91	0.18	61.13	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2878801971
74.36	2.33	78.21	5.12	72.49	3.82	63.01	3.48			82.40	1.54	88.91	0.00	61.13	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.529862896
76.22	1.86	78.21	0.00	72.49	0.01	63.01	0.00			82.40	0.00	88.91	0.00	72.27	11.14	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1300408558
78.04	1.82	80.76	2.56	74.86	2.36	65.30	2.30			84.67	2.27	90.20	1.29	72.44	0.16	/workspace/coverage/default/2.chip_jtag_csr_rw.1922407621
79.32	1.28	80.83	0.06	74.86	0.01	72.93	7.63			84.67	0.00	90.20	0.00	72.44	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.485212504
80.45	1.13	80.95	0.13	75.01	0.15	77.09	4.16			84.71	0.04	90.39	0.18	74.57	2.14	/workspace/coverage/default/0.chip_sw_alert_test.464028070
81.54	1.08	82.38	1.43	75.99	0.98	79.00	1.91			85.94	1.23	91.13	0.74	74.77	0.20	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1535021433
82.59	1.05	84.07	1.69	76.76	0.77	80.56	1.56			86.00	0.06	91.13	0.00	76.99	2.22	/workspace/coverage/cover_reg_top/79.xbar_error_random.3351831865
83.63	1.04	84.07	0.00	77.04	0.28	80.56	0.00			86.08	0.08	91.13	0.00	82.88	5.89	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1973149072
84.46	0.83	85.38	1.32	79.61	2.57	81.03	0.47			86.39	0.31	91.13	0.00	83.20	0.32	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3285682161
85.24	0.78	86.53	1.14	81.25	1.64	81.26	0.23			88.08	1.69	91.13	0.00	83.20	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2209207576
86.01	0.77	87.05	0.52	81.60	0.35	84.45	3.19			88.66	0.58	91.13	0.00	83.20	0.00	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1139377043
86.76	0.74	87.22	0.17	81.69	0.09	84.46	0.02			88.77	0.11	95.19	4.07	83.20	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.503465187
87.46	0.70	88.45	1.23	82.72	1.03	85.22	0.75			89.95	1.19	95.19	0.00	83.20	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1464996593
88.09	0.63	89.41	0.96	83.49	0.77	85.86	0.64			90.82	0.87	95.75	0.55	83.20	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1315465907
88.68	0.59	89.41	0.00	83.52	0.03	85.86	0.00			90.82	0.00	95.75	0.00	86.72	3.52	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1130492179
89.21	0.53	89.41	0.00	83.52	0.00	85.86	0.00			90.82	0.00	95.75	0.00	89.88	3.16	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2135418796
89.73	0.52	89.45	0.04	86.20	2.68	85.86	0.00			90.83	0.01	95.75	0.00	90.28	0.40	/workspace/coverage/cover_reg_top/22.chip_tl_errors.3505582345
90.23	0.50	90.37	0.91	87.09	0.89	86.32	0.45			91.54	0.72	95.75	0.00	90.28	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.3118943298
90.70	0.47	90.37	0.00	87.09	0.00	86.32	0.00			91.54	0.00	95.75	0.00	93.11	2.83	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3234996115
91.15	0.45	91.15	0.78	87.60	0.51	86.93	0.61			92.34	0.80	95.75	0.00	93.11	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1991223932
91.57	0.42	91.84	0.70	88.44	0.84	87.04	0.11			93.00	0.66	95.93	0.18	93.13	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230180230
91.95	0.39	92.44	0.60	88.99	0.54	87.71	0.66			93.52	0.52	95.93	0.00	93.13	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3060458502
92.28	0.32	92.47	0.04	89.11	0.12	87.71	0.00			93.55	0.02	95.93	0.00	94.89	1.76	/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1864967991
92.58	0.30	92.47	0.00	89.11	0.01	89.34	1.63			93.55	0.00	96.12	0.18	94.89	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1000816229
92.83	0.25	92.52	0.05	89.19	0.08	90.55	1.21			93.72	0.17	96.12	0.00	94.89	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2169487512
93.06	0.23	92.52	0.00	89.48	0.29	90.55	0.00			93.75	0.03	96.12	0.00	95.93	1.05	/workspace/coverage/cover_reg_top/45.xbar_stress_all.122801661
93.28	0.22	92.92	0.40	89.83	0.35	90.70	0.15			94.20	0.45	96.12	0.00	95.93	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.4172594394
93.49	0.21	93.75	0.84	90.00	0.17	90.87	0.17			94.27	0.07	96.12	0.00	95.93	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2081418654
93.68	0.19	93.75	0.00	90.05	0.05	90.87	0.00			94.27	0.00	96.12	0.00	97.02	1.08	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3414519022
93.84	0.17	93.75	0.00	91.02	0.97	90.87	0.00			94.27	0.00	96.12	0.00	97.04	0.02	/workspace/coverage/cover_reg_top/6.chip_tl_errors.2797908646
94.00	0.16	93.75	0.00	91.08	0.07	90.87	0.00			94.27	0.00	96.12	0.00	97.91	0.87	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4254241776
94.15	0.15	93.97	0.22	91.41	0.33	91.22	0.35			94.27	0.00	96.12	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2069643535
94.28	0.13	94.32	0.35	91.54	0.12	91.23	0.01			94.35	0.07	96.30	0.18	97.92	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1787422462
94.40	0.12	94.37	0.05	91.85	0.32	91.27	0.04			94.69	0.35	96.30	0.00	97.92	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2556150963
94.52	0.12	94.38	0.01	91.86	0.01	91.77	0.50			94.69	0.00	96.49	0.18	97.92	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2050654083
94.63	0.12	94.49	0.11	92.01	0.16	91.90	0.13			94.82	0.12	96.67	0.18	97.92	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1597602628
94.73	0.10	94.51	0.03	92.03	0.02	92.42	0.52			94.83	0.02	96.67	0.00	97.92	0.00	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1867035924
94.82	0.09	94.51	0.00	92.03	0.00	92.77	0.35			94.83	0.00	96.86	0.18	97.92	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.796454400
94.90	0.08	94.51	0.00	92.03	0.00	93.25	0.48			94.83	0.00	96.86	0.00	97.92	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1481601413
94.98	0.08	94.51	0.00	92.03	0.00	93.70	0.45			94.83	0.00	96.86	0.00	97.92	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1488821102
95.05	0.07	94.55	0.03	92.22	0.19	93.72	0.02			95.02	0.19	96.86	0.00	97.92	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1905868691
95.12	0.07	94.55	0.00	92.63	0.41	93.72	0.00			95.02	0.00	96.86	0.00	97.92	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3476273830
95.17	0.05	94.58	0.03	92.65	0.02	93.79	0.07			95.04	0.02	97.04	0.18	97.92	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3113285744
95.22	0.05	94.58	0.00	92.70	0.05	93.79	0.00			95.06	0.02	97.04	0.00	98.16	0.23	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3753403283
95.27	0.05	94.63	0.05	92.72	0.02	93.96	0.17			95.08	0.02	97.04	0.00	98.16	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1803716542
95.31	0.04	94.63	0.00	92.76	0.04	93.96	0.00			95.08	0.00	97.04	0.00	98.37	0.21	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.209802788
95.35	0.04	94.64	0.01	92.78	0.01	93.96	0.00			95.10	0.02	97.23	0.18	98.38	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2919194109
95.39	0.04	94.64	0.00	92.80	0.03	94.17	0.20			95.10	0.00	97.23	0.00	98.39	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3795092975
95.43	0.04	94.64	0.01	92.82	0.01	94.18	0.01			95.11	0.01	97.41	0.18	98.40	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3504621810
95.46	0.04	94.64	0.00	93.04	0.22	94.18	0.00			95.11	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.2339420620
95.50	0.03	94.72	0.08	93.04	0.00	94.28	0.11			95.12	0.01	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2375599304
95.53	0.03	94.76	0.04	93.13	0.10	94.28	0.00			95.18	0.06	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3929960737
95.56	0.03	94.76	0.00	93.31	0.17	94.28	0.00			95.18	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3408698745
95.58	0.03	94.76	0.00	93.31	0.00	94.45	0.17			95.18	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4233011478
95.61	0.03	94.82	0.07	93.33	0.03	94.47	0.01			95.23	0.05	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1594171899
95.64	0.03	94.82	0.00	93.33	0.00	94.62	0.16			95.23	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2829075303
95.66	0.03	94.88	0.06	93.36	0.03	94.69	0.06			95.23	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1166233
95.69	0.02	94.90	0.01	93.41	0.05	94.77	0.08			95.24	0.01	97.41	0.00	98.40	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2265895197
95.71	0.02	94.90	0.00	93.41	0.00	94.91	0.15			95.24	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.587903006
95.73	0.02	94.96	0.06	93.46	0.05	94.92	0.01			95.26	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2830729412
95.76	0.02	94.96	0.00	93.50	0.05	94.92	0.00			95.26	0.00	97.41	0.00	98.48	0.08	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3007325743
95.77	0.02	94.97	0.01	93.54	0.04	94.98	0.06			95.26	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.24763256
95.79	0.02	94.97	0.00	93.64	0.10	94.98	0.00			95.26	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2203278397
95.81	0.02	94.97	0.00	93.68	0.04	94.98	0.00			95.28	0.02	97.41	0.00	98.53	0.05	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.391568530
95.83	0.02	94.97	0.00	93.68	0.00	95.08	0.10			95.28	0.00	97.41	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.980230837
95.84	0.02	94.97	0.00	93.77	0.09	95.08	0.00			95.28	0.00	97.41	0.00	98.54	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1653525386
95.86	0.02	94.97	0.00	93.79	0.02	95.08	0.00			95.28	0.00	97.41	0.00	98.61	0.07	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2054579926
95.87	0.01	94.97	0.00	93.79	0.00	95.17	0.08			95.28	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2259251106
95.89	0.01	94.98	0.01	93.81	0.01	95.22	0.05			95.29	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_stream.2342284082
95.90	0.01	94.98	0.00	93.89	0.08	95.22	0.00			95.29	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3340592892
95.91	0.01	95.00	0.03	93.92	0.04	95.23	0.01			95.29	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2715463177
95.92	0.01	95.04	0.04	93.94	0.02	95.23	0.00			95.29	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.120583654
95.93	0.01	95.07	0.04	93.97	0.02	95.23	0.00			95.30	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.374916861
95.94	0.01	95.10	0.03	93.98	0.01	95.26	0.03			95.30	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2010168682
95.95	0.01	95.10	0.00	93.98	0.00	95.26	0.00			95.30	0.00	97.41	0.00	98.67	0.06	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.507880210
95.96	0.01	95.10	0.00	94.02	0.04	95.26	0.00			95.32	0.02	97.41	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all.910709777
95.97	0.01	95.12	0.03	94.02	0.01	95.26	0.01			95.34	0.02	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3150250267
95.98	0.01	95.12	0.00	94.08	0.05	95.26	0.00			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2285569205
95.99	0.01	95.13	0.01	94.09	0.02	95.28	0.01			95.34	0.01	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.264156886
96.00	0.01	95.14	0.01	94.13	0.03	95.28	0.01			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4171948958
96.00	0.01	95.14	0.00	94.17	0.04	95.28	0.00			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_gpio.927690367
96.01	0.01	95.14	0.00	94.17	0.00	95.32	0.04			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3808402860
96.02	0.01	95.14	0.00	94.17	0.00	95.36	0.04			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2736491860
96.02	0.01	95.14	0.00	94.21	0.04	95.36	0.00			95.34	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2002125031
96.03	0.01	95.14	0.00	94.21	0.00	95.36	0.00			95.34	0.00	97.41	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.270755364
96.03	0.01	95.14	0.00	94.21	0.00	95.36	0.00			95.34	0.00	97.41	0.00	98.74	0.04	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.743007896
96.04	0.01	95.14	0.00	94.21	0.00	95.38	0.02			95.34	0.00	97.41	0.00	98.75	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.4199156873
96.04	0.01	95.14	0.00	94.23	0.03	95.38	0.00			95.35	0.01	97.41	0.00	98.75	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.182636982
96.05	0.01	95.14	0.00	94.23	0.00	95.41	0.03			95.35	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3702884094
96.06	0.01	95.14	0.00	94.24	0.01	95.43	0.02			95.35	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2524134603
96.06	0.01	95.14	0.00	94.24	0.00	95.46	0.03			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.843143043
96.07	0.01	95.14	0.01	94.26	0.02	95.46	0.01			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_rw.3672407704
96.07	0.01	95.14	0.00	94.29	0.03	95.46	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all.404735330
96.08	0.01	95.14	0.00	94.31	0.03	95.46	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all.2420239208
96.08	0.01	95.14	0.00	94.34	0.03	95.46	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2195796255
96.08	0.01	95.14	0.00	94.37	0.03	95.46	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.4094128302
96.09	0.01	95.14	0.00	94.37	0.00	95.49	0.02			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4021722173
96.09	0.01	95.14	0.00	94.37	0.00	95.51	0.02			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1454789245
96.10	0.01	95.14	0.00	94.39	0.02	95.51	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.903010100
96.10	0.01	95.14	0.00	94.41	0.02	95.51	0.00			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.248766502
96.10	0.01	95.15	0.01	94.41	0.00	95.52	0.01			95.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.3599852731
96.11	0.01	95.15	0.00	94.42	0.01	95.52	0.00			95.35	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1707292731
96.11	0.01	95.15	0.00	94.42	0.00	95.54	0.02			95.35	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1284096107
96.11	0.01	95.15	0.00	94.44	0.02	95.54	0.00			95.35	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all.1975603909
96.11	0.01	95.15	0.00	94.46	0.02	95.54	0.00			95.35	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3410145365
96.12	0.01	95.15	0.00	94.46	0.00	95.54	0.01			95.35	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2705332633
96.12	0.01	95.15	0.00	94.46	0.00	95.55	0.01			95.35	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.112180451
96.12	0.01	95.15	0.00	94.47	0.01	95.55	0.01			95.35	0.00	97.41	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4128889303
96.13	0.01	95.15	0.00	94.47	0.01	95.55	0.00			95.35	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.724714578
96.13	0.01	95.15	0.00	94.48	0.01	95.55	0.00			95.35	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2058068716
96.13	0.01	95.15	0.00	94.50	0.01	95.55	0.00			95.35	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/1.chip_sw_gpio.2235439897
96.13	0.01	95.16	0.01	94.51	0.01	95.55	0.00			95.35	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2337727328
96.14	0.01	95.17	0.01	94.51	0.00	95.56	0.01			95.35	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1970149446
96.14	0.01	95.17	0.00	94.51	0.00	95.56	0.01			95.35	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.805619528
96.14	0.01	95.18	0.01	94.51	0.00	95.56	0.01			95.35	0.00	97.41	0.00	98.83	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2181385121
96.14	0.01	95.18	0.01	94.51	0.01	95.57	0.01			95.35	0.00	97.41	0.00	98.83	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc.420095400
96.14	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2803621295
96.15	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2736408972
96.15	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.466469307
96.15	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441088846
96.15	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.4219166971
96.15	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2971034674
96.16	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3213683000
96.16	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4150487716
96.16	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942163424
96.16	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180838802
96.16	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3408157708
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1967504962
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076023900
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.743130288
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.934408570
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.707442736
96.17	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.832689189
96.18	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739872247
96.18	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3382127242
96.18	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2575725414
96.18	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673406129
96.18	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.956300590
96.19	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3073604335
96.19	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.713709090
96.19	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.149835545
96.19	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.4294911211
96.19	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770532072
96.20	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2727424975
96.20	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.604322613
96.20	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.4122550109
96.20	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4016603637
96.20	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.951473772
96.21	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1325201894
96.21	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.832642523
96.21	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2428283637
96.21	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763610875
96.21	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403130007
96.22	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1900492388
96.22	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.3297364522
96.22	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342534540
96.22	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986071979
96.22	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2510681212
96.23	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3908707807
96.23	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3840795739
96.23	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3940636609
96.23	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.318426814
96.23	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1311973169
96.24	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2598879027
96.24	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2942869651
96.24	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959728512
96.24	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2032899271
96.24	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.2549881094
96.25	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2988474535
96.25	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3994445717
96.25	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1245206044
96.25	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.148556266
96.25	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3114128368
96.26	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1316953444
96.26	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4256438160
96.26	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115671532
96.26	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1142219749
96.26	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471272973
96.27	0.01	95.18	0.00	94.51	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1573768740
96.27	0.01	95.18	0.00	94.52	0.01	95.57	0.00			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.4059520338
96.27	0.01	95.18	0.00	94.53	0.01	95.57	0.00			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all.3667722403
96.27	0.01	95.19	0.01	94.53	0.00	95.57	0.00			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1490957576
96.27	0.01	95.20	0.01	94.53	0.00	95.58	0.01			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/13.chip_sw_all_escalation_resets.903063650
96.27	0.01	95.20	0.00	94.53	0.00	95.59	0.01			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4209131166
96.28	0.01	95.20	0.00	94.53	0.00	95.59	0.01			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4155570158
96.28	0.01	95.20	0.00	94.53	0.00	95.60	0.01			95.35	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_kmac_idle.3442901681
96.28	0.01	95.20	0.00	94.53	0.00	95.60	0.00			95.36	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3828060794
96.28	0.01	95.20	0.00	94.53	0.00	95.60	0.00			95.37	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.2202953954
96.28	0.01	95.20	0.00	94.54	0.01	95.60	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.4082172981
96.28	0.01	95.20	0.00	94.55	0.01	95.60	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3158887043
96.28	0.01	95.20	0.00	94.55	0.01	95.60	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1873925836
96.28	0.01	95.20	0.01	94.55	0.00	95.60	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1617463188
96.29	0.01	95.21	0.01	94.55	0.00	95.60	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4233323367
96.29	0.01	95.21	0.00	94.55	0.00	95.61	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.955002418
96.29	0.01	95.21	0.00	94.55	0.00	95.62	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3694047488
96.29	0.01	95.21	0.00	94.55	0.00	95.62	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3502909198
96.29	0.01	95.21	0.00	94.55	0.00	95.63	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1770779443
96.29	0.01	95.21	0.00	94.55	0.00	95.63	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.267338544
96.29	0.01	95.21	0.00	94.55	0.00	95.64	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.701230640
96.29	0.01	95.21	0.00	94.56	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3687780925
96.29	0.01	95.21	0.00	94.56	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3516523018
96.29	0.01	95.21	0.00	94.56	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2683550717
96.29	0.01	95.21	0.00	94.57	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.4057509211
96.29	0.01	95.21	0.00	94.57	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2032269529
96.29	0.01	95.21	0.00	94.57	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2572127340
96.30	0.01	95.21	0.00	94.58	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1281223567
96.30	0.01	95.21	0.00	94.58	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2096591510
96.30	0.01	95.21	0.00	94.59	0.01	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4202310752
96.30	0.01	95.21	0.01	94.59	0.00	95.64	0.00			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.840182855
96.30	0.01	95.21	0.00	94.59	0.00	95.64	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.4181897239
96.30	0.01	95.21	0.00	94.59	0.00	95.64	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.592261336
96.30	0.01	95.21	0.00	94.59	0.00	95.65	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2800433000
96.30	0.01	95.21	0.00	94.59	0.00	95.65	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3014811876
96.30	0.01	95.21	0.00	94.59	0.00	95.65	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.389070176
96.30	0.01	95.21	0.00	94.59	0.00	95.65	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.518476304
96.30	0.01	95.21	0.00	94.59	0.00	95.66	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1700784838
96.30	0.01	95.21	0.00	94.59	0.00	95.66	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3640301255
96.30	0.01	95.21	0.00	94.59	0.00	95.66	0.01			95.37	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2668475755

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.904518200
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.250472881
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3754574114
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2012376547
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1610480170
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3879690931
/workspace/coverage/cover_reg_top/0.chip_tl_errors.819369713
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1197930623
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.536132933
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2306043230
/workspace/coverage/cover_reg_top/0.xbar_error_random.4243137544
/workspace/coverage/cover_reg_top/0.xbar_random.540264235
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1391809345
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2790809760
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1400906524
/workspace/coverage/cover_reg_top/0.xbar_same_source.3163436057
/workspace/coverage/cover_reg_top/0.xbar_smoke.3958546068
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1254051086
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.533518914
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3565237140
/workspace/coverage/cover_reg_top/0.xbar_stress_all.315391434
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1051516326
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3297895870
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2898433811
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1428018091
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3659889855
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3166985973
/workspace/coverage/cover_reg_top/1.chip_csr_rw.212830260
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1250758878
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1336707361
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1933015902
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2081354049
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3217759799
/workspace/coverage/cover_reg_top/1.xbar_error_random.3330746854
/workspace/coverage/cover_reg_top/1.xbar_random.1298934633
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2443752880
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.259970592
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1577224295
/workspace/coverage/cover_reg_top/1.xbar_same_source.409412580
/workspace/coverage/cover_reg_top/1.xbar_smoke.2748876735
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3239143841
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3370981403
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1604595663
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2097684997
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.102521686
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.319148201
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1355553135
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3523786586
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3569191886
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3049622467
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4258406654
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3562016748
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.447243822
/workspace/coverage/cover_reg_top/10.xbar_error_random.226860934
/workspace/coverage/cover_reg_top/10.xbar_random.943729775
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1454422856
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2573639044
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3577633649
/workspace/coverage/cover_reg_top/10.xbar_same_source.2135014870
/workspace/coverage/cover_reg_top/10.xbar_smoke.1366652997
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3075256058
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3122592866
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.689657827
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3484005982
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.794779835
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1786248079
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1065836884
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4003276521
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1538444537
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2868284946
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3460813531
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1644965516
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.55761317
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2111780343
/workspace/coverage/cover_reg_top/11.xbar_error_random.862124289
/workspace/coverage/cover_reg_top/11.xbar_random.1415367829
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3387417366
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1179860047
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2501425910
/workspace/coverage/cover_reg_top/11.xbar_same_source.1001841178
/workspace/coverage/cover_reg_top/11.xbar_smoke.1388730084
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3068550033
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3221103138
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3782628332
/workspace/coverage/cover_reg_top/11.xbar_stress_all.900872406
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3050156180
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2796430476
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.513973914
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1138857140
/workspace/coverage/cover_reg_top/12.chip_csr_rw.16664826
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2521357316
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3932322301
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1745478850
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.418489653
/workspace/coverage/cover_reg_top/12.xbar_error_random.138894852
/workspace/coverage/cover_reg_top/12.xbar_random.3888175498
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2971491536
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2254077972
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.473553106
/workspace/coverage/cover_reg_top/12.xbar_same_source.1739083831
/workspace/coverage/cover_reg_top/12.xbar_smoke.2971008146
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.461190315
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2413007456
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.341496293
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1624108391
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3029770700
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1394102833
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4010091128
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.63741491
/workspace/coverage/cover_reg_top/13.chip_csr_rw.36571741
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3636116633
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2188079885
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2908061172
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2263288044
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3478253632
/workspace/coverage/cover_reg_top/13.xbar_error_random.2499321750
/workspace/coverage/cover_reg_top/13.xbar_random.4238314581
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1653206007
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.574423824
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4025021433
/workspace/coverage/cover_reg_top/13.xbar_same_source.3739772246
/workspace/coverage/cover_reg_top/13.xbar_smoke.54897011
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3798497340
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2506713945
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2429599926
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2897708349
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3682931747
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1705832142
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.574150358
/workspace/coverage/cover_reg_top/14.chip_csr_rw.429291353
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.5539347
/workspace/coverage/cover_reg_top/14.chip_tl_errors.835899518
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/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383994946
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3066483991
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2684947482
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2450166602
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072009371
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3071155127
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1918973625
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203829523
/workspace/coverage/default/60.chip_sw_all_escalation_resets.136761003
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282403550
/workspace/coverage/default/61.chip_sw_all_escalation_resets.240879877
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3145335539
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1715907703
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3756362344
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1582854375
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2609435781
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.288569700
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2927766801
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111139190
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1085877011
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920763955
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.714214473
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1764478847
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520901160
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4051432351
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.419476118
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.775727292
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4226080345
/workspace/coverage/default/70.chip_sw_all_escalation_resets.353487850
/workspace/coverage/default/71.chip_sw_all_escalation_resets.230485352
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761993751
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3735818876
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2580473168
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.889181585
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2456693839
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182818333
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2284660517
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336080624
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229814878
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1507272844
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4010851674
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2383363709
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1800008914
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1433678239
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3538755609
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1740460079
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3008064220
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2737407812
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3095967253
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.270945817
/workspace/coverage/default/84.chip_sw_all_escalation_resets.825371309
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883037245
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3084654407
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2680520949
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3237335446
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4147102211
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872915775
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3706031888
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173758072
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1351086106
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359186640
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3616739791
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1386872947
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3727743300
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3449407929
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1955351361
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2200239760
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2172979734
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3710168718
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1137116839
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4200856768
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1363038112
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2127691354
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1632213446
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3681435642
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2650409417
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4097945322
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.969800286
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2746471036
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3991334263

---

Total test records in report: 2792

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1319151919			Apr 28 04:13:51 PM PDT 24	Apr 28 04:17:23 PM PDT 24	2557787660 ps
T2	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1991223932			Apr 28 03:57:01 PM PDT 24	Apr 28 04:07:42 PM PDT 24	4234410216 ps
T3	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.862191672			Apr 28 04:11:25 PM PDT 24	Apr 28 04:32:33 PM PDT 24	7582624656 ps
T60	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1297694238			Apr 28 03:58:47 PM PDT 24	Apr 28 04:04:24 PM PDT 24	2872852196 ps
T89	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4220971734			Apr 28 03:57:09 PM PDT 24	Apr 28 04:09:16 PM PDT 24	4478718232 ps
T64	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.69210117			Apr 28 03:59:21 PM PDT 24	Apr 28 07:34:25 PM PDT 24	254425271646 ps
T30	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.171579318			Apr 28 04:06:24 PM PDT 24	Apr 28 04:27:01 PM PDT 24	7503649924 ps
T90	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1803716542			Apr 28 03:56:53 PM PDT 24	Apr 28 04:05:52 PM PDT 24	4654913718 ps
T31	/workspace/coverage/default/93.chip_sw_all_escalation_resets.4199156873			Apr 28 04:23:30 PM PDT 24	Apr 28 04:33:41 PM PDT 24	4781554100 ps
T65	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.805619528			Apr 28 04:14:30 PM PDT 24	Apr 28 04:21:56 PM PDT 24	3880892922 ps
T4	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.587903006			Apr 28 04:08:26 PM PDT 24	Apr 28 04:11:10 PM PDT 24	2264681167 ps
T32	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1535021433			Apr 28 04:21:22 PM PDT 24	Apr 28 04:32:03 PM PDT 24	5273650296 ps
T126	/workspace/coverage/default/0.chip_sw_edn_boot_mode.389070176			Apr 28 03:52:28 PM PDT 24	Apr 28 04:02:22 PM PDT 24	2981073550 ps
T181	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4233323367			Apr 28 03:55:05 PM PDT 24	Apr 28 04:07:49 PM PDT 24	4743117760 ps
T46	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.980230837			Apr 28 03:51:48 PM PDT 24	Apr 28 03:56:23 PM PDT 24	2731810883 ps
T148	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2878801971			Apr 28 03:59:50 PM PDT 24	Apr 28 04:06:31 PM PDT 24	3927993772 ps
T68	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3263722508			Apr 28 04:14:23 PM PDT 24	Apr 28 04:23:44 PM PDT 24	4947819004 ps
T149	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1443477511			Apr 28 04:07:03 PM PDT 24	Apr 28 04:12:22 PM PDT 24	3229933538 ps
T179	/workspace/coverage/default/65.chip_sw_all_escalation_resets.2609435781			Apr 28 04:21:22 PM PDT 24	Apr 28 04:30:00 PM PDT 24	5680898420 ps
T180	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1910720397			Apr 28 04:20:14 PM PDT 24	Apr 28 04:32:06 PM PDT 24	6216711910 ps
T281	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426650083			Apr 28 04:20:30 PM PDT 24	Apr 28 04:28:49 PM PDT 24	3342038220 ps
T125	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3856306233			Apr 28 03:56:07 PM PDT 24	Apr 28 04:26:06 PM PDT 24	8302025150 ps
T382	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2285886953			Apr 28 04:04:49 PM PDT 24	Apr 28 04:10:25 PM PDT 24	3243464248 ps
T230	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230180230			Apr 28 04:21:38 PM PDT 24	Apr 28 04:29:05 PM PDT 24	3331507708 ps
T271	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1583249002			Apr 28 04:11:32 PM PDT 24	Apr 28 04:15:52 PM PDT 24	3412409112 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_stream.2342284082			Apr 28 03:54:42 PM PDT 24	Apr 28 05:13:37 PM PDT 24	18614080152 ps
T5	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1000816229			Apr 28 03:51:30 PM PDT 24	Apr 28 03:57:14 PM PDT 24	4491932812 ps
T166	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3113285744			Apr 28 03:53:04 PM PDT 24	Apr 28 04:02:34 PM PDT 24	4748772606 ps
T121	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3013723440			Apr 28 03:56:31 PM PDT 24	Apr 28 04:05:39 PM PDT 24	4400908356 ps
T44	/workspace/coverage/default/0.chip_tap_straps_rma.2375599304			Apr 28 03:54:01 PM PDT 24	Apr 28 03:59:37 PM PDT 24	3764248511 ps
T182	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1207639434			Apr 28 04:15:45 PM PDT 24	Apr 28 04:26:21 PM PDT 24	4191358404 ps
T116	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3892017435			Apr 28 03:54:04 PM PDT 24	Apr 28 04:01:42 PM PDT 24	4148707865 ps
T111	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3481780717			Apr 28 03:58:07 PM PDT 24	Apr 28 04:06:22 PM PDT 24	18117306136 ps
T210	/workspace/coverage/default/2.rom_keymgr_functest.3454167490			Apr 28 04:16:00 PM PDT 24	Apr 28 04:25:48 PM PDT 24	4237530516 ps
T245	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3533684501			Apr 28 04:19:46 PM PDT 24	Apr 28 04:27:11 PM PDT 24	3255630568 ps
T164	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2363557553			Apr 28 03:51:40 PM PDT 24	Apr 28 04:14:48 PM PDT 24	7994186080 ps
T246	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3114128368			Apr 28 04:22:08 PM PDT 24	Apr 28 04:28:35 PM PDT 24	4057313700 ps
T688	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1776969174			Apr 28 04:08:44 PM PDT 24	Apr 28 04:14:00 PM PDT 24	3233768162 ps
T196	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4048692548			Apr 28 04:06:44 PM PDT 24	Apr 28 04:11:08 PM PDT 24	2641742480 ps
T168	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2609076653			Apr 28 04:10:44 PM PDT 24	Apr 28 04:19:19 PM PDT 24	7348222568 ps
T153	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2662192664			Apr 28 04:09:26 PM PDT 24	Apr 28 07:23:00 PM PDT 24	254558902554 ps
T45	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1554886133			Apr 28 04:12:55 PM PDT 24	Apr 28 04:22:10 PM PDT 24	6344430495 ps
T659	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.651046135			Apr 28 03:58:52 PM PDT 24	Apr 28 04:12:23 PM PDT 24	5194054708 ps
T202	/workspace/coverage/default/6.chip_sw_all_escalation_resets.2549881094			Apr 28 04:14:38 PM PDT 24	Apr 28 04:28:21 PM PDT 24	5510804404 ps
T117	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.796454400			Apr 28 04:03:04 PM PDT 24	Apr 28 04:12:01 PM PDT 24	5569980333 ps
T265	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.453038974			Apr 28 03:50:35 PM PDT 24	Apr 28 04:01:17 PM PDT 24	4551715970 ps
T266	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1873925836			Apr 28 03:52:47 PM PDT 24	Apr 28 04:02:40 PM PDT 24	3924029136 ps
T267	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3796103469			Apr 28 03:53:41 PM PDT 24	Apr 28 04:13:47 PM PDT 24	7180961107 ps
T203	/workspace/coverage/default/38.chip_sw_all_escalation_resets.112180451			Apr 28 04:17:34 PM PDT 24	Apr 28 04:27:39 PM PDT 24	5669328116 ps
T268	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4150487716			Apr 28 04:16:48 PM PDT 24	Apr 28 04:28:45 PM PDT 24	5903132720 ps
T225	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1597602628			Apr 28 04:14:05 PM PDT 24	Apr 28 04:29:03 PM PDT 24	5836351432 ps
T253	/workspace/coverage/default/24.chip_sw_all_escalation_resets.956300590			Apr 28 04:16:06 PM PDT 24	Apr 28 04:28:19 PM PDT 24	6010369052 ps
T254	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.489199969			Apr 28 04:02:34 PM PDT 24	Apr 28 04:06:53 PM PDT 24	3543208747 ps
T6	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4155570158			Apr 28 03:53:46 PM PDT 24	Apr 28 04:03:41 PM PDT 24	6990798399 ps
T255	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.826241779			Apr 28 04:02:29 PM PDT 24	Apr 28 04:12:48 PM PDT 24	4125648792 ps
T256	/workspace/coverage/default/2.chip_sw_aes_idle.503287603			Apr 28 04:10:38 PM PDT 24	Apr 28 04:15:09 PM PDT 24	3035321550 ps
T161	/workspace/coverage/default/2.chip_sival_flash_info_access.3203577981			Apr 28 04:05:51 PM PDT 24	Apr 28 04:12:14 PM PDT 24	2914531574 ps
T188	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3925699845			Apr 28 03:51:40 PM PDT 24	Apr 28 03:56:27 PM PDT 24	3342955005 ps
T257	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3092433414			Apr 28 04:08:59 PM PDT 24	Apr 28 04:15:23 PM PDT 24	6273999202 ps
T226	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1967504962			Apr 28 04:16:51 PM PDT 24	Apr 28 04:26:14 PM PDT 24	5673330108 ps
T189	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3642310315			Apr 28 04:05:32 PM PDT 24	Apr 28 04:15:29 PM PDT 24	4020189180 ps
T277	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4210059880			Apr 28 04:13:37 PM PDT 24	Apr 28 04:37:01 PM PDT 24	6566837354 ps
T278	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.701230640			Apr 28 03:52:52 PM PDT 24	Apr 28 03:58:44 PM PDT 24	4537635646 ps
T156	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1867035924			Apr 28 04:18:45 PM PDT 24	Apr 28 04:28:10 PM PDT 24	4143874368 ps
T204	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2637723257			Apr 28 03:53:09 PM PDT 24	Apr 28 04:00:08 PM PDT 24	3952240922 ps
T205	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2737407812			Apr 28 04:21:49 PM PDT 24	Apr 28 04:35:12 PM PDT 24	5527870840 ps
T280	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1787422462			Apr 28 04:22:06 PM PDT 24	Apr 28 04:32:43 PM PDT 24	4781576428 ps
T283	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872915775			Apr 28 04:22:08 PM PDT 24	Apr 28 04:30:06 PM PDT 24	3415679000 ps
T284	/workspace/coverage/default/1.chip_sw_example_flash.3685813776			Apr 28 03:56:20 PM PDT 24	Apr 28 04:00:16 PM PDT 24	2896862820 ps
T285	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2598879027			Apr 28 04:19:02 PM PDT 24	Apr 28 04:25:54 PM PDT 24	4167225050 ps
T13	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.24763256			Apr 28 04:05:46 PM PDT 24	Apr 28 07:50:02 PM PDT 24	76494175695 ps
T173	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3779080471			Apr 28 03:59:03 PM PDT 24	Apr 28 04:06:25 PM PDT 24	3411845186 ps
T112	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2830797358			Apr 28 04:11:44 PM PDT 24	Apr 28 04:21:12 PM PDT 24	18441954608 ps
T183	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4171948958			Apr 28 03:57:43 PM PDT 24	Apr 28 04:06:54 PM PDT 24	4347684416 ps
T33	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2715463177			Apr 28 03:52:16 PM PDT 24	Apr 28 03:58:06 PM PDT 24	3244946680 ps
T176	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.110106541			Apr 28 03:51:55 PM PDT 24	Apr 28 04:00:23 PM PDT 24	4028394388 ps
T849	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2468810814			Apr 28 03:56:10 PM PDT 24	Apr 28 04:05:34 PM PDT 24	5004449378 ps
T184	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1433678239			Apr 28 04:21:38 PM PDT 24	Apr 28 04:30:13 PM PDT 24	3263772626 ps
T850	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1242551667			Apr 28 03:53:41 PM PDT 24	Apr 28 03:57:49 PM PDT 24	3193378850 ps
T314	/workspace/coverage/default/1.chip_sw_hmac_enc.420095400			Apr 28 03:58:51 PM PDT 24	Apr 28 04:04:19 PM PDT 24	3005082944 ps
T177	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1454643324			Apr 28 04:10:33 PM PDT 24	Apr 28 04:18:12 PM PDT 24	5257369352 ps
T206	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.267338544			Apr 28 03:53:50 PM PDT 24	Apr 28 04:01:29 PM PDT 24	4079982146 ps
T643	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3222246237			Apr 28 04:20:47 PM PDT 24	Apr 28 04:29:01 PM PDT 24	3370867224 ps
T851	/workspace/coverage/default/2.chip_sw_aes_enc.3918260064			Apr 28 04:08:46 PM PDT 24	Apr 28 04:13:13 PM PDT 24	2801082952 ps
T372	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.651239058			Apr 28 04:05:23 PM PDT 24	Apr 28 04:10:01 PM PDT 24	2495360400 ps
T707	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1955351361			Apr 28 04:22:19 PM PDT 24	Apr 28 04:32:08 PM PDT 24	4390564966 ps
T207	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3784278719			Apr 28 04:00:45 PM PDT 24	Apr 28 04:07:54 PM PDT 24	4428159824 ps
T118	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1595796074			Apr 28 03:55:56 PM PDT 24	Apr 28 04:04:06 PM PDT 24	5130999247 ps
T14	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1570838281			Apr 28 04:05:42 PM PDT 24	Apr 28 04:17:30 PM PDT 24	4617044812 ps
T169	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.503465187			Apr 28 03:55:01 PM PDT 24	Apr 28 04:00:15 PM PDT 24	2733097950 ps
T197	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4226080345			Apr 28 04:21:23 PM PDT 24	Apr 28 04:28:53 PM PDT 24	4369820600 ps
T228	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1239365340			Apr 28 04:01:55 PM PDT 24	Apr 28 04:10:42 PM PDT 24	4510079508 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3795092975			Apr 28 03:58:31 PM PDT 24	Apr 28 08:09:46 PM PDT 24	79109334368 ps
T72	/workspace/coverage/default/0.chip_tap_straps_dev.2545065420			Apr 28 03:55:14 PM PDT 24	Apr 28 04:14:50 PM PDT 24	12571282747 ps
T275	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173758072			Apr 28 04:23:48 PM PDT 24	Apr 28 04:32:35 PM PDT 24	3823524494 ps
T66	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1082304604			Apr 28 03:51:49 PM PDT 24	Apr 28 07:06:32 PM PDT 24	59378922550 ps
T141	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.670954501			Apr 28 04:05:00 PM PDT 24	Apr 28 07:21:21 PM PDT 24	64287771204 ps
T82	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1481601413			Apr 28 03:51:36 PM PDT 24	Apr 28 04:10:47 PM PDT 24	10683714250 ps
T178	/workspace/coverage/default/1.chip_tap_straps_dev.3654737339			Apr 28 04:02:20 PM PDT 24	Apr 28 04:05:23 PM PDT 24	2476122489 ps
T675	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2684947482			Apr 28 04:20:17 PM PDT 24	Apr 28 04:27:15 PM PDT 24	3745139916 ps
T122	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3911529439			Apr 28 03:52:32 PM PDT 24	Apr 28 04:15:51 PM PDT 24	8394943863 ps
T15	/workspace/coverage/default/0.chip_sw_gpio_smoketest.3118943298			Apr 28 03:57:30 PM PDT 24	Apr 28 04:01:02 PM PDT 24	3300876400 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.700326140			Apr 28 03:52:21 PM PDT 24	Apr 28 04:01:26 PM PDT 24	3222983928 ps
T852	/workspace/coverage/default/1.chip_sw_example_concurrency.496552542			Apr 28 03:55:59 PM PDT 24	Apr 28 04:00:36 PM PDT 24	2445671300 ps
T853	/workspace/coverage/default/0.chip_sw_aes_smoketest.3200464394			Apr 28 03:57:16 PM PDT 24	Apr 28 04:02:56 PM PDT 24	2803315900 ps
T38	/workspace/coverage/default/1.chip_sw_spi_device_tpm.2506722323			Apr 28 03:58:10 PM PDT 24	Apr 28 04:05:53 PM PDT 24	3473772421 ps
T673	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.148556266			Apr 28 04:20:38 PM PDT 24	Apr 28 04:28:32 PM PDT 24	3465726268 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1315465907			Apr 28 03:53:41 PM PDT 24	Apr 28 04:15:26 PM PDT 24	16262962602 ps
T103	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342534540			Apr 28 04:20:13 PM PDT 24	Apr 28 04:28:02 PM PDT 24	4012089502 ps
T104	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1035530008			Apr 28 04:10:04 PM PDT 24	Apr 28 04:22:39 PM PDT 24	4543677800 ps
T105	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2032899271			Apr 28 04:21:03 PM PDT 24	Apr 28 04:34:07 PM PDT 24	5912337798 ps
T106	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2736491860			Apr 28 03:53:17 PM PDT 24	Apr 28 04:31:28 PM PDT 24	16879831471 ps
T107	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.270945817			Apr 28 04:21:47 PM PDT 24	Apr 28 04:28:10 PM PDT 24	3838082450 ps
T108	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4135995539			Apr 28 04:06:29 PM PDT 24	Apr 28 04:24:19 PM PDT 24	5914395776 ps
T109	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3282829833			Apr 28 04:19:21 PM PDT 24	Apr 28 04:31:52 PM PDT 24	6198742740 ps
T110	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1139377043			Apr 28 04:09:08 PM PDT 24	Apr 28 05:09:46 PM PDT 24	16732166524 ps
T67	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2169487512			Apr 28 04:05:35 PM PDT 24	Apr 28 05:37:22 PM PDT 24	43094513422 ps
T854	/workspace/coverage/default/0.chip_sw_aes_entropy.1389412450			Apr 28 03:53:53 PM PDT 24	Apr 28 03:59:28 PM PDT 24	2779076538 ps
T242	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2383363709			Apr 28 04:14:13 PM PDT 24	Apr 28 04:24:19 PM PDT 24	4919355546 ps
T383	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4108229121			Apr 28 04:10:54 PM PDT 24	Apr 28 04:17:39 PM PDT 24	2816003168 ps
T855	/workspace/coverage/default/1.chip_sw_kmac_idle.3442901681			Apr 28 04:00:11 PM PDT 24	Apr 28 04:03:39 PM PDT 24	2810913480 ps
T279	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2988474535			Apr 28 04:20:17 PM PDT 24	Apr 28 04:30:42 PM PDT 24	3619751940 ps
T190	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3987155972			Apr 28 04:08:16 PM PDT 24	Apr 28 04:25:25 PM PDT 24	5711263136 ps
T127	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2050654083			Apr 28 04:00:10 PM PDT 24	Apr 28 05:00:39 PM PDT 24	14061160796 ps
T138	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4209131166			Apr 28 03:52:17 PM PDT 24	Apr 28 04:00:44 PM PDT 24	8741924592 ps
T856	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.431704048			Apr 28 04:08:14 PM PDT 24	Apr 28 04:26:10 PM PDT 24	5808601886 ps
T194	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.741827569			Apr 28 04:22:38 PM PDT 24	Apr 28 04:34:57 PM PDT 24	4594510200 ps
T291	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2549967866			Apr 28 04:13:57 PM PDT 24	Apr 28 04:37:09 PM PDT 24	7223683210 ps
T857	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3997313243			Apr 28 04:03:28 PM PDT 24	Apr 28 04:19:05 PM PDT 24	7334943849 ps
T858	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4170676466			Apr 28 03:56:22 PM PDT 24	Apr 28 04:00:06 PM PDT 24	3345553624 ps
T712	/workspace/coverage/default/86.chip_sw_all_escalation_resets.2680520949			Apr 28 04:22:18 PM PDT 24	Apr 28 04:31:19 PM PDT 24	5366070120 ps
T674	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2755700252			Apr 28 03:53:03 PM PDT 24	Apr 28 04:02:36 PM PDT 24	4810233676 ps
T859	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2604482932			Apr 28 03:55:10 PM PDT 24	Apr 28 04:02:34 PM PDT 24	5812683580 ps
T47	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.374916861			Apr 28 04:05:38 PM PDT 24	Apr 28 04:11:38 PM PDT 24	5272511680 ps
T351	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441088846			Apr 28 03:58:10 PM PDT 24	Apr 28 04:03:38 PM PDT 24	3921572250 ps
T191	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1568462927			Apr 28 04:08:12 PM PDT 24	Apr 28 04:17:36 PM PDT 24	3610906600 ps
T165	/workspace/coverage/default/2.chip_sw_flash_init.270634435			Apr 28 04:05:54 PM PDT 24	Apr 28 04:47:44 PM PDT 24	25952136397 ps
T162	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1488821102			Apr 28 03:59:00 PM PDT 24	Apr 28 04:11:44 PM PDT 24	7503265784 ps
T208	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.4255560642			Apr 28 04:00:42 PM PDT 24	Apr 28 04:10:29 PM PDT 24	3880191948 ps
T123	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3702884094			Apr 28 04:11:10 PM PDT 24	Apr 28 04:21:17 PM PDT 24	3252482272 ps
T211	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1700784838			Apr 28 03:58:54 PM PDT 24	Apr 28 05:06:06 PM PDT 24	13360717416 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.280633069			Apr 28 04:11:30 PM PDT 24	Apr 28 04:21:54 PM PDT 24	5015787300 ps
T174	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2259251106			Apr 28 03:50:21 PM PDT 24	Apr 28 05:19:26 PM PDT 24	43709821560 ps
T860	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1363606108			Apr 28 03:55:20 PM PDT 24	Apr 28 03:59:10 PM PDT 24	2462026600 ps
T861	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3096283983			Apr 28 03:53:53 PM PDT 24	Apr 28 04:00:21 PM PDT 24	3064242580 ps
T862	/workspace/coverage/default/0.chip_sw_example_rom.1330487950			Apr 28 03:51:34 PM PDT 24	Apr 28 03:54:03 PM PDT 24	2941507428 ps
T163	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3215597754			Apr 28 04:09:20 PM PDT 24	Apr 28 04:19:34 PM PDT 24	5973451613 ps
T689	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1671669953			Apr 28 03:56:30 PM PDT 24	Apr 28 04:02:05 PM PDT 24	3392757020 ps
T676	/workspace/coverage/default/34.chip_sw_all_escalation_resets.668431469			Apr 28 04:17:27 PM PDT 24	Apr 28 04:26:58 PM PDT 24	5188512684 ps
T863	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1398171339			Apr 28 03:51:44 PM PDT 24	Apr 28 04:01:44 PM PDT 24	4499437696 ps
T864	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1832831945			Apr 28 03:52:52 PM PDT 24	Apr 28 03:57:31 PM PDT 24	3471343000 ps
T865	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2319709264			Apr 28 04:09:11 PM PDT 24	Apr 28 04:16:04 PM PDT 24	3452787273 ps
T83	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3504621810			Apr 28 04:14:58 PM PDT 24	Apr 28 04:24:41 PM PDT 24	5481651130 ps
T93	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.931144559			Apr 28 04:19:30 PM PDT 24	Apr 28 04:31:58 PM PDT 24	6850572874 ps
T94	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2769943028			Apr 28 03:55:55 PM PDT 24	Apr 28 04:05:13 PM PDT 24	4159071876 ps
T95	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671422216			Apr 28 04:14:16 PM PDT 24	Apr 28 04:21:20 PM PDT 24	4211832734 ps
T96	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.849320968			Apr 28 04:06:52 PM PDT 24	Apr 28 04:10:46 PM PDT 24	2751251650 ps
T88	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2249171315			Apr 28 03:51:22 PM PDT 24	Apr 28 03:54:47 PM PDT 24	2778757820 ps
T97	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.594269277			Apr 28 03:55:40 PM PDT 24	Apr 28 04:01:20 PM PDT 24	3063896451 ps
T98	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1907101690			Apr 28 04:05:19 PM PDT 24	Apr 28 04:15:42 PM PDT 24	3580702296 ps
T79	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1284096107			Apr 28 03:56:04 PM PDT 24	Apr 28 04:03:34 PM PDT 24	4834578992 ps
T99	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.283109963			Apr 28 03:53:40 PM PDT 24	Apr 28 03:57:53 PM PDT 24	2870436004 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2081418654			Apr 28 03:52:07 PM PDT 24	Apr 28 04:06:33 PM PDT 24	7231759149 ps
T48	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.863709831			Apr 28 03:54:40 PM PDT 24	Apr 28 04:29:04 PM PDT 24	21914388792 ps
T192	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1166233			Apr 28 03:51:51 PM PDT 24	Apr 28 04:21:14 PM PDT 24	8346256789 ps
T782	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788099070			Apr 28 04:19:12 PM PDT 24	Apr 28 04:26:21 PM PDT 24	3545370106 ps
T354	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2634790020			Apr 28 03:52:18 PM PDT 24	Apr 28 04:20:45 PM PDT 24	9567069934 ps
T708	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942163424			Apr 28 04:14:38 PM PDT 24	Apr 28 04:22:02 PM PDT 24	4281640676 ps
T646	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1582854375			Apr 28 04:20:08 PM PDT 24	Apr 28 04:26:39 PM PDT 24	3263778744 ps
T355	/workspace/coverage/default/70.chip_sw_all_escalation_resets.353487850			Apr 28 04:21:10 PM PDT 24	Apr 28 04:33:25 PM PDT 24	5441574960 ps
T709	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3319594994			Apr 28 03:58:13 PM PDT 24	Apr 28 04:09:28 PM PDT 24	4410566856 ps
T58	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3544114580			Apr 28 03:54:14 PM PDT 24	Apr 28 04:02:36 PM PDT 24	7609432700 ps
T866	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.833851436			Apr 28 03:52:49 PM PDT 24	Apr 28 04:02:56 PM PDT 24	3621481196 ps
T867	/workspace/coverage/default/1.chip_sw_example_manufacturer.2556334335			Apr 28 03:56:50 PM PDT 24	Apr 28 04:01:57 PM PDT 24	3375023520 ps
T315	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1919712128			Apr 28 03:53:54 PM PDT 24	Apr 28 03:58:07 PM PDT 24	3008797439 ps
T84	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3269196951			Apr 28 04:13:43 PM PDT 24	Apr 28 04:26:33 PM PDT 24	6027966600 ps
T868	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1078731291			Apr 28 04:09:00 PM PDT 24	Apr 28 04:16:59 PM PDT 24	5245770562 ps
T61	/workspace/coverage/default/0.chip_sw_alert_test.464028070			Apr 28 03:53:58 PM PDT 24	Apr 28 03:58:41 PM PDT 24	2563195990 ps
T258	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.282287912			Apr 28 04:11:57 PM PDT 24	Apr 28 04:20:38 PM PDT 24	3381296156 ps
T869	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1536779262			Apr 28 04:13:14 PM PDT 24	Apr 28 04:17:28 PM PDT 24	3378919197 ps
T730	/workspace/coverage/default/46.chip_sw_all_escalation_resets.932503827			Apr 28 04:18:15 PM PDT 24	Apr 28 04:28:24 PM PDT 24	4826163360 ps
T870	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2401676844			Apr 28 03:55:30 PM PDT 24	Apr 28 04:03:11 PM PDT 24	4249404612 ps
T157	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3118800072			Apr 28 03:51:31 PM PDT 24	Apr 28 04:03:19 PM PDT 24	4916377612 ps
T871	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3369484749			Apr 28 03:58:10 PM PDT 24	Apr 28 04:08:56 PM PDT 24	4473750080 ps
T642	/workspace/coverage/default/0.chip_sw_aes_masking_off.51506991			Apr 28 03:52:58 PM PDT 24	Apr 28 03:58:31 PM PDT 24	2289099579 ps
T185	/workspace/coverage/default/2.chip_sw_power_idle_load.2816873824			Apr 28 04:10:50 PM PDT 24	Apr 28 04:23:32 PM PDT 24	3573507368 ps
T229	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4128889303			Apr 28 03:54:08 PM PDT 24	Apr 28 04:14:06 PM PDT 24	10586319660 ps
T170	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2265461546			Apr 28 03:59:25 PM PDT 24	Apr 28 04:08:35 PM PDT 24	6183394502 ps
T119	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.485212504			Apr 28 03:55:20 PM PDT 24	Apr 28 04:34:16 PM PDT 24	27764352727 ps
T39	/workspace/coverage/default/0.chip_sw_spi_device_tpm.3124850140			Apr 28 03:52:24 PM PDT 24	Apr 28 03:58:28 PM PDT 24	3480789301 ps
T49	/workspace/coverage/default/2.chip_jtag_csr_rw.1922407621			Apr 28 04:03:13 PM PDT 24	Apr 28 04:31:51 PM PDT 24	12140196391 ps
T361	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4256438160			Apr 28 04:15:03 PM PDT 24	Apr 28 04:22:19 PM PDT 24	3741448596 ps
T115	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.772143924			Apr 28 03:56:49 PM PDT 24	Apr 28 04:58:56 PM PDT 24	18555417042 ps
T80	/workspace/coverage/default/1.chip_jtag_mem_access.2039768907			Apr 28 03:54:17 PM PDT 24	Apr 28 04:18:11 PM PDT 24	12763801452 ps
T356	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3815317075			Apr 28 03:59:27 PM PDT 24	Apr 28 04:17:22 PM PDT 24	5739224410 ps
T120	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4114452232			Apr 28 03:50:41 PM PDT 24	Apr 28 03:52:34 PM PDT 24	3019552920 ps
T294	/workspace/coverage/default/1.chip_sival_flash_info_access.2894033385			Apr 28 03:54:18 PM PDT 24	Apr 28 03:58:38 PM PDT 24	2522161378 ps
T357	/workspace/coverage/default/1.chip_sw_edn_auto_mode.786479827			Apr 28 03:59:10 PM PDT 24	Apr 28 04:15:45 PM PDT 24	4888574952 ps
T198	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.251127334			Apr 28 03:54:02 PM PDT 24	Apr 28 04:24:02 PM PDT 24	7452568238 ps
T310	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1238200464			Apr 28 03:52:33 PM PDT 24	Apr 28 04:02:09 PM PDT 24	3750283908 ps
T370	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1900492388			Apr 28 04:17:58 PM PDT 24	Apr 28 04:30:26 PM PDT 24	5307836552 ps
T872	/workspace/coverage/default/1.chip_sw_aes_smoketest.401716781			Apr 28 04:05:22 PM PDT 24	Apr 28 04:09:52 PM PDT 24	2704391524 ps
T214	/workspace/coverage/default/0.chip_sw_flash_init.2731040445			Apr 28 03:51:04 PM PDT 24	Apr 28 04:20:18 PM PDT 24	21249300393 ps
T193	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1932440689			Apr 28 03:54:40 PM PDT 24	Apr 28 07:21:52 PM PDT 24	63033965003 ps
T873	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2335426941			Apr 28 04:12:47 PM PDT 24	Apr 28 04:20:34 PM PDT 24	7436171276 ps
T81	/workspace/coverage/default/0.chip_jtag_mem_access.1143624642			Apr 28 03:45:16 PM PDT 24	Apr 28 04:13:37 PM PDT 24	13241803668 ps
T874	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1779956889			Apr 28 04:07:04 PM PDT 24	Apr 28 04:12:58 PM PDT 24	4186195088 ps
T368	/workspace/coverage/default/1.chip_sw_kmac_app_rom.2266901441			Apr 28 03:59:40 PM PDT 24	Apr 28 04:03:33 PM PDT 24	2676881824 ps
T113	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1102363912			Apr 28 04:03:08 PM PDT 24	Apr 28 04:34:14 PM PDT 24	14230189746 ps
T19	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3780870458			Apr 28 03:58:24 PM PDT 24	Apr 28 05:00:09 PM PDT 24	20456499855 ps
T875	/workspace/coverage/default/3.chip_sw_uart_tx_rx.4055245862			Apr 28 04:11:36 PM PDT 24	Apr 28 04:22:41 PM PDT 24	4200974740 ps
T710	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1886819595			Apr 28 04:02:00 PM PDT 24	Apr 28 04:10:41 PM PDT 24	3660944524 ps
T139	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3888544574			Apr 28 03:57:59 PM PDT 24	Apr 28 04:05:33 PM PDT 24	7225288834 ps
T876	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2608724125			Apr 28 04:02:37 PM PDT 24	Apr 28 04:14:18 PM PDT 24	4276665856 ps
T238	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1029506102			Apr 28 04:12:04 PM PDT 24	Apr 28 04:15:42 PM PDT 24	2694830352 ps
T223	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1950027249			Apr 28 03:58:54 PM PDT 24	Apr 28 04:11:39 PM PDT 24	4846551993 ps
T751	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2580473168			Apr 28 04:20:52 PM PDT 24	Apr 28 04:33:23 PM PDT 24	5960238856 ps
T877	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3260023142			Apr 28 03:56:37 PM PDT 24	Apr 28 04:04:44 PM PDT 24	3242641704 ps
T878	/workspace/coverage/default/1.chip_sw_edn_kat.620090771			Apr 28 03:59:11 PM PDT 24	Apr 28 04:09:59 PM PDT 24	3601149516 ps
T774	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.631985803			Apr 28 04:18:13 PM PDT 24	Apr 28 04:26:08 PM PDT 24	4139123920 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_config_host.4181897239			Apr 28 03:54:43 PM PDT 24	Apr 28 04:25:22 PM PDT 24	7748580854 ps
T879	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.734285975			Apr 28 03:51:11 PM PDT 24	Apr 28 04:00:22 PM PDT 24	4554909252 ps
T62	/workspace/coverage/default/1.chip_sw_alert_test.1694850962			Apr 28 03:57:55 PM PDT 24	Apr 28 04:02:05 PM PDT 24	2663322504 ps
T880	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.443939449			Apr 28 04:11:09 PM PDT 24	Apr 28 04:21:00 PM PDT 24	4536213142 ps
T760	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2250094923			Apr 28 04:16:43 PM PDT 24	Apr 28 04:28:49 PM PDT 24	4648961000 ps
T881	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1986310864			Apr 28 04:09:37 PM PDT 24	Apr 28 04:14:44 PM PDT 24	2941832936 ps
T298	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2058068716			Apr 28 03:51:59 PM PDT 24	Apr 28 04:08:01 PM PDT 24	5873436336 ps
T882	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1586720897			Apr 28 03:55:04 PM PDT 24	Apr 28 07:21:24 PM PDT 24	63470867808 ps
T711	/workspace/coverage/default/32.chip_sw_all_escalation_resets.3010649188			Apr 28 04:18:11 PM PDT 24	Apr 28 04:29:16 PM PDT 24	5986040974 ps
T883	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.575567207			Apr 28 04:08:58 PM PDT 24	Apr 28 04:20:25 PM PDT 24	5543116190 ps
T884	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1297233492			Apr 28 03:58:00 PM PDT 24	Apr 28 04:03:15 PM PDT 24	3254316642 ps
T704	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989183800			Apr 28 04:18:55 PM PDT 24	Apr 28 04:27:02 PM PDT 24	4199170738 ps
T885	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2747089741			Apr 28 04:05:58 PM PDT 24	Apr 28 04:34:27 PM PDT 24	8249474105 ps
T320	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2010168682			Apr 28 03:52:47 PM PDT 24	Apr 28 04:13:55 PM PDT 24	11983867005 ps
T886	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2165633840			Apr 28 03:58:07 PM PDT 24	Apr 28 04:07:22 PM PDT 24	4326196160 ps
T887	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1097696335			Apr 28 04:00:48 PM PDT 24	Apr 28 04:26:17 PM PDT 24	13030108686 ps
T745	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3184676273			Apr 28 04:18:16 PM PDT 24	Apr 28 04:28:55 PM PDT 24	5783940560 ps
T888	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.429492926			Apr 28 04:00:26 PM PDT 24	Apr 28 04:05:59 PM PDT 24	4010534812 ps
T323	/workspace/coverage/default/0.chip_sival_flash_info_access.2951633536			Apr 28 03:50:46 PM PDT 24	Apr 28 03:54:47 PM PDT 24	2641322320 ps
T889	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3310717392			Apr 28 03:53:44 PM PDT 24	Apr 28 04:04:28 PM PDT 24	8323226248 ps
T752	/workspace/coverage/default/85.chip_sw_all_escalation_resets.3084654407			Apr 28 04:22:49 PM PDT 24	Apr 28 04:35:54 PM PDT 24	4932007920 ps
T309	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.343698679			Apr 28 04:09:08 PM PDT 24	Apr 28 04:44:31 PM PDT 24	10595528595 ps
T890	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2962189203			Apr 28 03:54:25 PM PDT 24	Apr 28 03:58:21 PM PDT 24	3683073127 ps
T224	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1368246363			Apr 28 03:59:40 PM PDT 24	Apr 28 04:12:52 PM PDT 24	4673921048 ps
T797	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403130007			Apr 28 04:18:08 PM PDT 24	Apr 28 04:26:11 PM PDT 24	4283862600 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1970149446			Apr 28 03:53:09 PM PDT 24	Apr 28 05:04:53 PM PDT 24	20428396319 ps
T891	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.888108312			Apr 28 04:11:15 PM PDT 24	Apr 28 04:34:44 PM PDT 24	5690654490 ps
T892	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1871108887			Apr 28 04:14:40 PM PDT 24	Apr 28 04:41:46 PM PDT 24	7484569500 ps
T150	/workspace/coverage/default/0.chip_plic_all_irqs_10.3060458502			Apr 28 03:53:37 PM PDT 24	Apr 28 03:59:46 PM PDT 24	3397068856 ps
T318	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1764478847			Apr 28 04:21:13 PM PDT 24	Apr 28 04:31:45 PM PDT 24	4431983356 ps