Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	498	1			T484	2		T491	7		T366	1
all_values[1]	450	1			T234	1		T386	1		T491	2
all_values[2]	458	1			T386	1		T491	5		T492	1
all_values[3]	478	1			T386	1		T491	5		T419	1
all_values[4]	469	1			T471	3		T484	4		T491	2
all_values[5]	496	1			T484	3		T386	1		T491	2
all_values[6]	495	1			T484	1		T491	6		T402	1
all_values[7]	471	1			T831	1		T491	7		T419	1
all_values[8]	508	1			T471	1		T484	2		T831	1
all_values[9]	467	1			T484	1		T491	4		T366	1
all_values[10]	488	1			T484	1		T499	1		T491	3
all_values[11]	489	1			T499	1		T491	5		T402	1
all_values[12]	458	1			T831	1		T491	2		T366	1
all_values[13]	527	1			T484	1		T491	1		T366	1
all_values[14]	461	1			T471	1		T484	1		T386	1
all_values[15]	482	1			T484	3		T491	3		T419	2
all_values[16]	462	1			T484	2		T491	5		T419	1
all_values[17]	464	1			T386	1		T491	5		T492	1
all_values[18]	495	1			T484	4		T386	1		T491	5
all_values[19]	453	1			T234	1		T471	1		T484	1
all_values[20]	490	1			T484	1		T831	3		T386	1
all_values[21]	488	1			T471	1		T386	1		T491	3
all_values[22]	479	1			T484	1		T831	1		T491	2
all_values[23]	463	1			T471	1		T484	2		T831	1
all_values[24]	490	1			T484	1		T386	1		T491	2
all_values[25]	450	1			T484	1		T386	1		T491	4
all_values[26]	463	1			T484	1		T491	8		T366	1
all_values[27]	450	1			T484	1		T491	4		T810	1
all_values[28]	467	1			T234	1		T471	1		T484	2
all_values[29]	462	1			T471	1		T484	3		T499	1
all_values[30]	508	1			T484	2		T386	1		T491	4
all_values[31]	468	1			T484	1		T491	5		T492	1
all_values[32]	493	1			T471	1		T490	1		T491	4
all_values[33]	429	1			T484	2		T831	1		T386	2
all_values[34]	503	1			T484	3		T831	1		T386	1
all_values[35]	485	1			T234	1		T471	2		T491	8
all_values[36]	512	1			T484	1		T491	2		T492	1
all_values[37]	467	1			T831	1		T491	3		T492	1
all_values[38]	477	1			T484	1		T491	2		T366	1
all_values[39]	502	1			T471	1		T386	1		T491	7
all_values[40]	466	1			T484	1		T386	1		T491	5
all_values[41]	486	1			T484	4		T491	5		T419	2
all_values[42]	482	1			T484	1		T491	3		T492	1
all_values[43]	507	1			T234	1		T484	1		T386	1
all_values[44]	443	1			T471	1		T484	2		T491	4
all_values[45]	462	1			T484	2		T490	1		T419	2
all_values[46]	487	1			T831	1		T491	3		T419	1
all_values[47]	490	1			T484	1		T491	5		T419	4
all_values[48]	516	1			T484	1		T499	1		T491	5
all_values[49]	467	1			T484	1		T386	1		T499	1