Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3592	1			T350	2		T484	12		T487	1
all_values[1]	3559	1			T350	2		T484	19		T480	1
all_values[2]	3595	1			T350	4		T484	11		T480	6
all_values[3]	3518	1			T350	4		T484	15		T480	3
all_values[4]	3576	1			T350	5		T484	15		T487	1
all_values[5]	3497	1			T350	3		T484	17		T480	1
all_values[6]	3561	1			T484	12		T480	3		T485	1
all_values[7]	3601	1			T350	2		T484	11		T487	1
all_values[8]	3625	1			T350	1		T484	20		T487	1
all_values[9]	3502	1			T350	3		T484	17		T480	2
all_values[10]	3591	1			T350	4		T484	22		T487	1
all_values[11]	3467	1			T350	1		T484	23		T487	2
all_values[12]	3501	1			T350	3		T484	11		T480	5
all_values[13]	3454	1			T350	2		T484	13		T487	1
all_values[14]	3411	1			T350	3		T484	12		T487	1
all_values[15]	3559	1			T350	1		T484	16		T480	3
all_values[16]	3595	1			T350	3		T484	14		T480	3
all_values[17]	3510	1			T350	2		T484	12		T487	1
all_values[18]	3540	1			T350	4		T484	9		T480	7
all_values[19]	3562	1			T350	5		T484	11		T487	1
all_values[20]	3510	1			T350	2		T484	13		T480	2
all_values[21]	3578	1			T350	1		T484	16		T480	1
all_values[22]	3629	1			T350	3		T484	19		T487	1
all_values[23]	3560	1			T350	3		T484	21		T487	1
all_values[24]	3515	1			T350	3		T484	7		T487	2
all_values[25]	3558	1			T484	17		T487	1		T485	3
all_values[26]	3636	1			T350	2		T484	19		T487	3
all_values[27]	3533	1			T350	3		T484	15		T480	5
all_values[28]	3591	1			T350	3		T484	8		T487	1
all_values[29]	3597	1			T350	2		T484	15		T487	1
all_values[30]	3437	1			T350	3		T484	14		T487	2
all_values[31]	3528	1			T350	3		T484	23		T487	2
all_values[32]	3547	1			T350	6		T484	14		T487	1
all_values[33]	3506	1			T350	5		T484	9		T480	1
all_values[34]	3434	1			T350	4		T484	7		T487	1
all_values[35]	3610	1			T350	3		T484	10		T487	1
all_values[36]	3454	1			T350	2		T484	11		T487	1
all_values[37]	3589	1			T350	2		T484	13		T480	3
all_values[38]	3558	1			T350	6		T484	19		T480	4
all_values[39]	3512	1			T350	4		T484	13		T487	3
all_values[40]	3463	1			T350	2		T484	17		T487	1
all_values[41]	3533	1			T350	1		T484	10		T487	1
all_values[42]	3530	1			T350	3		T484	9		T487	1
all_values[43]	3610	1			T350	3		T484	11		T487	1
all_values[44]	3606	1			T484	8		T487	2		T480	4
all_values[45]	3625	1			T350	2		T484	6		T487	1
all_values[46]	3574	1			T350	1		T484	20		T487	1
all_values[47]	3502	1			T484	12		T487	3		T480	3
all_values[48]	3576	1			T350	3		T484	13		T480	2
all_values[49]	3473	1			T350	3		T484	12		T487	1
all_values[50]	3598	1			T350	2		T484	17		T480	2
all_values[51]	3613	1			T350	3		T484	14		T480	5
all_values[52]	3644	1			T484	11		T487	2		T480	3
all_values[53]	3691	1			T350	3		T484	14		T480	1
all_values[54]	3552	1			T350	1		T484	13		T480	2
all_values[55]	3667	1			T350	5		T484	18		T480	4
all_values[56]	3542	1			T350	3		T484	14		T487	1
all_values[57]	3644	1			T350	3		T484	15		T487	2
all_values[58]	3446	1			T484	13		T480	5		T485	2
all_values[59]	3424	1			T350	2		T484	15		T480	6
all_values[60]	3595	1			T350	6		T484	21		T487	1
all_values[61]	3475	1			T350	1		T484	17		T487	1
all_values[62]	3501	1			T484	12		T487	1		T480	2
all_values[63]	3550	1			T350	2		T484	14		T487	1