Cond split page
dashboard | hierarchy | modlist | groups | tests | asserts
Go back
 LINE       16480
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_2_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT63,T477,T142

 LINE       16481
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_3_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT63,T477,T142

 LINE       16482
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_4_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT96,T677,T63

 LINE       16483
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_5_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT63,T477,T142

 LINE       16484
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_0_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT2,T121,T182

 LINE       16485
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_1_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT13,T14,T291

 LINE       16486
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_2_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT181,T189,T38

 LINE       16487
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_3_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT60,T64,T31

 LINE       16488
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_4_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT90,T31,T65

 LINE       16489
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_5_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT265,T266,T161

 LINE       16490
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_THRESHOLD0_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT2,T60,T64

 LINE       16491
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_CC0_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT2,T60,T90

 LINE       16492
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_MSIP0_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT186,T236,T63

 LINE       16493
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_ALERT_TEST_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT2,T60,T64
1CoveredT61,T62,T63

 LINE       16496
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T60,T64

 LINE       16496
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T60,T64
10CoveredT2,T60,T64

 LINE       16500
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | (addr_hit[182] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[183] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[184] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[185] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[186] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[187] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[188] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[189] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[190] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[191] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[192] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[193] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[194] & ((|(4'b1 & (~reg_be))))) | (addr_hit[195] & ((|(4'b1 & (~reg_be))))) | (addr_hit[196] & ((|(4'b1 & (~reg_be))))) | (addr_hit[197] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T60,T64
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | 
     62  (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | 
     63  (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | 
     64  (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | 
     65  (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | 
     66  (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | 
     67  (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | 
     68  (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | 
     69  (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | 
     70  (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | 
     71  (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | 
     72  (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | 
     73  (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | 
     74  (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | 
     75  (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | 
     76  (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | 
     77  (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | 
     78  (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | 
     79  (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | 
     80  (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | 
     81  (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | 
     82  (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | 
     83  (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | 
     84  (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | 
     85  (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | 
     86  (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | 
     87  (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | 
     88  (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | 
     89  (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | 
     90  (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | 
     91  (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | 
     92  (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | 
     93  (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | 
     94  (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | 
     95  (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | 
     96  (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | 
     97  (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | 
     98  (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | 
     99  (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | 
    100  (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | 
    101  (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | 
    102  (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | 
    103  (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | 
    104  (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | 
    105  (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | 
    106  (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | 
    107  (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | 
    108  (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | 
    109  (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | 
    110  (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | 
    111  (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | 
    112  (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | 
    113  (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | 
    114  (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | 
    115  (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | 
    116  (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | 
    117  (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | 
    118  (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | 
    119  (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | 
    120  (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | 
    121  (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | 
    122  (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | 
    123  (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | 
    124  (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | 
    125  (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | 
    126  (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | 
    127  (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | 
    128  (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | 
    129  (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | 
    130  (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | 
    131  (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | 
    132  (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | 
    133  (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | 
    134  (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | 
    135  (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | 
    136  (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | 
    137  (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | 
    138  (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | 
    139  (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | 
    140  (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | 
    141  (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | 
    142  (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | 
    143  (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | 
    144  (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | 
    145  (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | 
    146  (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | 
    147  (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | 
    148  (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | 
    149  (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | 
    150  (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | 
    151  (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | 
    152  (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | 
    153  (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | 
    154  (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | 
    155  (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | 
    156  (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | 
    157  (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | 
    158  (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | 
    159  (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | 
    160  (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | 
    161  (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | 
    162  (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | 
    163  (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | 
    164  (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | 
    165  (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | 
    166  (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | 
    167  (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | 
    168  (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | 
    169  (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | 
    170  (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | 
    171  (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | 
    172  (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | 
    173  (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | 
    174  (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | 
    175  (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | 
    176  (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | 
    177  (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | 
    178  (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | 
    179  (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | 
    180  (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | 
    181  (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | 
    182  (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | 
    183  (addr_hit[182] & ((|(4'b1111 & (~reg_be))))) | 
    184  (addr_hit[183] & ((|(4'b1111 & (~reg_be))))) | 
    185  (addr_hit[184] & ((|(4'b1111 & (~reg_be))))) | 
    186  (addr_hit[185] & ((|(4'b1111 & (~reg_be))))) | 
    187  (addr_hit[186] & ((|(4'b1111 & (~reg_be))))) | 
    188  (addr_hit[187] & ((|(4'b0111 & (~reg_be))))) | 
    189  (addr_hit[188] & ((|(4'b1111 & (~reg_be))))) | 
    190  (addr_hit[189] & ((|(4'b1111 & (~reg_be))))) | 
    191  (addr_hit[190] & ((|(4'b1111 & (~reg_be))))) | 
    192  (addr_hit[191] & ((|(4'b1111 & (~reg_be))))) | 
    193  (addr_hit[192] & ((|(4'b1111 & (~reg_be))))) | 
    194  (addr_hit[193] & ((|(4'b0111 & (~reg_be))))) | 
    195  (addr_hit[194] & ((|(4'b1 & (~reg_be))))) | 
    196  (addr_hit[195] & ((|(4'b1 & (~reg_be))))) | 
    197  (addr_hit[196] & ((|(4'b1 & (~reg_be))))) | 
    198  (addr_hit[197] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT2,T60,T64
198 (addr_hit[197] & ((|(4...CoveredT477,T329,T504
197 (addr_hit[196] & ((|(4...CoveredT477,T330,T504
196 (addr_hit[195] & ((|(4...CoveredT477,T504,T511
195 (addr_hit[194] & ((|(4...CoveredT477,T329,T504
194 (addr_hit[193] & ((|(4...CoveredT477,T142,T330
193 (addr_hit[192] & ((|(4...CoveredT477,T142,T330
192 (addr_hit[191] & ((|(4...CoveredT477,T142,T330
191 (addr_hit[190] & ((|(4...CoveredT477,T142,T330
190 (addr_hit[189] & ((|(4...CoveredT477,T142,T330
189 (addr_hit[188] & ((|(4...CoveredT477,T142,T330
188 (addr_hit[187] & ((|(4...CoveredT477,T504,T511
187 (addr_hit[186] & ((|(4...CoveredT477,T504,T511
186 (addr_hit[185] & ((|(4...CoveredT477,T504,T511
185 (addr_hit[184] & ((|(4...CoveredT477,T504,T511
184 (addr_hit[183] & ((|(4...CoveredT477,T504,T511
183 (addr_hit[182] & ((|(4...CoveredT477,T504,T511
182 (addr_hit[181] & ((|(4...CoveredT477,T504,T511
181 (addr_hit[180] & ((|(4...CoveredT477,T504,T144
180 (addr_hit[179] & ((|(4...CoveredT477,T504,T511
179 (addr_hit[178] & ((|(4...CoveredT477,T329,T504
178 (addr_hit[177] & ((|(4...CoveredT477,T504,T511
177 (addr_hit[176] & ((|(4...CoveredT477,T330,T511
176 (addr_hit[175] & ((|(4...CoveredT477,T504,T144
175 (addr_hit[174] & ((|(4...CoveredT477,T330,T329
174 (addr_hit[173] & ((|(4...CoveredT477,T142,T330
173 (addr_hit[172] & ((|(4...CoveredT477,T504,T511
172 (addr_hit[171] & ((|(4...CoveredT477,T504,T360
171 (addr_hit[170] & ((|(4...CoveredT477,T504,T144
170 (addr_hit[169] & ((|(4...CoveredT477,T504,T511
169 (addr_hit[168] & ((|(4...CoveredT477,T504,T144
168 (addr_hit[167] & ((|(4...CoveredT477,T504,T144
167 (addr_hit[166] & ((|(4...CoveredT477,T142,T329
166 (addr_hit[165] & ((|(4...CoveredT477,T142,T504
165 (addr_hit[164] & ((|(4...CoveredT477,T330,T329
164 (addr_hit[163] & ((|(4...CoveredT477,T329,T504
163 (addr_hit[162] & ((|(4...CoveredT477,T329,T504
162 (addr_hit[161] & ((|(4...CoveredT477,T330,T329
161 (addr_hit[160] & ((|(4...CoveredT477,T329,T511
160 (addr_hit[159] & ((|(4...CoveredT477,T329,T504
159 (addr_hit[158] & ((|(4...CoveredT477,T330,T504
158 (addr_hit[157] & ((|(4...CoveredT477,T142,T330
157 (addr_hit[156] & ((|(4...CoveredT477,T329,T504
156 (addr_hit[155] & ((|(4...CoveredT477,T504,T360
155 (addr_hit[154] & ((|(4...CoveredT477,T329,T504
154 (addr_hit[153] & ((|(4...CoveredT477,T504,T511
153 (addr_hit[152] & ((|(4...CoveredT477,T329,T511
152 (addr_hit[151] & ((|(4...CoveredT477,T504,T511
151 (addr_hit[150] & ((|(4...CoveredT477,T330,T329
150 (addr_hit[149] & ((|(4...CoveredT477,T142,T504
149 (addr_hit[148] & ((|(4...CoveredT477,T329,T504
148 (addr_hit[147] & ((|(4...CoveredT477,T504,T144
147 (addr_hit[146] & ((|(4...CoveredT477,T504,T360
146 (addr_hit[145] & ((|(4...CoveredT477,T504,T511
145 (addr_hit[144] & ((|(4...CoveredT477,T142,T504
144 (addr_hit[143] & ((|(4...CoveredT477,T504,T144
143 (addr_hit[142] & ((|(4...CoveredT477,T142,T329
142 (addr_hit[141] & ((|(4...CoveredT477,T329,T504
141 (addr_hit[140] & ((|(4...CoveredT477,T504,T144
140 (addr_hit[139] & ((|(4...CoveredT477,T330,T504
139 (addr_hit[138] & ((|(4...CoveredT477,T330,T329
138 (addr_hit[137] & ((|(4...CoveredT477,T330,T504
137 (addr_hit[136] & ((|(4...CoveredT477,T142,T330
136 (addr_hit[135] & ((|(4...CoveredT477,T329,T504
135 (addr_hit[134] & ((|(4...CoveredT477,T330,T504
134 (addr_hit[133] & ((|(4...CoveredT477,T142,T504
133 (addr_hit[132] & ((|(4...CoveredT477,T329,T504
132 (addr_hit[131] & ((|(4...CoveredT477,T329,T504
131 (addr_hit[130] & ((|(4...CoveredT477,T329,T504
130 (addr_hit[129] & ((|(4...CoveredT477,T142,T504
129 (addr_hit[128] & ((|(4...CoveredT477,T142,T330
128 (addr_hit[127] & ((|(4...CoveredT477,T329,T504
127 (addr_hit[126] & ((|(4...CoveredT477,T330,T329
126 (addr_hit[125] & ((|(4...CoveredT477,T142,T504
125 (addr_hit[124] & ((|(4...CoveredT477,T142,T504
124 (addr_hit[123] & ((|(4...CoveredT477,T329,T504
123 (addr_hit[122] & ((|(4...CoveredT477,T329,T504
122 (addr_hit[121] & ((|(4...CoveredT477,T329,T504
121 (addr_hit[120] & ((|(4...CoveredT477,T504,T511
120 (addr_hit[119] & ((|(4...CoveredT477,T504,T144
119 (addr_hit[118] & ((|(4...CoveredT477,T504,T511
118 (addr_hit[117] & ((|(4...CoveredT477,T142,T329
117 (addr_hit[116] & ((|(4...CoveredT477,T504,T144
116 (addr_hit[115] & ((|(4...CoveredT477,T504,T511
115 (addr_hit[114] & ((|(4...CoveredT477,T504,T511
114 (addr_hit[113] & ((|(4...CoveredT477,T329,T504
113 (addr_hit[112] & ((|(4...CoveredT477,T504,T144
112 (addr_hit[111] & ((|(4...CoveredT477,T142,T330
111 (addr_hit[110] & ((|(4...CoveredT477,T329,T504
110 (addr_hit[109] & ((|(4...CoveredT477,T330,T329
109 (addr_hit[108] & ((|(4...CoveredT477,T329,T504
108 (addr_hit[107] & ((|(4...CoveredT477,T330,T504
107 (addr_hit[106] & ((|(4...CoveredT477,T504,T511
106 (addr_hit[105] & ((|(4...CoveredT477,T142,T330
105 (addr_hit[104] & ((|(4...CoveredT477,T142,T504
104 (addr_hit[103] & ((|(4...CoveredT477,T142,T504
103 (addr_hit[102] & ((|(4...CoveredT477,T504,T360
102 (addr_hit[101] & ((|(4...CoveredT477,T330,T504
101 (addr_hit[100] & ((|(4...CoveredT477,T504,T360
100 (addr_hit[99] & ((|(4'...CoveredT477,T142,T504
99 (addr_hit[98] & ((|(4'...CoveredT477,T330,T504
98 (addr_hit[97] & ((|(4'...CoveredT477,T329,T504
97 (addr_hit[96] & ((|(4'...CoveredT477,T504,T144
96 (addr_hit[95] & ((|(4'...CoveredT477,T142,T504
95 (addr_hit[94] & ((|(4'...CoveredT477,T329,T504
94 (addr_hit[93] & ((|(4'...CoveredT477,T504,T360
93 (addr_hit[92] & ((|(4'...CoveredT477,T329,T504
92 (addr_hit[91] & ((|(4'...CoveredT477,T329,T504
91 (addr_hit[90] & ((|(4'...CoveredT477,T330,T504
90 (addr_hit[89] & ((|(4'...CoveredT477,T142,T330
89 (addr_hit[88] & ((|(4'...CoveredT477,T329,T504
88 (addr_hit[87] & ((|(4'...CoveredT477,T329,T504
87 (addr_hit[86] & ((|(4'...CoveredT477,T329,T504
86 (addr_hit[85] & ((|(4'...CoveredT477,T504,T144
85 (addr_hit[84] & ((|(4'...CoveredT477,T329,T504
84 (addr_hit[83] & ((|(4'...CoveredT477,T329,T504
83 (addr_hit[82] & ((|(4'...CoveredT477,T504,T360
82 (addr_hit[81] & ((|(4'...CoveredT477,T330,T329
81 (addr_hit[80] & ((|(4'...CoveredT477,T504,T511
80 (addr_hit[79] & ((|(4'...CoveredT477,T504,T511
79 (addr_hit[78] & ((|(4'...CoveredT477,T142,T330
78 (addr_hit[77] & ((|(4'...CoveredT477,T329,T504
77 (addr_hit[76] & ((|(4'...CoveredT477,T329,T504
76 (addr_hit[75] & ((|(4'...CoveredT477,T504,T511
75 (addr_hit[74] & ((|(4'...CoveredT477,T504,T144
74 (addr_hit[73] & ((|(4'...CoveredT477,T330,T329
73 (addr_hit[72] & ((|(4'...CoveredT477,T504,T511
72 (addr_hit[71] & ((|(4'...CoveredT477,T329,T504
71 (addr_hit[70] & ((|(4'...CoveredT477,T142,T504
70 (addr_hit[69] & ((|(4'...CoveredT477,T142,T504
69 (addr_hit[68] & ((|(4'...CoveredT477,T330,T144
68 (addr_hit[67] & ((|(4'...CoveredT477,T142,T504
67 (addr_hit[66] & ((|(4'...CoveredT477,T142,T504
66 (addr_hit[65] & ((|(4'...CoveredT477,T329,T504
65 (addr_hit[64] & ((|(4'...CoveredT477,T504,T511
64 (addr_hit[63] & ((|(4'...CoveredT477,T142,T330
63 (addr_hit[62] & ((|(4'...CoveredT477,T329,T504
62 (addr_hit[61] & ((|(4'...CoveredT477,T504,T144
61 (addr_hit[60] & ((|(4'...CoveredT477,T329,T504
60 (addr_hit[59] & ((|(4'...CoveredT477,T329,T504
59 (addr_hit[58] & ((|(4'...CoveredT477,T329,T504
58 (addr_hit[57] & ((|(4'...CoveredT477,T142,T504
57 (addr_hit[56] & ((|(4'...CoveredT477,T504,T144
56 (addr_hit[55] & ((|(4'...CoveredT477,T330,T504
55 (addr_hit[54] & ((|(4'...CoveredT477,T330,T329
54 (addr_hit[53] & ((|(4'...CoveredT477,T504,T360
53 (addr_hit[52] & ((|(4'...CoveredT477,T330,T504
52 (addr_hit[51] & ((|(4'...CoveredT477,T142,T504
51 (addr_hit[50] & ((|(4'...CoveredT477,T329,T504
50 (addr_hit[49] & ((|(4'...CoveredT477,T329,T504
49 (addr_hit[48] & ((|(4'...CoveredT477,T504,T144
48 (addr_hit[47] & ((|(4'...CoveredT477,T329,T504
47 (addr_hit[46] & ((|(4'...CoveredT477,T504,T511
46 (addr_hit[45] & ((|(4'...CoveredT477,T330,T504
45 (addr_hit[44] & ((|(4'...CoveredT477,T330,T504
44 (addr_hit[43] & ((|(4'...CoveredT477,T329,T504
43 (addr_hit[42] & ((|(4'...CoveredT477,T504,T360
42 (addr_hit[41] & ((|(4'...CoveredT477,T330,T504
41 (addr_hit[40] & ((|(4'...CoveredT477,T329,T504
40 (addr_hit[39] & ((|(4'...CoveredT477,T504,T511
39 (addr_hit[38] & ((|(4'...CoveredT477,T329,T504
38 (addr_hit[37] & ((|(4'...CoveredT477,T330,T329
37 (addr_hit[36] & ((|(4'...CoveredT477,T142,T330
36 (addr_hit[35] & ((|(4'...CoveredT477,T330,T329
35 (addr_hit[34] & ((|(4'...CoveredT477,T142,T329
34 (addr_hit[33] & ((|(4'...CoveredT477,T142,T504
33 (addr_hit[32] & ((|(4'...CoveredT477,T504,T511
32 (addr_hit[31] & ((|(4'...CoveredT477,T504,T511
31 (addr_hit[30] & ((|(4'...CoveredT477,T504,T360
30 (addr_hit[29] & ((|(4'...CoveredT477,T504,T511
29 (addr_hit[28] & ((|(4'...CoveredT477,T330,T504
28 (addr_hit[27] & ((|(4'...CoveredT477,T142,T504
27 (addr_hit[26] & ((|(4'...CoveredT477,T329,T504
26 (addr_hit[25] & ((|(4'...CoveredT477,T142,T329
25 (addr_hit[24] & ((|(4'...CoveredT477,T329,T504
24 (addr_hit[23] & ((|(4'...CoveredT477,T329,T504
23 (addr_hit[22] & ((|(4'...CoveredT477,T142,T504
22 (addr_hit[21] & ((|(4'...CoveredT477,T330,T329
21 (addr_hit[20] & ((|(4'...CoveredT477,T330,T504
20 (addr_hit[19] & ((|(4'...CoveredT477,T504,T144
19 (addr_hit[18] & ((|(4'...CoveredT477,T329,T504
18 (addr_hit[17] & ((|(4'...CoveredT477,T504,T144
17 (addr_hit[16] & ((|(4'...CoveredT477,T504,T511
16 (addr_hit[15] & ((|(4'...CoveredT477,T142,T504
15 (addr_hit[14] & ((|(4'...CoveredT477,T144,T511
14 (addr_hit[13] & ((|(4'...CoveredT477,T504,T511
13 (addr_hit[12] & ((|(4'...CoveredT477,T142,T504
12 (addr_hit[11] & ((|(4'...CoveredT477,T142,T504
11 (addr_hit[10] & ((|(4'...CoveredT477,T329,T504
10 (addr_hit[9] & ((|(4'b...CoveredT477,T142,T504
9 (addr_hit[8] & ((|(4'b...CoveredT477,T142,T330
8 (addr_hit[7] & ((|(4'b...CoveredT477,T329,T504
7 (addr_hit[6] & ((|(4'b...CoveredT477,T330,T504
6 (addr_hit[5] & ((|(4'b...CoveredT477,T330,T504
5 (addr_hit[4] & ((|(4'b...CoveredT477,T504,T144
4 (addr_hit[3] & ((|(4'b...CoveredT477,T142,T504
3 (addr_hit[2] & ((|(4'b...CoveredT477,T142,T504
2 (addr_hit[1] & ((|(4'b...CoveredT477,T504,T144
1 (addr_hit[0] & ((|(4'b...CoveredT2,T60,T64

 LINE       16500
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT76,T77,T78
10CoveredT236,T63,T678
11CoveredT2,T60,T64

 LINE       16500
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T504,T144

 LINE       16500
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T504,T144

 LINE       16500
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT2,T122,T194
11CoveredT477,T142,T330

 LINE       16500
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T144,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT121,T191,T192
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T504,T144

 LINE       16500
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T504,T144

 LINE       16500
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T330,T329

 LINE       16500
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT182,T183,T184
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T142,T329

 LINE       16500
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T504,T360

 LINE       16500
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT13,T14,T291
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T142,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T142,T329

 LINE       16500
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T330,T329

 LINE       16500
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T142,T330

 LINE       16500
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T330,T329

 LINE       16500
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T504,T360

 LINE       16500
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T330,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T504,T511

 LINE       16500
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T329,T504

 LINE       16500
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T60,T64
10CoveredT150,T288,T23
11CoveredT477,T504,T144
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%