Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138842	1			T70	26		T72	5		T78	18
values[2]	8741	1			T70	1		T77	31		T498	1
values[3]	3202	1			T498	1		T745	1		T407	1
values[4]	1834	1			T498	1		T745	1		T508	11
values[5]	1098	1			T498	1		T745	1		T508	12
values[6]	797	1			T498	1		T745	1		T508	14
values[7]	612	1			T498	1		T745	1		T508	14
values[8]	475	1			T498	1		T745	1		T508	25
values[9]	440	1			T498	1		T745	1		T508	8
values[10]	490	1			T498	1		T745	1		T508	23
values[11]	413	1			T498	1		T745	1		T508	7
values[12]	446	1			T498	1		T745	1		T508	16
values[13]	428	1			T498	1		T745	1		T508	13
values[14]	371	1			T498	1		T745	1		T508	3
values[15]	355	1			T498	1		T745	1		T508	5
values[16]	438	1			T498	1		T745	1		T508	12
values[17]	407	1			T498	1		T745	1		T508	7
values[18]	387	1			T498	1		T745	1		T508	9
values[19]	375	1			T498	1		T745	1		T508	7
values[20]	405	1			T498	1		T745	1		T508	12
values[21]	347	1			T498	1		T745	1		T508	9
values[22]	395	1			T498	1		T745	1		T508	6
values[23]	376	1			T498	1		T745	1		T508	4
values[24]	360	1			T498	1		T745	1		T508	3
values[25]	385	1			T498	1		T745	1		T508	13
values[26]	429	1			T498	1		T745	1		T508	7
values[27]	402	1			T498	1		T745	1		T508	9
values[28]	390	1			T498	1		T745	1		T508	5
values[29]	393	1			T498	1		T745	1		T508	6
values[30]	312	1			T498	1		T745	1		T508	9
values[31]	404	1			T498	1		T745	1		T508	8
values[32]	355	1			T498	1		T745	1		T508	20
values[33]	404	1			T498	1		T745	1		T508	3
values[34]	407	1			T498	1		T745	1		T508	14
values[35]	375	1			T498	1		T745	1		T508	6
values[36]	393	1			T498	1		T745	1		T508	3
values[37]	367	1			T498	1		T745	1		T508	7
values[38]	373	1			T498	1		T745	1		T508	6
values[39]	425	1			T498	1		T745	1		T508	7
values[40]	363	1			T498	1		T745	1		T508	5
values[41]	345	1			T498	1		T745	1		T508	4
values[42]	368	1			T498	1		T745	1		T508	17
values[43]	367	1			T498	1		T745	1		T508	2
values[44]	401	1			T498	1		T745	1		T508	10
values[45]	386	1			T498	1		T745	1		T508	11
values[46]	302	1			T498	1		T745	1		T508	5
values[47]	338	1			T498	1		T745	2		T508	8
values[48]	335	1			T498	1		T745	1		T508	7
values[49]	343	1			T498	1		T745	1		T508	19
values[50]	388	1			T498	1		T745	1		T508	16
values[51]	294	1			T498	1		T745	1		T508	5
values[52]	330	1			T498	1		T745	1		T508	9
values[53]	341	1			T498	1		T745	1		T508	4
values[54]	296	1			T498	1		T745	1		T508	6
values[55]	294	1			T498	1		T745	1		T751	6
values[56]	324	1			T498	1		T745	1		T751	8
values[57]	291	1			T498	1		T745	1		T751	8
values[58]	325	1			T498	1		T745	1		T751	3
values[59]	299	1			T498	1		T745	1		T751	9
values[60]	295	1			T498	1		T745	1		T751	7
values[61]	336	1			T498	1		T745	1		T751	6
values[62]	278	1			T498	1		T745	1		T751	4
values[63]	234	1			T498	1		T745	1		T751	8
values[64]	225	1			T498	1		T745	1		T751	13
values[65]	183	1			T498	1		T745	1		T751	9
values[66]	206	1			T498	1		T745	1		T751	7
values[67]	211	1			T498	1		T745	1		T751	12
values[68]	135	1			T498	1		T745	1		T751	4
values[69]	174	1			T498	2		T745	1		T566	6
values[70]	134	1			T498	1		T745	1		T758	1
values[71]	136	1			T498	1		T745	1		T758	1
values[72]	117	1			T498	1		T745	1		T758	1
values[73]	107	1			T498	1		T745	1		T758	1
values[74]	83	1			T498	1		T745	1		T758	1
values[75]	73	1			T498	1		T745	1		T758	1
values[76]	82	1			T498	1		T745	1		T758	1
values[77]	91	1			T498	1		T745	1		T758	1
values[78]	70	1			T498	1		T745	1		T758	1
values[79]	84	1			T498	1		T745	1		T758	1
values[80]	99	1			T498	1		T745	1		T758	1
values[81]	68	1			T498	1		T745	1		T758	1
values[82]	107	1			T498	1		T745	1		T758	1
values[83]	70	1			T498	1		T745	1		T758	1
values[84]	80	1			T498	1		T745	1		T758	2
values[85]	104	1			T498	1		T745	1		T758	8
values[86]	76	1			T498	1		T745	1		T758	1
values[87]	112	1			T498	1		T745	1		T758	1
values[88]	81	1			T498	1		T745	1		T758	3
values[89]	76	1			T498	1		T745	1		T758	2
values[90]	86	1			T498	1		T745	1		T758	1
values[91]	58	1			T498	1		T745	1		T758	2
values[92]	55	1			T498	1		T745	1		T758	3
values[93]	79	1			T498	1		T745	1		T758	3
values[94]	57	1			T498	1		T745	1		T758	2
values[95]	71	1			T498	1		T745	1		T758	9
values[96]	64	1			T498	1		T745	1		T758	2
values[97]	70	1			T498	1		T745	1		T758	1
values[98]	69	1			T498	1		T745	1		T758	1
values[99]	63	1			T498	1		T745	1		T758	2
values[100]	58	1			T498	1		T745	1		T758	3
values[101]	69	1			T498	1		T745	1		T758	2
values[102]	63	1			T498	1		T745	1		T758	4
values[103]	61	1			T498	1		T745	1		T758	5
values[104]	54	1			T498	1		T745	1		T758	2
values[105]	69	1			T498	1		T745	1		T758	3
values[106]	62	1			T498	1		T745	1		T758	1
values[107]	62	1			T498	1		T745	1		T758	3
values[108]	60	1			T498	1		T745	1		T758	3
values[109]	50	1			T498	1		T745	1		T758	2
values[110]	49	1			T498	5		T745	1		T758	1
values[111]	58	1			T498	3		T745	1		T758	3
values[112]	64	1			T498	3		T745	1		T758	2
values[113]	51	1			T498	1		T745	1		T758	1
values[114]	67	1			T498	2		T745	1		T758	1
values[115]	45	1			T498	1		T745	2		T758	2
values[116]	55	1			T498	1		T745	2		T758	5
values[117]	53	1			T498	1		T745	2		T758	6
values[118]	50	1			T498	1		T745	3		T758	3
values[119]	39	1			T498	1		T745	2		T758	1
values[120]	50	1			T498	1		T745	1		T758	1
values[121]	50	1			T498	1		T745	1		T758	1
values[122]	54	1			T498	1		T745	2		T758	1
values[123]	55	1			T498	1		T745	3		T758	2
values[124]	60	1			T498	3		T745	6		T758	2
values[125]	75	1			T498	2		T745	1		T758	1
values[126]	116	1			T498	3		T745	2		T758	2
values[127]	653	1			T498	30		T745	32		T758	30
values[128]	5150	1			T498	264		T745	354		T758	222