Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	95.49	94.26	95.69		94.98	97.38	99.55

Total tests in report: 2783

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.54	40.54	45.32	45.32	43.10	43.10	33.20	33.20			58.23	58.23	63.03	63.03	0.38	0.38	/workspace/coverage/default/25.chip_sw_all_escalation_resets.367818907
50.37	9.83	54.38	9.06	53.57	10.47	36.35	3.15			67.17	8.93	90.02	26.99	0.75	0.38	/workspace/coverage/default/0.chip_jtag_csr_rw.4074663161
57.86	7.49	63.58	9.21	56.70	3.14	39.18	2.83			67.36	0.20	90.02	0.00	30.31	29.56	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3621115810
64.00	6.14	76.51	12.93	65.24	8.54	43.12	3.94			78.80	11.43	90.02	0.00	30.31	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2383208202
66.95	2.95	76.51	0.00	66.04	0.80	43.12	0.00			79.10	0.30	90.02	0.00	46.93	16.61	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1249416287
69.46	2.50	76.51	0.00	66.04	0.00	58.15	15.03			79.10	0.00	90.02	0.00	46.93	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3796933037
71.80	2.34	81.74	5.23	69.86	3.82	61.58	3.43			80.65	1.55	90.02	0.00	46.93	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1517194366
74.03	2.24	83.64	1.90	76.00	6.14	62.03	0.45			84.66	4.01	90.02	0.00	47.86	0.93	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3569934558
75.92	1.89	83.89	0.25	76.20	0.20	72.32	10.29			84.88	0.21	90.39	0.37	47.86	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2827223488
77.78	1.86	83.89	0.00	76.51	0.31	72.32	0.00			84.88	0.00	90.39	0.00	58.69	10.83	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1672696164
79.47	1.69	83.94	0.05	77.42	0.90	74.49	2.17			85.05	0.17	90.39	0.00	65.53	6.84	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2741141476
80.89	1.43	86.18	2.25	80.20	2.78	76.02	1.53			87.04	1.99	90.39	0.00	65.54	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3377027469
82.06	1.17	88.08	1.89	82.63	2.44	76.32	0.30			89.40	2.37	90.39	0.00	65.54	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4283749873
83.13	1.07	88.08	0.00	82.93	0.29	76.37	0.05			89.47	0.07	90.39	0.00	71.58	6.04	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.178662868
84.13	0.99	88.60	0.52	83.37	0.45	80.66	4.29			89.76	0.30	90.57	0.18	71.80	0.22	/workspace/coverage/default/1.chip_jtag_csr_rw.2479166247
85.04	0.91	88.60	0.00	83.61	0.23	80.66	0.00			89.86	0.10	90.57	0.00	76.92	5.12	/workspace/coverage/cover_reg_top/63.xbar_stress_all.1034206969
85.94	0.90	89.85	1.25	84.61	1.01	82.61	1.95			91.05	1.19	90.57	0.00	76.92	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.910841988
86.77	0.83	89.85	0.00	84.61	0.00	82.61	0.00			91.05	0.00	90.57	0.00	81.92	4.99	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2084377462
87.54	0.77	90.16	0.31	84.74	0.13	82.62	0.02			91.17	0.12	94.64	4.07	81.92	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2697678654
88.21	0.67	90.16	0.00	84.74	0.00	82.62	0.00			91.17	0.00	94.64	0.00	85.95	4.03	/workspace/coverage/cover_reg_top/98.xbar_access_same_device.2375673341
88.86	0.65	91.16	1.00	85.49	0.75	82.80	0.17			91.86	0.69	95.93	1.29	85.95	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.107659277
89.50	0.64	91.20	0.04	88.63	3.14	83.01	0.21			91.89	0.03	95.93	0.00	86.36	0.41	/workspace/coverage/cover_reg_top/4.chip_tl_errors.774569853
90.09	0.59	91.20	0.00	88.63	0.00	83.01	0.00			91.89	0.00	95.93	0.00	89.87	3.51	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3157341586
90.60	0.51	91.23	0.03	88.67	0.04	84.37	1.36			91.89	0.00	95.93	0.00	91.52	1.64	/workspace/coverage/default/1.chip_sw_alert_test.61379084
91.08	0.48	91.24	0.01	88.73	0.06	85.10	0.74			91.90	0.01	95.93	0.00	93.61	2.09	/workspace/coverage/cover_reg_top/77.xbar_error_random.158772353
91.56	0.48	91.25	0.01	88.73	0.01	87.75	2.65			91.90	0.00	96.12	0.18	93.61	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2155592296
91.97	0.41	91.92	0.67	89.51	0.78	88.05	0.29			92.62	0.72	96.12	0.00	93.61	0.00	/workspace/coverage/default/2.chip_sw_gpio.4166410901
92.31	0.34	92.33	0.41	89.65	0.14	89.43	1.39			92.70	0.08	96.12	0.00	93.62	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1221840168
92.64	0.34	92.87	0.55	90.31	0.66	89.85	0.42			93.09	0.40	96.12	0.00	93.62	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2225936311
92.90	0.26	93.37	0.50	90.75	0.44	90.03	0.18			93.54	0.45	96.12	0.00	93.62	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1610059621
93.16	0.26	93.37	0.00	90.75	0.00	90.03	0.00			93.54	0.00	96.12	0.00	95.16	1.54	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.643377230
93.40	0.24	93.37	0.00	90.75	0.00	90.03	0.00			93.54	0.00	96.12	0.00	96.59	1.43	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.4192849079
93.62	0.22	94.19	0.82	90.97	0.22	90.17	0.15			93.65	0.11	96.12	0.00	96.59	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3106389213
93.77	0.16	94.19	0.00	90.97	0.00	91.13	0.95			93.65	0.00	96.12	0.00	96.59	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.578366949
93.90	0.13	94.40	0.20	91.12	0.16	91.36	0.24			93.80	0.16	96.12	0.00	96.59	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1139697186
94.02	0.12	94.40	0.00	91.14	0.01	91.36	0.00			93.80	0.00	96.12	0.00	97.32	0.73	/workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3186670830
94.14	0.12	94.40	0.00	91.14	0.00	91.36	0.00			93.80	0.00	96.12	0.00	98.04	0.72	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3886642085
94.26	0.12	94.40	0.00	91.14	0.00	92.08	0.71			93.80	0.00	96.12	0.00	98.04	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.819936043
94.38	0.12	94.40	0.00	91.14	0.00	92.75	0.67			93.80	0.00	96.12	0.00	98.07	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3707474364
94.48	0.10	94.41	0.01	91.43	0.29	92.75	0.00			94.13	0.33	96.12	0.00	98.07	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1333304973
94.58	0.10	94.41	0.00	92.03	0.60	92.75	0.00			94.13	0.00	96.12	0.00	98.07	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1436455091
94.68	0.10	94.41	0.00	92.05	0.03	93.27	0.52			94.15	0.02	96.12	0.00	98.08	0.01	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.267381031
94.76	0.08	94.53	0.12	92.14	0.09	93.47	0.20			94.24	0.09	96.12	0.00	98.08	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1976429066
94.84	0.07	94.53	0.01	92.35	0.21	93.47	0.00			94.47	0.23	96.12	0.00	98.08	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2544766107
94.91	0.07	94.53	0.00	92.51	0.16	93.47	0.00			94.49	0.02	96.12	0.00	98.32	0.23	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1328480276
94.96	0.06	94.54	0.01	92.54	0.03	93.57	0.10			94.50	0.02	96.30	0.18	98.32	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2035488754
95.02	0.05	94.54	0.00	92.54	0.00	93.90	0.33			94.50	0.00	96.30	0.00	98.32	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3174369090
95.07	0.05	94.63	0.08	92.55	0.01	93.90	0.01			94.52	0.02	96.49	0.18	98.33	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2236746745
95.12	0.05	94.69	0.06	92.63	0.08	93.91	0.01			94.65	0.13	96.49	0.00	98.33	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2798095448
95.16	0.04	94.72	0.03	92.67	0.04	94.07	0.16			94.68	0.02	96.49	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2459612791
95.20	0.04	94.73	0.01	92.69	0.01	94.07	0.00			94.70	0.02	96.67	0.18	98.34	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.809113546
95.24	0.04	94.74	0.01	92.70	0.01	94.08	0.01			94.71	0.01	96.86	0.18	98.36	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933161907
95.28	0.04	94.74	0.00	92.71	0.01	94.12	0.04			94.71	0.00	97.04	0.18	98.36	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3878386045
95.32	0.04	94.74	0.01	92.72	0.01	94.12	0.01			94.72	0.01	97.23	0.18	98.37	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1501170476
95.35	0.04	94.75	0.01	92.73	0.01	94.13	0.01			94.73	0.01	97.41	0.18	98.38	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2979781536
95.39	0.04	94.75	0.00	92.73	0.00	94.30	0.17			94.73	0.00	97.41	0.00	98.43	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2496772269
95.43	0.04	94.75	0.00	92.88	0.14	94.30	0.00			94.76	0.03	97.41	0.00	98.46	0.04	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3809852821
95.46	0.03	94.75	0.00	92.88	0.00	94.50	0.19			94.76	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4162210751
95.49	0.03	94.82	0.08	92.88	0.00	94.60	0.10			94.77	0.01	97.41	0.00	98.46	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.2609843240
95.52	0.03	94.82	0.00	92.88	0.00	94.78	0.18			94.77	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4237832391
95.55	0.03	94.82	0.00	93.05	0.17	94.78	0.00			94.77	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.1113485274
95.57	0.03	94.89	0.06	93.07	0.03	94.80	0.01			94.82	0.05	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2586930513
95.60	0.03	94.93	0.04	93.13	0.06	94.82	0.02			94.85	0.03	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3597474156
95.63	0.03	94.93	0.00	93.13	0.00	94.97	0.15			94.85	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4141507834
95.65	0.02	94.93	0.00	93.27	0.13	94.97	0.00			94.85	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1021394695
95.67	0.02	94.96	0.03	93.33	0.06	94.98	0.01			94.87	0.02	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3197033262
95.69	0.02	95.02	0.05	93.38	0.05	94.98	0.00			94.90	0.02	97.41	0.00	98.46	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3673240344
95.71	0.02	95.02	0.01	93.38	0.00	95.08	0.10			94.91	0.01	97.41	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2741128076
95.73	0.02	95.02	0.00	93.38	0.00	95.18	0.11			94.91	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.864912087
95.74	0.02	95.02	0.00	93.40	0.01	95.18	0.00			94.91	0.00	97.41	0.00	98.54	0.08	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3638891351
95.76	0.02	95.02	0.00	93.42	0.03	95.25	0.06			94.91	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2171884174
95.77	0.01	95.02	0.00	93.49	0.07	95.25	0.00			94.92	0.02	97.41	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all.853090265
95.78	0.01	95.02	0.00	93.56	0.07	95.25	0.00			94.92	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1476622407
95.80	0.01	95.06	0.04	93.58	0.02	95.25	0.00			94.93	0.01	97.41	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.39416916
95.81	0.01	95.06	0.00	93.60	0.02	95.25	0.00			94.93	0.00	97.41	0.00	98.59	0.05	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3080631972
95.82	0.01	95.06	0.00	93.66	0.06	95.25	0.00			94.93	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3839945216
95.83	0.01	95.06	0.00	93.66	0.00	95.31	0.06			94.93	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3371040772
95.84	0.01	95.06	0.00	93.66	0.00	95.31	0.00			94.93	0.00	97.41	0.00	98.65	0.06	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.157656424
95.85	0.01	95.09	0.03	93.67	0.01	95.33	0.02			94.93	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2617470063
95.85	0.01	95.12	0.03	93.67	0.01	95.33	0.01			94.95	0.02	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1607533976
95.86	0.01	95.12	0.00	93.72	0.05	95.33	0.00			94.95	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3987997316
95.87	0.01	95.14	0.02	93.73	0.01	95.33	0.01			94.96	0.02	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.477294406
95.88	0.01	95.14	0.00	93.73	0.00	95.38	0.05			94.96	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3962264084
95.89	0.01	95.14	0.00	93.78	0.05	95.38	0.00			94.96	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2074967571
95.89	0.01	95.14	0.01	93.82	0.04	95.38	0.00			94.96	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2727055689
95.90	0.01	95.15	0.01	93.86	0.04	95.38	0.01			94.96	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2793076696
95.91	0.01	95.15	0.00	93.88	0.02	95.38	0.00			94.96	0.00	97.41	0.00	98.67	0.02	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4005768198
95.92	0.01	95.15	0.00	93.90	0.03	95.38	0.00			94.96	0.00	97.41	0.00	98.68	0.01	/workspace/coverage/cover_reg_top/16.xbar_stress_all.3370320623
95.92	0.01	95.15	0.00	93.91	0.01	95.41	0.03			94.96	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4084869339
95.93	0.01	95.15	0.00	93.91	0.00	95.45	0.04			94.96	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1946884840
95.93	0.01	95.15	0.00	93.91	0.00	95.45	0.00			94.96	0.00	97.41	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.28911374
95.94	0.01	95.15	0.00	93.94	0.03	95.45	0.00			94.96	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.898006359
95.94	0.01	95.15	0.00	93.98	0.03	95.45	0.00			94.96	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1760725339
95.95	0.01	95.15	0.00	94.00	0.03	95.45	0.00			94.96	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1109880612
95.95	0.01	95.15	0.00	94.00	0.00	95.48	0.03			94.96	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1410009289
95.96	0.01	95.15	0.00	94.01	0.01	95.48	0.00			94.96	0.00	97.41	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1671783971
95.96	0.01	95.15	0.00	94.01	0.00	95.51	0.03			94.96	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2699421149
95.97	0.01	95.15	0.00	94.01	0.00	95.53	0.03			94.96	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1811325516
95.97	0.01	95.15	0.00	94.03	0.03	95.53	0.00			94.96	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all.2927485746
95.98	0.01	95.15	0.00	94.03	0.00	95.53	0.00			94.96	0.00	97.41	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1053607285
95.98	0.01	95.15	0.00	94.06	0.02	95.53	0.00			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3651372924
95.98	0.01	95.15	0.00	94.08	0.02	95.53	0.00			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3336192807
95.99	0.01	95.15	0.00	94.09	0.01	95.54	0.01			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1879569327
95.99	0.01	95.15	0.00	94.09	0.00	95.56	0.02			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1177307210
95.99	0.01	95.15	0.00	94.09	0.00	95.58	0.02			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3335323903
96.00	0.01	95.15	0.00	94.11	0.02	95.58	0.00			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_gpio.1871887869
96.00	0.01	95.16	0.01	94.11	0.01	95.58	0.00			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.4075909350
96.00	0.01	95.17	0.01	94.11	0.00	95.59	0.01			94.96	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.3688071637
96.00	0.01	95.17	0.00	94.11	0.00	95.59	0.01			94.96	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2761722772
96.01	0.01	95.17	0.00	94.11	0.01	95.59	0.00			94.96	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/13.chip_tl_errors.715193011
96.01	0.01	95.17	0.00	94.13	0.01	95.59	0.00			94.96	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1190758605
96.01	0.01	95.17	0.00	94.14	0.01	95.59	0.00			94.96	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all.991353078
96.01	0.01	95.17	0.00	94.16	0.01	95.59	0.00			94.96	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3807738238
96.02	0.01	95.17	0.00	94.16	0.00	95.60	0.01			94.96	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3430086277
96.02	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3490437738
96.02	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1973483885
96.02	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.6804397
96.02	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.251858519
96.03	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982822737
96.03	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238450515
96.03	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4063505060
96.03	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2318392492
96.03	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3237566130
96.04	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.937418503
96.04	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2276504652
96.04	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3909197617
96.04	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3651097340
96.04	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1668792909
96.05	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688789025
96.05	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078797994
96.05	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1474868596
96.05	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138905333
96.05	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2315891026
96.06	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3640027724
96.06	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2647430730
96.06	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810410263
96.06	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1145998679
96.06	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540384271
96.07	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3681880709
96.07	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169698929
96.07	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1506467733
96.07	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.830691114
96.07	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657549516
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3966865237
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015331597
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1932996421
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2723682641
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.4149387176
96.08	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1552786768
96.09	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3716323797
96.09	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1993468586
96.09	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3322504780
96.09	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3717543708
96.09	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.485310161
96.10	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193603045
96.10	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3098156864
96.10	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.9466608
96.10	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3956195159
96.10	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3724884557
96.11	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702372043
96.11	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2481716575
96.11	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2612315733
96.11	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4101058152
96.11	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1939926556
96.12	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3275516883
96.12	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745348577
96.12	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1431675841
96.12	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.813731616
96.12	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.158601060
96.13	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3202476057
96.13	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3090936639
96.13	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4130825414
96.13	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.932375367
96.13	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218953928
96.14	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2869239532
96.14	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1033197335
96.14	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3043867386
96.14	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3205915333
96.14	0.01	95.17	0.00	94.16	0.00	95.60	0.00			94.96	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.106296502
96.15	0.01	95.17	0.00	94.17	0.01	95.60	0.00			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.995602508
96.15	0.01	95.17	0.00	94.18	0.01	95.60	0.00			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.520048485
96.15	0.01	95.18	0.01	94.18	0.01	95.60	0.00			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/18.chip_csr_rw.820341673
96.15	0.01	95.18	0.01	94.18	0.00	95.61	0.01			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.80720259
96.15	0.01	95.18	0.00	94.18	0.00	95.62	0.01			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3114225542
96.15	0.01	95.18	0.00	94.18	0.00	95.63	0.01			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3300194926
96.16	0.01	95.19	0.01	94.18	0.00	95.64	0.01			94.96	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4256036776
96.16	0.01	95.19	0.00	94.18	0.00	95.64	0.00			94.97	0.01	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1095966848
96.16	0.01	95.19	0.00	94.18	0.00	95.64	0.00			94.98	0.01	97.41	0.00	99.55	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.1058449493
96.16	0.01	95.19	0.00	94.19	0.01	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all.3916990366
96.16	0.01	95.19	0.00	94.20	0.01	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2842562098
96.16	0.01	95.19	0.00	94.20	0.01	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_gpio.1794025410
96.16	0.01	95.19	0.00	94.21	0.01	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3143359858
96.16	0.01	95.19	0.00	94.22	0.01	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2493342940
96.17	0.01	95.19	0.01	94.22	0.00	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3362712175
96.17	0.01	95.20	0.01	94.22	0.00	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2818540537
96.17	0.01	95.21	0.01	94.22	0.00	95.64	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3675667349
96.17	0.01	95.21	0.00	94.22	0.00	95.64	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1534932385
96.17	0.01	95.21	0.00	94.22	0.00	95.65	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1093005792
96.17	0.01	95.21	0.00	94.22	0.00	95.65	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1548049898
96.17	0.01	95.21	0.00	94.22	0.00	95.66	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3919843981
96.17	0.01	95.21	0.00	94.22	0.00	95.66	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3735233212
96.17	0.01	95.21	0.00	94.22	0.00	95.67	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.753723019
96.17	0.01	95.21	0.00	94.22	0.00	95.67	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2588467097
96.17	0.01	95.21	0.00	94.22	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.1221965369
96.18	0.01	95.21	0.00	94.22	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.4116772025
96.18	0.01	95.21	0.00	94.23	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.529271261
96.18	0.01	95.21	0.00	94.23	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.4073326770
96.18	0.01	95.21	0.00	94.24	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2476544352
96.18	0.01	95.21	0.00	94.24	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.1413737602
96.18	0.01	95.21	0.00	94.24	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.533948107
96.18	0.01	95.21	0.00	94.25	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.696612586
96.18	0.01	95.21	0.00	94.25	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1698769584
96.18	0.01	95.21	0.00	94.25	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.711712609
96.18	0.01	95.21	0.00	94.26	0.01	95.67	0.00			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4139823045
96.18	0.01	95.21	0.00	94.26	0.00	95.68	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.825702425
96.18	0.01	95.21	0.00	94.26	0.00	95.68	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2477035696
96.18	0.01	95.21	0.00	94.26	0.00	95.68	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1327081377
96.18	0.01	95.21	0.00	94.26	0.00	95.68	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3691808659
96.18	0.01	95.21	0.00	94.26	0.00	95.68	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4085508722
96.18	0.01	95.21	0.00	94.26	0.00	95.69	0.01			94.98	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2238266416

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4149708605
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3016789024
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2307695259
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.941078132
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3703887940
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.353140637
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4041305348
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2596550706
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2715185138
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.367202919
/workspace/coverage/cover_reg_top/0.xbar_error_random.1909869021
/workspace/coverage/cover_reg_top/0.xbar_random.1990940050
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4038596975
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3456671266
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.444829155
/workspace/coverage/cover_reg_top/0.xbar_same_source.1580536724
/workspace/coverage/cover_reg_top/0.xbar_smoke.3592607150
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.826580103
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2315279230
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3751569126
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2483100229
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2583590895
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1188971764
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2606650992
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2209671739
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.46429300
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.351016232
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3044956047
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.793763037
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.173886619
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2505653947
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3041054035
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2714727190
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1081459994
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2715744149
/workspace/coverage/cover_reg_top/1.xbar_error_random.2900675740
/workspace/coverage/cover_reg_top/1.xbar_random.2500024461
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2004372670
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.646963023
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.684260619
/workspace/coverage/cover_reg_top/1.xbar_same_source.901912904
/workspace/coverage/cover_reg_top/1.xbar_smoke.4098122152
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.960187932
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.339273916
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.532792475
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2964499716
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.52812056
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4109069
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1065293269
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3060115778
/workspace/coverage/cover_reg_top/10.chip_csr_rw.603115318
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3475445088
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2380623464
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.392361764
/workspace/coverage/cover_reg_top/10.xbar_error_random.3933357170
/workspace/coverage/cover_reg_top/10.xbar_random.3214087527
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.281896324
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2011807185
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.160561362
/workspace/coverage/cover_reg_top/10.xbar_same_source.1517476308
/workspace/coverage/cover_reg_top/10.xbar_smoke.4257124483
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2911858210
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.250047601
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3146079871
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3330030423
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.710952536
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.40055259
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1116392217
/workspace/coverage/cover_reg_top/11.chip_csr_rw.539440327
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.201725079
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3869989480
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.674614574
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1066037770
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1169974091
/workspace/coverage/cover_reg_top/11.xbar_error_random.1522353960
/workspace/coverage/cover_reg_top/11.xbar_random.865170544
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3770404161
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1514035140
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3436832596
/workspace/coverage/cover_reg_top/11.xbar_same_source.2385326654
/workspace/coverage/cover_reg_top/11.xbar_smoke.3413166216
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4282520229
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4019602876
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1310532984
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.723639586
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.953932198
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1066199180
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4021499674
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1832498939
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3508812278
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.95963548
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1218442688
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4290249899
/workspace/coverage/cover_reg_top/12.xbar_error_random.2934670921
/workspace/coverage/cover_reg_top/12.xbar_random.288612116
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2403798950
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2897786719
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3115416918
/workspace/coverage/cover_reg_top/12.xbar_same_source.1930627293
/workspace/coverage/cover_reg_top/12.xbar_smoke.1290866257
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2037340868
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.474978961
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.70475907
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2057316527
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4039658003
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3594937537
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3818906313
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3097927392
/workspace/coverage/cover_reg_top/13.chip_csr_rw.4178362631
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3727013503
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4198540333
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.979560226
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4013307203
/workspace/coverage/cover_reg_top/13.xbar_error_random.3721992407
/workspace/coverage/cover_reg_top/13.xbar_random.1097243885
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.767013783
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1331364157
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.907685607
/workspace/coverage/cover_reg_top/13.xbar_same_source.943653754
/workspace/coverage/cover_reg_top/13.xbar_smoke.2089961462
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4033852473
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1818927067
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2354487374
/workspace/coverage/cover_reg_top/13.xbar_stress_all.4257033111
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4109079569
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3832304468
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3307845468
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.80907089
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3306159948
/workspace/coverage/cover_reg_top/14.chip_tl_errors.653100853
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1137627338
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3273728322
/workspace/coverage/cover_reg_top/14.xbar_error_random.1791498955
/workspace/coverage/cover_reg_top/14.xbar_random.3880172009
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2997543695
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2467312805
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3276330910
/workspace/coverage/cover_reg_top/14.xbar_same_source.3054531058
/workspace/coverage/cover_reg_top/14.xbar_smoke.3128405433
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1354450571
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1435404794
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/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.490251910
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.168187811
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3950656064
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.224605547
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2730969734
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2432237367
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1444591058
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2749038354
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2637476353
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1514920420
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2527394175
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2198404905
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2295586467
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545987321
/workspace/coverage/default/75.chip_sw_all_escalation_resets.627957818
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2131478694
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2908644908
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2945550569
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904469327
/workspace/coverage/default/78.chip_sw_all_escalation_resets.160670657
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962691494
/workspace/coverage/default/79.chip_sw_all_escalation_resets.889724828
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3698932674
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3937171955
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3396467792
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.27908702
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2551701819
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767976984
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.255965190
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750193356
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4193715738
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.840091176
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1441054763
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434008882
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3253927560
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.395636161
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3996101730
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3794347415
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3061588233
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446455982
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3052717413
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.285092458
/workspace/coverage/default/89.chip_sw_all_escalation_resets.427710900
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.321220501
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2613975732
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3223362843
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1634523737
/workspace/coverage/default/90.chip_sw_all_escalation_resets.490291053
/workspace/coverage/default/91.chip_sw_all_escalation_resets.979008823
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2023466229
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2733063386
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3481619341
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2800500486
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1188295886
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3367743255
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2796839551
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2514953677
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2070520660
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2139832146
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3072342935
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2062262584
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.623075157
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.346448968
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1106144635
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.568775295
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3967996947

---

Total test records in report: 2783

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1946884840			Apr 30 04:35:08 PM PDT 24	Apr 30 04:50:59 PM PDT 24	5006036848 ps
T2	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2294992184			Apr 30 04:36:07 PM PDT 24	Apr 30 04:43:40 PM PDT 24	3105282416 ps
T3	/workspace/coverage/default/2.chip_sw_example_manufacturer.2314250537			Apr 30 04:36:21 PM PDT 24	Apr 30 04:39:36 PM PDT 24	2339933136 ps
T84	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1410009289			Apr 30 04:44:39 PM PDT 24	Apr 30 04:52:14 PM PDT 24	2580546840 ps
T30	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1221840168			Apr 30 04:46:33 PM PDT 24	Apr 30 04:54:43 PM PDT 24	5915906810 ps
T31	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.650797892			Apr 30 04:37:25 PM PDT 24	Apr 30 04:46:54 PM PDT 24	5060270780 ps
T32	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1985369820			Apr 30 04:48:00 PM PDT 24	Apr 30 04:57:15 PM PDT 24	5389339000 ps
T13	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2459612791			Apr 30 04:28:56 PM PDT 24	Apr 30 05:00:57 PM PDT 24	7851895861 ps
T85	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1068768685			Apr 30 04:47:15 PM PDT 24	Apr 30 05:05:39 PM PDT 24	8050620472 ps
T61	/workspace/coverage/default/25.chip_sw_all_escalation_resets.367818907			Apr 30 04:50:28 PM PDT 24	Apr 30 04:59:46 PM PDT 24	5162120620 ps
T116	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1692000028			Apr 30 04:32:58 PM PDT 24	Apr 30 04:36:34 PM PDT 24	2510680988 ps
T186	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.267381031			Apr 30 04:33:07 PM PDT 24	Apr 30 04:40:51 PM PDT 24	4650062016 ps
T42	/workspace/coverage/default/3.chip_tap_straps_testunlock0.98316154			Apr 30 04:46:05 PM PDT 24	Apr 30 04:58:23 PM PDT 24	8275287814 ps
T169	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3094400647			Apr 30 04:36:23 PM PDT 24	Apr 30 04:46:51 PM PDT 24	4722484132 ps
T208	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2171884174			Apr 30 04:22:54 PM PDT 24	Apr 30 04:31:56 PM PDT 24	3754194800 ps
T58	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3377027469			Apr 30 04:49:56 PM PDT 24	Apr 30 04:56:22 PM PDT 24	3631030218 ps
T247	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3828790811			Apr 30 04:36:15 PM PDT 24	Apr 30 04:50:41 PM PDT 24	4464474736 ps
T325	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3276980125			Apr 30 04:24:21 PM PDT 24	Apr 30 04:29:47 PM PDT 24	3491395072 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_stream.2532827840			Apr 30 04:21:42 PM PDT 24	Apr 30 05:39:14 PM PDT 24	18213226000 ps
T19	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.318161688			Apr 30 04:32:00 PM PDT 24	Apr 30 05:25:15 PM PDT 24	20580135211 ps
T187	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1441054763			Apr 30 04:51:39 PM PDT 24	Apr 30 05:00:38 PM PDT 24	6221682964 ps
T815	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2399579726			Apr 30 04:42:00 PM PDT 24	Apr 30 04:49:03 PM PDT 24	3006312022 ps
T4	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2827223488			Apr 30 04:30:36 PM PDT 24	Apr 30 05:58:00 PM PDT 24	50593774198 ps
T59	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1973483885			Apr 30 04:23:14 PM PDT 24	Apr 30 04:28:30 PM PDT 24	3403510492 ps
T200	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.587070113			Apr 30 04:31:16 PM PDT 24	Apr 30 04:41:16 PM PDT 24	4318064300 ps
T188	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2102011521			Apr 30 04:31:14 PM PDT 24	Apr 30 04:56:09 PM PDT 24	13709535968 ps
T195	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2187949833			Apr 30 04:36:47 PM PDT 24	Apr 30 04:45:28 PM PDT 24	4009732184 ps
T117	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.76705882			Apr 30 04:32:49 PM PDT 24	Apr 30 04:37:36 PM PDT 24	2966022855 ps
T113	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2802811061			Apr 30 04:39:18 PM PDT 24	Apr 30 05:32:43 PM PDT 24	19213305429 ps
T202	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3675667349			Apr 30 04:23:22 PM PDT 24	Apr 30 04:34:07 PM PDT 24	4629710200 ps
T423	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.412460445			Apr 30 04:27:57 PM PDT 24	Apr 30 04:32:53 PM PDT 24	3243501711 ps
T193	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933161907			Apr 30 04:47:15 PM PDT 24	Apr 30 04:53:21 PM PDT 24	3812383320 ps
T127	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2225936311			Apr 30 04:30:57 PM PDT 24	Apr 30 04:38:38 PM PDT 24	5625198080 ps
T44	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3312094190			Apr 30 04:27:24 PM PDT 24	Apr 30 04:34:30 PM PDT 24	4990631894 ps
T43	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1095966848			Apr 30 04:27:20 PM PDT 24	Apr 30 04:38:30 PM PDT 24	5971879728 ps
T150	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1632598942			Apr 30 04:37:28 PM PDT 24	Apr 30 04:48:02 PM PDT 24	4374305982 ps
T285	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.215047511			Apr 30 04:35:51 PM PDT 24	Apr 30 04:39:33 PM PDT 24	2753492092 ps
T128	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1739715257			Apr 30 04:45:49 PM PDT 24	Apr 30 04:59:57 PM PDT 24	6448808890 ps
T79	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1177754376			Apr 30 04:50:57 PM PDT 24	Apr 30 04:56:48 PM PDT 24	3605250240 ps
T93	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2362327955			Apr 30 04:23:41 PM PDT 24	Apr 30 04:27:28 PM PDT 24	3183536708 ps
T94	/workspace/coverage/default/2.chip_sw_kmac_idle.2932937536			Apr 30 04:42:29 PM PDT 24	Apr 30 04:45:42 PM PDT 24	3044583710 ps
T95	/workspace/coverage/default/53.chip_sw_all_escalation_resets.976367299			Apr 30 04:50:51 PM PDT 24	Apr 30 05:01:25 PM PDT 24	4901363730 ps
T67	/workspace/coverage/default/0.chip_tap_straps_dev.2060346556			Apr 30 04:26:52 PM PDT 24	Apr 30 04:40:41 PM PDT 24	8172141409 ps
T96	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169698929			Apr 30 04:48:31 PM PDT 24	Apr 30 04:53:27 PM PDT 24	3452719972 ps
T65	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1496050072			Apr 30 04:42:43 PM PDT 24	Apr 30 04:52:25 PM PDT 24	5451716670 ps
T60	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.518789243			Apr 30 04:22:05 PM PDT 24	Apr 30 04:23:52 PM PDT 24	2540668203 ps
T97	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2631583560			Apr 30 04:31:07 PM PDT 24	Apr 30 04:42:46 PM PDT 24	4838593636 ps
T98	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1811754533			Apr 30 04:23:51 PM PDT 24	Apr 30 04:28:22 PM PDT 24	2852991427 ps
T5	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4162210751			Apr 30 04:22:07 PM PDT 24	Apr 30 04:24:10 PM PDT 24	2598336670 ps
T636	/workspace/coverage/default/1.chip_sw_hmac_smoketest.3212216569			Apr 30 04:36:39 PM PDT 24	Apr 30 04:42:36 PM PDT 24	3771635500 ps
T6	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3174369090			Apr 30 04:37:46 PM PDT 24	Apr 30 05:55:16 PM PDT 24	47382372804 ps
T330	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2637476353			Apr 30 04:51:24 PM PDT 24	Apr 30 05:00:17 PM PDT 24	5504842390 ps
T161	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1010922343			Apr 30 04:38:56 PM PDT 24	Apr 30 04:52:14 PM PDT 24	10263416008 ps
T201	/workspace/coverage/default/1.chip_sw_pattgen_ios.711712609			Apr 30 04:31:02 PM PDT 24	Apr 30 04:34:40 PM PDT 24	2883921106 ps
T248	/workspace/coverage/default/0.chip_plic_all_irqs_0.2383208202			Apr 30 04:25:11 PM PDT 24	Apr 30 04:44:29 PM PDT 24	5974753294 ps
T300	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.485310161			Apr 30 04:48:50 PM PDT 24	Apr 30 04:55:17 PM PDT 24	3757427880 ps
T209	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2921753410			Apr 30 04:45:47 PM PDT 24	Apr 30 04:54:18 PM PDT 24	4394532244 ps
T124	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.578366949			Apr 30 04:30:58 PM PDT 24	Apr 30 04:42:12 PM PDT 24	7495778040 ps
T125	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2155592296			Apr 30 04:32:22 PM PDT 24	Apr 30 04:50:05 PM PDT 24	4685833162 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1139697186			Apr 30 04:29:58 PM PDT 24	Apr 30 05:01:32 PM PDT 24	24471899712 ps
T365	/workspace/coverage/default/0.chip_sw_example_concurrency.2331786849			Apr 30 04:23:06 PM PDT 24	Apr 30 04:28:13 PM PDT 24	3154793320 ps
T122	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3726171546			Apr 30 04:36:37 PM PDT 24	Apr 30 04:58:48 PM PDT 24	8923510168 ps
T156	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1879569327			Apr 30 04:24:30 PM PDT 24	Apr 30 04:59:52 PM PDT 24	11822410082 ps
T213	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1140033643			Apr 30 04:35:27 PM PDT 24	Apr 30 04:56:19 PM PDT 24	7200793152 ps
T366	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702372043			Apr 30 04:50:06 PM PDT 24	Apr 30 04:55:57 PM PDT 24	4066929446 ps
T66	/workspace/coverage/default/3.chip_tap_straps_rma.4027536766			Apr 30 04:43:47 PM PDT 24	Apr 30 04:49:58 PM PDT 24	4904008984 ps
T367	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.4286492912			Apr 30 04:27:49 PM PDT 24	Apr 30 04:36:56 PM PDT 24	4207089460 ps
T14	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2968416844			Apr 30 04:35:32 PM PDT 24	Apr 30 04:47:04 PM PDT 24	3762094440 ps
T502	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1260501089			Apr 30 04:44:00 PM PDT 24	Apr 30 04:48:36 PM PDT 24	3068704096 ps
T234	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3878386045			Apr 30 04:49:23 PM PDT 24	Apr 30 05:01:01 PM PDT 24	5160793590 ps
T268	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.291923653			Apr 30 04:45:10 PM PDT 24	Apr 30 04:50:36 PM PDT 24	2882709016 ps
T269	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1548049898			Apr 30 04:26:17 PM PDT 24	Apr 30 04:57:44 PM PDT 24	8639844360 ps
T114	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2496772269			Apr 30 04:27:28 PM PDT 24	Apr 30 04:41:31 PM PDT 24	5056388553 ps
T126	/workspace/coverage/default/1.chip_sw_edn_boot_mode.1007238018			Apr 30 04:32:36 PM PDT 24	Apr 30 04:41:56 PM PDT 24	3213298578 ps
T270	/workspace/coverage/default/1.chip_sw_example_concurrency.3159479239			Apr 30 04:31:12 PM PDT 24	Apr 30 04:36:38 PM PDT 24	2693767148 ps
T271	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2093906902			Apr 30 04:28:18 PM PDT 24	Apr 30 04:31:49 PM PDT 24	3152236896 ps
T272	/workspace/coverage/default/0.chip_sw_aes_enc.4191628663			Apr 30 04:23:41 PM PDT 24	Apr 30 04:27:28 PM PDT 24	2388387624 ps
T118	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2035488754			Apr 30 04:34:08 PM PDT 24	Apr 30 04:42:39 PM PDT 24	5190122330 ps
T221	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.489820381			Apr 30 04:35:06 PM PDT 24	Apr 30 04:55:39 PM PDT 24	7886262364 ps
T278	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3054980979			Apr 30 04:43:39 PM PDT 24	Apr 30 04:48:50 PM PDT 24	3074197143 ps
T279	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2761722772			Apr 30 04:49:02 PM PDT 24	Apr 30 04:57:03 PM PDT 24	5526734054 ps
T280	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1468675389			Apr 30 04:41:25 PM PDT 24	Apr 30 04:57:14 PM PDT 24	4723150856 ps
T281	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.952599092			Apr 30 04:30:59 PM PDT 24	Apr 30 04:43:10 PM PDT 24	7289450444 ps
T115	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2310588140			Apr 30 04:43:23 PM PDT 24	Apr 30 05:34:14 PM PDT 24	24851239414 ps
T282	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2046528985			Apr 30 04:38:00 PM PDT 24	Apr 30 04:45:13 PM PDT 24	5104884590 ps
T283	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2014828099			Apr 30 04:43:20 PM PDT 24	Apr 30 05:03:06 PM PDT 24	7348534802 ps
T284	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.748611673			Apr 30 04:31:02 PM PDT 24	Apr 30 04:37:09 PM PDT 24	3015494054 ps
T164	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3884941795			Apr 30 04:35:32 PM PDT 24	Apr 30 04:43:57 PM PDT 24	5758382862 ps
T121	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3371040772			Apr 30 04:31:27 PM PDT 24	Apr 30 04:41:27 PM PDT 24	3988601454 ps
T816	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3656065823			Apr 30 04:27:14 PM PDT 24	Apr 30 04:57:26 PM PDT 24	8662855480 ps
T10	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3106389213			Apr 30 04:29:45 PM PDT 24	Apr 30 04:40:39 PM PDT 24	4648084735 ps
T119	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.873913387			Apr 30 04:32:09 PM PDT 24	Apr 30 05:01:21 PM PDT 24	9815980049 ps
T626	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2856055391			Apr 30 04:49:27 PM PDT 24	Apr 30 04:55:13 PM PDT 24	3598462576 ps
T73	/workspace/coverage/default/1.chip_jtag_csr_rw.2479166247			Apr 30 04:23:38 PM PDT 24	Apr 30 04:42:37 PM PDT 24	12275467126 ps
T817	/workspace/coverage/default/1.chip_sw_example_rom.346278141			Apr 30 04:29:49 PM PDT 24	Apr 30 04:31:53 PM PDT 24	2426550982 ps
T818	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1195393512			Apr 30 04:36:15 PM PDT 24	Apr 30 04:41:01 PM PDT 24	3488595755 ps
T123	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.363298857			Apr 30 04:22:46 PM PDT 24	Apr 30 05:23:25 PM PDT 24	36385517655 ps
T235	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.189924465			Apr 30 04:25:11 PM PDT 24	Apr 30 04:32:49 PM PDT 24	3020850516 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1761908293			Apr 30 04:22:28 PM PDT 24	Apr 30 06:06:22 PM PDT 24	31227564260 ps
T246	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3503832332			Apr 30 04:32:49 PM PDT 24	Apr 30 04:37:14 PM PDT 24	2749582826 ps
T644	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3444155716			Apr 30 04:25:43 PM PDT 24	Apr 30 04:50:29 PM PDT 24	8603389680 ps
T165	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1120644399			Apr 30 04:47:54 PM PDT 24	Apr 30 05:02:45 PM PDT 24	11120783239 ps
T819	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1014017742			Apr 30 04:42:42 PM PDT 24	Apr 30 04:51:39 PM PDT 24	3765145640 ps
T7	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4283749873			Apr 30 04:21:46 PM PDT 24	Apr 30 04:27:06 PM PDT 24	3149033664 ps
T820	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3959857564			Apr 30 04:23:54 PM PDT 24	Apr 30 04:34:47 PM PDT 24	3988972274 ps
T821	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3835436721			Apr 30 04:38:35 PM PDT 24	Apr 30 05:00:56 PM PDT 24	12531881550 ps
T152	/workspace/coverage/default/2.chip_plic_all_irqs_10.1610059621			Apr 30 04:43:00 PM PDT 24	Apr 30 04:52:50 PM PDT 24	3631819522 ps
T822	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3239151630			Apr 30 04:29:39 PM PDT 24	Apr 30 05:23:50 PM PDT 24	46539405673 ps
T622	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179858814			Apr 30 04:47:45 PM PDT 24	Apr 30 04:54:45 PM PDT 24	3749341952 ps
T21	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.358393646			Apr 30 04:38:43 PM PDT 24	Apr 30 05:03:33 PM PDT 24	22033829176 ps
T823	/workspace/coverage/default/1.chip_sw_uart_smoketest.1410668550			Apr 30 04:34:44 PM PDT 24	Apr 30 04:39:35 PM PDT 24	2957962840 ps
T311	/workspace/coverage/default/2.chip_sival_flash_info_access.208151885			Apr 30 04:35:29 PM PDT 24	Apr 30 04:40:51 PM PDT 24	3106067600 ps
T824	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.173098629			Apr 30 04:35:21 PM PDT 24	Apr 30 04:39:13 PM PDT 24	2905115972 ps
T422	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2655847599			Apr 30 04:27:54 PM PDT 24	Apr 30 04:46:53 PM PDT 24	5895590100 ps
T825	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1432419920			Apr 30 04:34:45 PM PDT 24	Apr 30 04:52:30 PM PDT 24	8105098369 ps
T310	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4025506653			Apr 30 04:32:24 PM PDT 24	Apr 30 04:41:41 PM PDT 24	4074306579 ps
T345	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.809113546			Apr 30 04:34:48 PM PDT 24	Apr 30 04:41:22 PM PDT 24	3615082324 ps
T129	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1790688295			Apr 30 04:43:26 PM PDT 24	Apr 30 04:54:15 PM PDT 24	5989433290 ps
T243	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2946810924			Apr 30 04:27:59 PM PDT 24	Apr 30 04:33:24 PM PDT 24	2765968990 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.633514754			Apr 30 04:42:36 PM PDT 24	Apr 30 05:04:33 PM PDT 24	18481054352 ps
T101	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1607533976			Apr 30 04:31:02 PM PDT 24	Apr 30 04:40:18 PM PDT 24	4393947476 ps
T102	/workspace/coverage/default/1.chip_sival_flash_info_access.1500369794			Apr 30 04:31:15 PM PDT 24	Apr 30 04:36:39 PM PDT 24	2732980460 ps
T103	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3300194926			Apr 30 04:33:43 PM PDT 24	Apr 30 05:25:08 PM PDT 24	25237120580 ps
T104	/workspace/coverage/default/0.chip_sw_kmac_idle.4190525479			Apr 30 04:26:27 PM PDT 24	Apr 30 04:31:15 PM PDT 24	3708098520 ps
T80	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2617262516			Apr 30 04:46:10 PM PDT 24	Apr 30 04:53:33 PM PDT 24	4032987560 ps
T105	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.349358380			Apr 30 04:48:29 PM PDT 24	Apr 30 04:54:10 PM PDT 24	3603219384 ps
T106	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3202476057			Apr 30 04:50:23 PM PDT 24	Apr 30 04:56:54 PM PDT 24	3371225878 ps
T107	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3009177425			Apr 30 04:40:18 PM PDT 24	Apr 30 05:07:05 PM PDT 24	9387918944 ps
T108	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2635613253			Apr 30 04:33:12 PM PDT 24	Apr 30 04:40:53 PM PDT 24	2785987736 ps
T333	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1327081377			Apr 30 04:26:14 PM PDT 24	Apr 30 04:38:48 PM PDT 24	5559345900 ps
T826	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1249701767			Apr 30 04:45:41 PM PDT 24	Apr 30 05:32:37 PM PDT 24	16947141052 ps
T214	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3796933037			Apr 30 04:23:37 PM PDT 24	Apr 30 04:53:50 PM PDT 24	9609283880 ps
T335	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3111014373			Apr 30 04:23:28 PM PDT 24	Apr 30 04:46:48 PM PDT 24	9804313686 ps
T621	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3322504780			Apr 30 04:48:12 PM PDT 24	Apr 30 04:55:22 PM PDT 24	3392643040 ps
T620	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320664259			Apr 30 04:49:18 PM PDT 24	Apr 30 04:54:37 PM PDT 24	3164031082 ps
T140	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.621382690			Apr 30 04:25:45 PM PDT 24	Apr 30 04:29:18 PM PDT 24	2790567383 ps
T110	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3061652748			Apr 30 04:33:40 PM PDT 24	Apr 30 05:21:39 PM PDT 24	15624415597 ps
T198	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2710894202			Apr 30 04:23:21 PM PDT 24	Apr 30 04:35:32 PM PDT 24	4870465483 ps
T130	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1609753569			Apr 30 04:26:20 PM PDT 24	Apr 30 04:33:06 PM PDT 24	6026215060 ps
T39	/workspace/coverage/default/0.chip_sw_spi_device_tpm.1245020004			Apr 30 04:22:18 PM PDT 24	Apr 30 04:27:41 PM PDT 24	3547794428 ps
T499	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3909197617			Apr 30 04:49:11 PM PDT 24	Apr 30 05:00:29 PM PDT 24	5351433700 ps
T827	/workspace/coverage/default/1.chip_sw_example_flash.706205165			Apr 30 04:28:33 PM PDT 24	Apr 30 04:32:44 PM PDT 24	2317211422 ps
T828	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4023523150			Apr 30 04:24:24 PM PDT 24	Apr 30 04:31:16 PM PDT 24	3240248412 ps
T501	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3956195159			Apr 30 04:48:54 PM PDT 24	Apr 30 04:57:09 PM PDT 24	5505641200 ps
T131	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2214734841			Apr 30 04:24:59 PM PDT 24	Apr 30 04:31:53 PM PDT 24	4636788680 ps
T829	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.687396683			Apr 30 04:46:31 PM PDT 24	Apr 30 04:52:46 PM PDT 24	5717389543 ps
T203	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2571540674			Apr 30 04:23:44 PM PDT 24	Apr 30 04:46:22 PM PDT 24	8931493360 ps
T830	/workspace/coverage/default/2.chip_sw_otbn_randomness.2275843927			Apr 30 04:39:02 PM PDT 24	Apr 30 04:53:32 PM PDT 24	5801033952 ps
T831	/workspace/coverage/default/2.chip_sw_uart_tx_rx.326001745			Apr 30 04:35:32 PM PDT 24	Apr 30 04:47:08 PM PDT 24	4409830904 ps
T45	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1976429066			Apr 30 04:33:20 PM PDT 24	Apr 30 05:00:51 PM PDT 24	20845308532 ps
T832	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1445481089			Apr 30 04:40:41 PM PDT 24	Apr 30 04:45:27 PM PDT 24	3500320880 ps
T623	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3150752382			Apr 30 04:49:10 PM PDT 24	Apr 30 04:59:29 PM PDT 24	5627381070 ps
T833	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.394031945			Apr 30 04:31:18 PM PDT 24	Apr 30 04:42:45 PM PDT 24	5648238318 ps
T141	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2883965246			Apr 30 04:37:24 PM PDT 24	Apr 30 04:44:12 PM PDT 24	6301353730 ps
T834	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3937113438			Apr 30 04:33:07 PM PDT 24	Apr 30 04:40:31 PM PDT 24	5493225720 ps
T264	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4272166202			Apr 30 04:31:28 PM PDT 24	Apr 30 04:39:48 PM PDT 24	8863174495 ps
T318	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3623473210			Apr 30 04:36:34 PM PDT 24	Apr 30 04:47:22 PM PDT 24	4454226596 ps
T306	/workspace/coverage/default/0.chip_plic_all_irqs_20.910841988			Apr 30 04:27:49 PM PDT 24	Apr 30 04:43:11 PM PDT 24	4628766340 ps
T210	/workspace/coverage/default/2.chip_tap_straps_prod.533959812			Apr 30 04:41:50 PM PDT 24	Apr 30 04:44:40 PM PDT 24	3164691101 ps
T199	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1628859519			Apr 30 04:38:09 PM PDT 24	Apr 30 04:42:26 PM PDT 24	3017784810 ps
T835	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2619792400			Apr 30 04:42:18 PM PDT 24	Apr 30 04:53:15 PM PDT 24	4512025420 ps
T173	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2507584296			Apr 30 04:31:09 PM PDT 24	Apr 30 04:47:04 PM PDT 24	8628340643 ps
T166	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3297156321			Apr 30 04:48:08 PM PDT 24	Apr 30 05:03:38 PM PDT 24	10671356977 ps
T294	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2917600879			Apr 30 04:23:28 PM PDT 24	Apr 30 05:04:25 PM PDT 24	11362838360 ps
T295	/workspace/coverage/default/0.chip_sw_all_escalation_resets.6804397			Apr 30 04:21:21 PM PDT 24	Apr 30 04:30:51 PM PDT 24	4073303086 ps
T296	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3275516883			Apr 30 04:50:14 PM PDT 24	Apr 30 04:56:30 PM PDT 24	3404470776 ps
T297	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3351902995			Apr 30 04:29:39 PM PDT 24	Apr 30 04:33:14 PM PDT 24	3115373558 ps
T265	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1696943017			Apr 30 04:23:29 PM PDT 24	Apr 30 04:30:44 PM PDT 24	9554349090 ps
T298	/workspace/coverage/default/2.chip_sw_edn_kat.1011272350			Apr 30 04:40:19 PM PDT 24	Apr 30 04:50:03 PM PDT 24	3625057704 ps
T196	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3680431068			Apr 30 04:47:55 PM PDT 24	Apr 30 05:07:52 PM PDT 24	7959997086 ps
T299	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1251599734			Apr 30 04:31:50 PM PDT 24	Apr 30 04:49:27 PM PDT 24	5600437030 ps
T836	/workspace/coverage/default/0.chip_sw_aes_smoketest.1650975179			Apr 30 04:33:18 PM PDT 24	Apr 30 04:37:22 PM PDT 24	2683983736 ps
T215	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.882634550			Apr 30 04:23:47 PM PDT 24	Apr 30 04:54:39 PM PDT 24	8609445904 ps
T55	/workspace/coverage/default/1.chip_sw_alert_test.61379084			Apr 30 04:32:17 PM PDT 24	Apr 30 04:37:25 PM PDT 24	3002931540 ps
T604	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.321220501			Apr 30 04:48:43 PM PDT 24	Apr 30 04:56:05 PM PDT 24	3604878416 ps
T837	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3641807383			Apr 30 04:23:56 PM PDT 24	Apr 30 04:27:03 PM PDT 24	2054716280 ps
T722	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1431675841			Apr 30 04:49:30 PM PDT 24	Apr 30 05:00:41 PM PDT 24	4882626052 ps
T157	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1818692921			Apr 30 04:25:55 PM PDT 24	Apr 30 07:31:55 PM PDT 24	255077604520 ps
T424	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3020460569			Apr 30 04:30:10 PM PDT 24	Apr 30 04:42:26 PM PDT 24	4817707881 ps
T624	/workspace/coverage/default/9.chip_sw_all_escalation_resets.2613975732			Apr 30 04:45:23 PM PDT 24	Apr 30 04:55:04 PM PDT 24	5197504984 ps
T838	/workspace/coverage/default/1.chip_tap_straps_prod.705339084			Apr 30 04:33:56 PM PDT 24	Apr 30 05:05:46 PM PDT 24	16806452366 ps
T351	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2493979843			Apr 30 04:25:18 PM PDT 24	Apr 30 04:28:45 PM PDT 24	2560405606 ps
T74	/workspace/coverage/default/2.chip_jtag_mem_access.1919109120			Apr 30 04:35:02 PM PDT 24	Apr 30 04:59:03 PM PDT 24	13466366568 ps
T111	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3397873479			Apr 30 04:31:29 PM PDT 24	Apr 30 05:12:16 PM PDT 24	15111400452 ps
T56	/workspace/coverage/default/0.chip_sw_alert_test.164665632			Apr 30 04:24:43 PM PDT 24	Apr 30 04:30:26 PM PDT 24	3474966970 ps
T669	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.937418503			Apr 30 04:46:12 PM PDT 24	Apr 30 04:53:38 PM PDT 24	3805734286 ps
T839	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3868587100			Apr 30 04:46:48 PM PDT 24	Apr 30 04:52:45 PM PDT 24	6077671292 ps
T239	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1297069141			Apr 30 04:47:55 PM PDT 24	Apr 30 04:55:05 PM PDT 24	3593562358 ps
T840	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1000407736			Apr 30 04:22:47 PM PDT 24	Apr 30 04:28:55 PM PDT 24	3703390200 ps
T142	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3531551834			Apr 30 04:41:45 PM PDT 24	Apr 30 04:45:56 PM PDT 24	3089871785 ps
T683	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2733063386			Apr 30 04:52:25 PM PDT 24	Apr 30 05:00:25 PM PDT 24	5218348040 ps
T62	/workspace/coverage/default/1.chip_tap_straps_rma.2609843240			Apr 30 04:34:00 PM PDT 24	Apr 30 04:42:01 PM PDT 24	5129359106 ps
T307	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1658005457			Apr 30 04:43:36 PM PDT 24	Apr 30 04:55:33 PM PDT 24	3974847200 ps
T841	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3085905751			Apr 30 04:23:30 PM PDT 24	Apr 30 04:43:47 PM PDT 24	9033134808 ps
T842	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.647367433			Apr 30 04:30:49 PM PDT 24	Apr 30 04:40:36 PM PDT 24	7308616502 ps
T625	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3717543708			Apr 30 04:46:13 PM PDT 24	Apr 30 04:53:20 PM PDT 24	3232082184 ps
T843	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.753723019			Apr 30 04:22:49 PM PDT 24	Apr 30 04:34:49 PM PDT 24	7776829419 ps
T844	/workspace/coverage/default/2.chip_sw_example_concurrency.1626723015			Apr 30 04:34:50 PM PDT 24	Apr 30 04:38:19 PM PDT 24	2537188896 ps
T155	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.814196612			Apr 30 04:23:35 PM PDT 24	Apr 30 04:32:28 PM PDT 24	4380719044 ps
T266	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4213286794			Apr 30 04:40:43 PM PDT 24	Apr 30 04:48:08 PM PDT 24	9546494556 ps
T845	/workspace/coverage/default/2.chip_sw_aes_smoketest.4088037878			Apr 30 04:45:00 PM PDT 24	Apr 30 04:49:31 PM PDT 24	2826784652 ps
T723	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904469327			Apr 30 04:51:19 PM PDT 24	Apr 30 04:56:33 PM PDT 24	3337591808 ps
T846	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3662079393			Apr 30 04:32:50 PM PDT 24	Apr 30 04:39:22 PM PDT 24	5113541520 ps
T314	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3530551865			Apr 30 04:32:05 PM PDT 24	Apr 30 04:50:10 PM PDT 24	6289191152 ps
T40	/workspace/coverage/default/1.chip_sw_spi_device_tpm.286174270			Apr 30 04:29:53 PM PDT 24	Apr 30 04:35:58 PM PDT 24	3026393647 ps
T11	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1351870748			Apr 30 04:22:06 PM PDT 24	Apr 30 04:35:29 PM PDT 24	6999195304 ps
T153	/workspace/coverage/default/1.chip_plic_all_irqs_10.2074967571			Apr 30 04:32:24 PM PDT 24	Apr 30 04:42:36 PM PDT 24	3545023052 ps
T847	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1141789735			Apr 30 04:30:40 PM PDT 24	Apr 30 04:44:00 PM PDT 24	8444957444 ps
T86	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3688886215			Apr 30 04:50:06 PM PDT 24	Apr 30 04:58:23 PM PDT 24	5982190584 ps
T848	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1182237792			Apr 30 04:26:24 PM PDT 24	Apr 30 04:45:55 PM PDT 24	8416204398 ps
T849	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.563225378			Apr 30 04:25:45 PM PDT 24	Apr 30 04:34:28 PM PDT 24	4196522440 ps
T850	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1160489440			Apr 30 04:25:58 PM PDT 24	Apr 30 04:34:41 PM PDT 24	4479541648 ps
T851	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1539622592			Apr 30 04:32:52 PM PDT 24	Apr 30 04:37:26 PM PDT 24	3036083888 ps
T852	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2357601551			Apr 30 04:29:38 PM PDT 24	Apr 30 04:40:19 PM PDT 24	6908951767 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.691131187			Apr 30 04:25:28 PM PDT 24	Apr 30 04:31:32 PM PDT 24	3370998891 ps
T224	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2079140957			Apr 30 04:38:18 PM PDT 24	Apr 30 06:04:37 PM PDT 24	46861256350 ps
T216	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4250544465			Apr 30 04:33:52 PM PDT 24	Apr 30 05:35:06 PM PDT 24	16904765160 ps
T853	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.324487685			Apr 30 04:30:23 PM PDT 24	Apr 30 04:45:33 PM PDT 24	9738180668 ps
T854	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3961217775			Apr 30 04:34:38 PM PDT 24	Apr 30 04:38:40 PM PDT 24	2783223488 ps
T236	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2236746745			Apr 30 04:48:53 PM PDT 24	Apr 30 04:59:12 PM PDT 24	5867333774 ps
T109	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2286674083			Apr 30 04:45:21 PM PDT 24	Apr 30 04:55:45 PM PDT 24	18847202100 ps
T256	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3906818975			Apr 30 04:47:05 PM PDT 24	Apr 30 04:56:19 PM PDT 24	6577736900 ps
T257	/workspace/coverage/default/1.chip_sw_all_escalation_resets.251858519			Apr 30 04:33:31 PM PDT 24	Apr 30 04:47:21 PM PDT 24	5051664920 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2584366767			Apr 30 04:37:43 PM PDT 24	Apr 30 04:49:43 PM PDT 24	6495886812 ps
T258	/workspace/coverage/default/0.chip_sw_edn_kat.2072070381			Apr 30 04:24:32 PM PDT 24	Apr 30 04:35:28 PM PDT 24	3357396260 ps
T163	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.819936043			Apr 30 04:35:37 PM PDT 24	Apr 30 05:48:56 PM PDT 24	43265377624 ps
T259	/workspace/coverage/default/0.chip_sw_aon_timer_irq.369268206			Apr 30 04:23:42 PM PDT 24	Apr 30 04:29:44 PM PDT 24	3361327118 ps
T260	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3937171955			Apr 30 04:48:04 PM PDT 24	Apr 30 04:59:47 PM PDT 24	6007429610 ps
T63	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1953682104			Apr 30 04:31:13 PM PDT 24	Apr 30 04:50:54 PM PDT 24	10200717341 ps
T15	/workspace/coverage/default/2.chip_sw_gpio.4166410901			Apr 30 04:36:10 PM PDT 24	Apr 30 04:43:43 PM PDT 24	3794814217 ps
T685	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931584748			Apr 30 04:50:06 PM PDT 24	Apr 30 04:57:22 PM PDT 24	3532251920 ps
T714	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4130825414			Apr 30 04:53:41 PM PDT 24	Apr 30 05:00:12 PM PDT 24	3360257864 ps
T303	/workspace/coverage/default/1.chip_plic_all_irqs_0.1476622407			Apr 30 04:31:41 PM PDT 24	Apr 30 04:51:22 PM PDT 24	5991244188 ps
T724	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2612315733			Apr 30 04:50:32 PM PDT 24	Apr 30 04:58:46 PM PDT 24	4812032480 ps
T33	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2617470063			Apr 30 04:25:04 PM PDT 24	Apr 30 04:29:20 PM PDT 24	2147581006 ps
T855	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.761360262			Apr 30 04:33:50 PM PDT 24	Apr 30 04:43:07 PM PDT 24	4178391264 ps
T856	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2432144481			Apr 30 04:34:34 PM PDT 24	Apr 30 04:40:06 PM PDT 24	4596781300 ps
T857	/workspace/coverage/default/0.chip_sw_example_rom.2336595748			Apr 30 04:20:53 PM PDT 24	Apr 30 04:22:41 PM PDT 24	2855112568 ps
T308	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.795260011			Apr 30 04:28:37 PM PDT 24	Apr 30 04:37:35 PM PDT 24	4576229269 ps
T36	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2955610613			Apr 30 04:31:13 PM PDT 24	Apr 30 04:37:51 PM PDT 24	4718169244 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3430086277			Apr 30 04:22:40 PM PDT 24	Apr 30 04:52:11 PM PDT 24	8008895890 ps
T858	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3396467792			Apr 30 04:45:55 PM PDT 24	Apr 30 04:55:11 PM PDT 24	6893389779 ps
T859	/workspace/coverage/default/1.chip_sw_rv_timer_irq.931939517			Apr 30 04:30:15 PM PDT 24	Apr 30 04:35:47 PM PDT 24	3277745816 ps
T860	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3173864010			Apr 30 04:32:33 PM PDT 24	Apr 30 04:37:41 PM PDT 24	3321883034 ps
T46	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1925560655			Apr 30 04:30:20 PM PDT 24	Apr 30 04:34:32 PM PDT 24	3929660900 ps
T400	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3237566130			Apr 30 04:47:21 PM PDT 24	Apr 30 04:58:29 PM PDT 24	6421337058 ps
T336	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2785154620			Apr 30 04:31:22 PM PDT 24	Apr 30 04:38:17 PM PDT 24	4060598160 ps
T401	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1609169912			Apr 30 04:43:57 PM PDT 24	Apr 30 04:48:13 PM PDT 24	2537003540 ps
T402	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2653765682			Apr 30 04:42:01 PM PDT 24	Apr 30 05:11:03 PM PDT 24	24911335380 ps
T180	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3035017389			Apr 30 04:23:15 PM PDT 24	Apr 30 04:34:00 PM PDT 24	6313016831 ps