Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159713	1			T70	25		T72	5		T78	13
values[2]	4576	1			T498	1		T386	15		T506	1
values[3]	2131	1			T498	1		T386	6		T745	1
values[4]	1604	1			T498	1		T386	12		T745	1
values[5]	1324	1			T498	1		T386	2		T745	1
values[6]	1095	1			T498	1		T386	9		T745	1
values[7]	1039	1			T498	1		T386	10		T745	1
values[8]	881	1			T498	1		T386	9		T745	1
values[9]	711	1			T498	1		T386	7		T745	1
values[10]	698	1			T498	1		T386	6		T745	1
values[11]	622	1			T498	1		T386	5		T745	1
values[12]	483	1			T498	1		T386	8		T745	1
values[13]	377	1			T498	1		T386	1		T745	1
values[14]	276	1			T498	1		T386	4		T745	1
values[15]	251	1			T498	1		T386	6		T745	1
values[16]	234	1			T498	1		T386	15		T745	1
values[17]	204	1			T498	1		T386	8		T745	1
values[18]	190	1			T498	1		T386	7		T745	1
values[19]	190	1			T498	1		T386	2		T745	1
values[20]	159	1			T498	1		T386	4		T745	1
values[21]	167	1			T498	1		T386	6		T745	1
values[22]	218	1			T498	1		T386	12		T745	1
values[23]	217	1			T498	1		T386	13		T745	2
values[24]	162	1			T498	1		T386	7		T745	1
values[25]	159	1			T498	1		T386	2		T745	1
values[26]	190	1			T498	1		T386	3		T745	1
values[27]	213	1			T498	2		T386	13		T745	1
values[28]	225	1			T498	1		T386	8		T745	1
values[29]	201	1			T498	1		T386	10		T745	1
values[30]	174	1			T498	1		T386	9		T745	1
values[31]	139	1			T498	1		T386	4		T745	1
values[32]	130	1			T498	1		T386	5		T745	1
values[33]	110	1			T498	1		T386	8		T745	1
values[34]	81	1			T498	1		T386	3		T745	1
values[35]	101	1			T498	1		T745	1		T430	1
values[36]	121	1			T498	1		T745	1		T430	1
values[37]	111	1			T498	1		T745	1		T430	1
values[38]	104	1			T498	1		T745	1		T430	1
values[39]	105	1			T498	1		T745	1		T430	1
values[40]	82	1			T498	1		T745	1		T430	1
values[41]	98	1			T498	1		T745	1		T430	1
values[42]	88	1			T498	1		T745	1		T430	1
values[43]	76	1			T498	1		T745	1		T430	1
values[44]	77	1			T498	1		T745	1		T430	1
values[45]	65	1			T498	1		T745	1		T430	1
values[46]	71	1			T498	1		T745	1		T430	1
values[47]	73	1			T498	1		T745	1		T430	1
values[48]	78	1			T498	1		T745	1		T430	1
values[49]	73	1			T498	1		T745	1		T430	1
values[50]	69	1			T498	1		T745	1		T430	2
values[51]	63	1			T498	1		T745	1		T430	1
values[52]	61	1			T498	1		T745	1		T430	1
values[53]	59	1			T498	1		T745	1		T430	1
values[54]	53	1			T498	1		T745	1		T430	1
values[55]	54	1			T498	1		T745	1		T430	1
values[56]	60	1			T498	1		T745	1		T430	1
values[57]	47	1			T498	1		T745	1		T430	1
values[58]	48	1			T498	1		T745	1		T430	1
values[59]	54	1			T498	1		T745	1		T430	1
values[60]	65	1			T498	1		T745	1		T430	1
values[61]	75	1			T498	1		T745	1		T430	1
values[62]	59	1			T498	1		T745	1		T430	1
values[63]	53	1			T498	1		T745	1		T430	1
values[64]	49	1			T498	1		T745	1		T430	1
values[65]	49	1			T498	1		T745	2		T430	1
values[66]	55	1			T498	1		T745	1		T430	1
values[67]	73	1			T498	1		T745	1		T430	1
values[68]	66	1			T498	1		T745	1		T430	1
values[69]	57	1			T498	1		T745	1		T430	2
values[70]	62	1			T498	1		T745	1		T430	1
values[71]	70	1			T498	1		T745	1		T430	1
values[72]	55	1			T498	1		T745	1		T430	1
values[73]	61	1			T498	1		T745	1		T430	1
values[74]	59	1			T498	1		T745	1		T430	1
values[75]	66	1			T498	1		T745	1		T430	1
values[76]	65	1			T498	1		T745	1		T430	1
values[77]	61	1			T498	1		T745	1		T430	1
values[78]	57	1			T498	1		T745	1		T430	1
values[79]	56	1			T498	1		T745	1		T430	1
values[80]	51	1			T498	1		T745	1		T430	1
values[81]	60	1			T498	1		T745	1		T430	1
values[82]	46	1			T498	1		T745	1		T430	1
values[83]	59	1			T498	1		T745	1		T430	1
values[84]	61	1			T498	1		T745	1		T430	1
values[85]	55	1			T498	1		T745	1		T430	1
values[86]	61	1			T498	1		T745	1		T430	1
values[87]	49	1			T498	1		T745	1		T430	1
values[88]	51	1			T498	1		T745	1		T430	1
values[89]	62	1			T498	1		T745	1		T430	1
values[90]	61	1			T498	1		T745	1		T430	1
values[91]	76	1			T498	1		T745	1		T430	1
values[92]	56	1			T498	1		T745	1		T430	1
values[93]	55	1			T498	1		T745	1		T430	1
values[94]	50	1			T498	1		T745	1		T430	1
values[95]	64	1			T498	1		T745	1		T430	1
values[96]	64	1			T498	1		T745	1		T430	1
values[97]	82	1			T498	1		T745	1		T430	1
values[98]	93	1			T498	1		T745	1		T430	1
values[99]	77	1			T498	1		T745	1		T430	1
values[100]	65	1			T498	1		T745	1		T430	1
values[101]	70	1			T498	1		T745	1		T430	1
values[102]	64	1			T498	1		T745	1		T430	1
values[103]	70	1			T498	1		T745	1		T430	1
values[104]	62	1			T498	1		T745	1		T430	1
values[105]	71	1			T498	1		T745	1		T430	1
values[106]	71	1			T498	1		T745	1		T430	1
values[107]	72	1			T498	1		T745	1		T430	1
values[108]	89	1			T498	1		T745	1		T430	1
values[109]	87	1			T498	1		T745	1		T430	1
values[110]	67	1			T498	1		T745	1		T430	1
values[111]	78	1			T498	1		T745	1		T430	1
values[112]	79	1			T498	1		T745	1		T430	1
values[113]	83	1			T498	1		T745	1		T430	1
values[114]	84	1			T498	1		T745	1		T430	1
values[115]	82	1			T498	1		T745	1		T430	1
values[116]	68	1			T498	1		T745	1		T430	1
values[117]	66	1			T498	1		T745	1		T430	2
values[118]	83	1			T498	1		T745	1		T430	5
values[119]	82	1			T498	1		T745	1		T430	9
values[120]	74	1			T498	1		T745	1		T430	2
values[121]	87	1			T498	1		T745	1		T430	3
values[122]	110	1			T498	1		T745	1		T430	1
values[123]	132	1			T498	1		T745	1		T430	1
values[124]	211	1			T498	2		T745	1		T430	1
values[125]	325	1			T498	2		T745	2		T430	1
values[126]	610	1			T498	18		T745	10		T430	6
values[127]	2603	1			T498	156		T745	108		T430	85
values[128]	4649	1			T498	249		T745	249		T430	202