Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141128	1			T70	24		T71	1		T72	8
values[2]	9052	1			T71	1		T72	1		T429	61
values[3]	3019	1			T71	1		T429	45		T662	1
values[4]	1840	1			T71	1		T429	37		T662	1
values[5]	1200	1			T71	1		T429	27		T662	1
values[6]	889	1			T71	1		T429	16		T662	1
values[7]	791	1			T71	1		T429	16		T662	1
values[8]	563	1			T71	1		T429	17		T662	1
values[9]	489	1			T71	1		T429	11		T662	1
values[10]	462	1			T71	1		T429	3		T662	1
values[11]	466	1			T71	1		T429	8		T662	1
values[12]	369	1			T71	1		T429	1		T662	1
values[13]	382	1			T71	1		T429	1		T662	1
values[14]	381	1			T71	1		T429	1		T662	1
values[15]	363	1			T71	1		T662	1		T508	4
values[16]	330	1			T71	1		T662	1		T508	4
values[17]	357	1			T71	1		T662	1		T508	7
values[18]	303	1			T71	1		T662	1		T508	3
values[19]	375	1			T71	1		T662	1		T508	9
values[20]	345	1			T71	1		T662	1		T508	18
values[21]	329	1			T71	1		T662	1		T508	6
values[22]	385	1			T71	1		T662	1		T508	4
values[23]	357	1			T71	1		T662	1		T508	6
values[24]	334	1			T71	1		T662	1		T508	13
values[25]	336	1			T71	1		T662	1		T508	9
values[26]	358	1			T71	1		T662	1		T508	6
values[27]	326	1			T71	1		T662	1		T508	3
values[28]	339	1			T71	1		T662	1		T508	7
values[29]	329	1			T71	1		T662	1		T508	4
values[30]	314	1			T71	1		T662	1		T508	20
values[31]	307	1			T71	1		T662	1		T508	4
values[32]	339	1			T71	1		T662	1		T508	5
values[33]	308	1			T71	1		T662	1		T508	10
values[34]	356	1			T71	1		T662	1		T508	4
values[35]	337	1			T71	1		T662	1		T508	5
values[36]	331	1			T71	1		T662	1		T508	3
values[37]	319	1			T71	1		T662	1		T508	10
values[38]	370	1			T71	1		T662	1		T508	5
values[39]	343	1			T71	1		T662	1		T508	10
values[40]	363	1			T71	1		T662	1		T508	13
values[41]	307	1			T71	1		T662	1		T508	5
values[42]	311	1			T71	1		T662	1		T508	4
values[43]	337	1			T71	1		T662	1		T508	15
values[44]	332	1			T71	1		T662	1		T508	6
values[45]	369	1			T71	1		T662	1		T508	7
values[46]	315	1			T71	1		T662	1		T508	3
values[47]	282	1			T71	1		T662	1		T508	9
values[48]	308	1			T71	1		T662	1		T508	7
values[49]	303	1			T71	1		T662	1		T508	6
values[50]	267	1			T71	1		T662	1		T508	6
values[51]	291	1			T71	1		T662	1		T508	4
values[52]	282	1			T71	1		T662	1		T508	9
values[53]	278	1			T71	1		T662	1		T508	5
values[54]	254	1			T71	1		T662	1		T508	5
values[55]	255	1			T71	1		T662	1		T508	7
values[56]	312	1			T71	1		T662	1		T508	6
values[57]	243	1			T71	1		T662	1		T508	11
values[58]	248	1			T71	1		T662	1		T508	3
values[59]	241	1			T71	1		T662	1		T508	6
values[60]	257	1			T71	1		T662	1		T508	10
values[61]	229	1			T71	1		T662	1		T508	6
values[62]	194	1			T71	1		T662	1		T508	5
values[63]	211	1			T71	1		T662	1		T508	9
values[64]	248	1			T71	1		T662	1		T508	7
values[65]	214	1			T71	1		T662	1		T508	7
values[66]	189	1			T71	1		T662	1		T508	13
values[67]	143	1			T71	2		T662	1		T508	10
values[68]	139	1			T71	1		T662	1		T508	7
values[69]	141	1			T71	1		T662	1		T508	1
values[70]	121	1			T71	1		T662	1		T431	17
values[71]	130	1			T71	1		T662	1		T431	9
values[72]	105	1			T71	1		T662	1		T431	18
values[73]	81	1			T71	1		T662	1		T431	14
values[74]	75	1			T71	1		T662	1		T431	12
values[75]	97	1			T71	1		T662	1		T431	9
values[76]	93	1			T71	1		T662	1		T431	7
values[77]	74	1			T71	1		T662	1		T431	4
values[78]	72	1			T71	1		T662	1		T431	6
values[79]	83	1			T71	1		T662	1		T431	7
values[80]	83	1			T71	1		T662	1		T431	6
values[81]	68	1			T71	1		T662	1		T431	5
values[82]	52	1			T71	1		T662	1		T431	1
values[83]	77	1			T71	1		T662	1		T431	1
values[84]	70	1			T71	1		T662	1		T431	4
values[85]	56	1			T71	1		T662	1		T431	2
values[86]	76	1			T71	1		T662	1		T431	4
values[87]	72	1			T71	2		T662	1		T431	6
values[88]	74	1			T71	5		T662	2		T431	5
values[89]	71	1			T71	6		T662	1		T431	6
values[90]	76	1			T71	2		T662	3		T431	3
values[91]	66	1			T71	1		T662	1		T431	1
values[92]	65	1			T71	8		T662	1		T431	4
values[93]	74	1			T71	4		T662	3		T431	9
values[94]	76	1			T71	5		T662	6		T431	9
values[95]	75	1			T71	9		T662	1		T431	5
values[96]	69	1			T71	3		T662	1		T431	3
values[97]	67	1			T71	4		T662	1		T431	5
values[98]	70	1			T71	1		T662	5		T431	1
values[99]	89	1			T71	4		T662	2		T431	6
values[100]	81	1			T71	4		T662	1		T431	7
values[101]	85	1			T71	2		T662	4		T431	6
values[102]	72	1			T71	2		T662	2		T431	5
values[103]	62	1			T71	1		T662	1		T431	3
values[104]	65	1			T71	4		T662	1		T431	3
values[105]	70	1			T71	3		T662	4		T431	3
values[106]	73	1			T71	2		T662	1		T431	5
values[107]	66	1			T71	2		T662	2		T431	4
values[108]	67	1			T71	2		T662	2		T431	4
values[109]	58	1			T71	3		T662	1		T431	3
values[110]	68	1			T71	2		T662	4		T431	8
values[111]	60	1			T71	2		T662	1		T431	7
values[112]	59	1			T71	1		T662	3		T431	2
values[113]	78	1			T71	2		T662	2		T431	3
values[114]	69	1			T71	6		T662	2		T431	1
values[115]	65	1			T71	2		T662	1		T431	1
values[116]	75	1			T71	6		T662	1		T431	2
values[117]	71	1			T71	3		T662	2		T431	7
values[118]	65	1			T71	1		T662	6		T431	8
values[119]	59	1			T71	3		T662	1		T431	5
values[120]	68	1			T71	2		T662	4		T431	2
values[121]	62	1			T71	3		T662	1		T755	9
values[122]	65	1			T71	1		T662	1		T755	6
values[123]	64	1			T71	1		T662	1		T755	4
values[124]	74	1			T71	1		T662	3		T755	3
values[125]	86	1			T71	2		T662	2		T755	5
values[126]	104	1			T71	2		T662	2		T755	9
values[127]	878	1			T71	24		T662	27		T755	87
values[128]	8140	1			T71	257		T662	338		T755	741