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Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0

Go back
Group Instances:
tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125925 1 T70 14 T72 3 T78 22
auto[1] 64577 1 T70 7 T78 1 T77 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 48138 1 T70 6 T72 1 T78 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 133831 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 56671 1 T70 7 T72 1 T78 4



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 14830 1 T70 3 T77 16 T497 6


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121635 1 T70 18 T72 2 T78 9
auto[1] 62634 1 T70 6 T72 5 T78 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 46679 1 T70 10 T72 5 T78 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 129419 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 54850 1 T70 11 T78 5 T76 1



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 14523 1 T70 5 T78 2 T76 1


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125979 1 T70 23 T71 358 T72 9
auto[1] 64478 1 T70 1 T71 129 T76 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 48465 1 T70 8 T71 170 T72 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 134108 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 56349 1 T70 8 T71 141 T72 4



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15080 1 T70 3 T71 51 T72 1


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 126146 1 T70 28 T71 359 T72 1
auto[1] 68301 1 T70 4 T71 634 T72 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 49594 1 T70 13 T71 325 T72 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136501 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 57946 1 T70 11 T71 314 T72 1



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15455 1 T70 6 T71 97 T77 16


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120716 1 T70 16 T72 2 T78 9
auto[1] 70352 1 T70 15 T72 1 T78 13



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 49797 1 T70 15 T72 3 T78 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 132595 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 58473 1 T70 12 T78 5 T76 3



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15793 1 T70 5 T78 1 T76 1

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