Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	478	1			T241	1		T389	1		T429	2
all_values[1]	465	1			T498	1		T429	2		T505	3
all_values[2]	464	1			T429	1		T505	3		T503	1
all_values[3]	487	1			T71	1		T429	6		T505	1
all_values[4]	468	1			T71	1		T389	1		T429	2
all_values[5]	426	1			T429	2		T505	1		T408	1
all_values[6]	479	1			T429	2		T505	3		T408	1
all_values[7]	472	1			T77	1		T429	2		T503	2
all_values[8]	503	1			T71	1		T429	3		T505	2
all_values[9]	469	1			T429	2		T505	1		T386	1
all_values[10]	494	1			T77	1		T241	1		T429	1
all_values[11]	466	1			T71	1		T77	1		T664	1
all_values[12]	430	1			T151	1		T77	1		T429	3
all_values[13]	463	1			T429	2		T503	1		T745	1
all_values[14]	475	1			T71	1		T429	4		T505	3
all_values[15]	452	1			T429	5		T505	3		T745	2
all_values[16]	477	1			T429	4		T505	4		T745	1
all_values[17]	493	1			T71	1		T77	1		T498	1
all_values[18]	450	1			T71	1		T389	1		T429	4
all_values[19]	465	1			T241	1		T389	1		T429	3
all_values[20]	473	1			T241	1		T429	5		T505	6
all_values[21]	442	1			T498	1		T429	4		T505	2
all_values[22]	425	1			T429	4		T510	4		T508	1
all_values[23]	470	1			T429	4		T505	4		T386	1
all_values[24]	507	1			T77	1		T429	5		T505	1
all_values[25]	465	1			T71	1		T429	4		T662	1
all_values[26]	496	1			T71	2		T498	1		T429	4
all_values[27]	473	1			T241	1		T389	1		T429	2
all_values[28]	461	1			T429	1		T505	2		T508	2
all_values[29]	479	1			T429	3		T505	2		T386	1
all_values[30]	467	1			T77	1		T389	1		T429	2
all_values[31]	459	1			T77	1		T498	1		T429	1
all_values[32]	475	1			T241	1		T389	1		T429	3
all_values[33]	455	1			T77	1		T498	1		T429	4
all_values[34]	482	1			T429	4		T505	2		T503	1
all_values[35]	471	1			T241	1		T429	4		T505	3
all_values[36]	475	1			T71	1		T241	1		T389	1
all_values[37]	441	1			T71	1		T429	6		T505	6
all_values[38]	448	1			T389	1		T429	2		T505	5
all_values[39]	466	1			T71	2		T429	1		T505	4
all_values[40]	458	1			T151	1		T77	1		T429	4
all_values[41]	461	1			T241	1		T429	3		T505	1
all_values[42]	462	1			T429	2		T505	2		T408	2
all_values[43]	477	1			T71	1		T241	1		T429	4
all_values[44]	467	1			T429	6		T505	6		T386	1
all_values[45]	464	1			T77	1		T505	3		T408	2
all_values[46]	402	1			T71	1		T151	1		T241	1
all_values[47]	453	1			T498	1		T241	1		T429	2
all_values[48]	475	1			T71	1		T389	1		T429	1
all_values[49]	461	1			T429	4		T505	3		T386	2