Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3340	1			T70	2		T429	22		T504	3
all_values[1]	3452	1			T429	27		T504	3		T505	19
all_values[2]	3365	1			T70	1		T429	23		T504	2
all_values[3]	3472	1			T77	2		T429	34		T505	19
all_values[4]	3416	1			T70	1		T429	20		T505	22
all_values[5]	3466	1			T70	1		T429	20		T504	3
all_values[6]	3440	1			T70	1		T429	22		T504	1
all_values[7]	3466	1			T70	1		T429	20		T504	5
all_values[8]	3429	1			T77	1		T429	21		T504	2
all_values[9]	3435	1			T70	1		T77	1		T429	12
all_values[10]	3538	1			T70	2		T429	20		T504	5
all_values[11]	3511	1			T70	1		T77	1		T429	17
all_values[12]	3429	1			T77	1		T429	28		T504	2
all_values[13]	3346	1			T429	21		T504	4		T505	23
all_values[14]	3428	1			T70	1		T429	22		T504	3
all_values[15]	3432	1			T70	1		T429	24		T504	2
all_values[16]	3464	1			T429	15		T504	2		T505	18
all_values[17]	3406	1			T429	16		T505	23		T503	1
all_values[18]	3468	1			T70	2		T77	1		T429	17
all_values[19]	3383	1			T70	2		T429	26		T504	2
all_values[20]	3389	1			T70	1		T429	22		T504	3
all_values[21]	3498	1			T429	23		T504	2		T505	24
all_values[22]	3484	1			T77	1		T429	17		T504	1
all_values[23]	3522	1			T77	1		T429	22		T504	1
all_values[24]	3456	1			T429	11		T504	5		T505	19
all_values[25]	3411	1			T77	2		T429	34		T504	3
all_values[26]	3405	1			T70	3		T429	26		T504	2
all_values[27]	3442	1			T70	1		T429	19		T504	2
all_values[28]	3516	1			T70	2		T77	1		T429	36
all_values[29]	3440	1			T70	1		T429	20		T504	4
all_values[30]	3460	1			T70	2		T429	19		T504	1
all_values[31]	3458	1			T70	1		T77	1		T429	19
all_values[32]	3450	1			T70	1		T77	1		T429	22
all_values[33]	3418	1			T70	1		T77	1		T429	15
all_values[34]	3373	1			T70	1		T77	1		T429	24
all_values[35]	3459	1			T70	2		T429	22		T504	2
all_values[36]	3456	1			T77	1		T429	17		T504	3
all_values[37]	3446	1			T70	1		T429	23		T504	1
all_values[38]	3376	1			T70	2		T429	19		T504	5
all_values[39]	3430	1			T429	28		T504	3		T505	23
all_values[40]	3450	1			T70	1		T429	23		T504	2
all_values[41]	3485	1			T70	2		T429	19		T504	3
all_values[42]	3491	1			T70	1		T429	25		T504	3
all_values[43]	3513	1			T77	3		T429	16		T505	20
all_values[44]	3490	1			T429	14		T505	21		T386	5
all_values[45]	3406	1			T77	1		T429	30		T504	2
all_values[46]	3457	1			T429	22		T504	1		T505	32
all_values[47]	3365	1			T70	3		T429	23		T504	3
all_values[48]	3480	1			T77	1		T429	18		T504	3
all_values[49]	3478	1			T70	2		T429	18		T504	2
all_values[50]	3357	1			T429	20		T504	4		T505	22
all_values[51]	3453	1			T77	1		T429	22		T504	2
all_values[52]	3412	1			T70	1		T77	1		T429	33
all_values[53]	3417	1			T429	22		T504	5		T505	25
all_values[54]	3453	1			T77	3		T429	21		T504	3
all_values[55]	3388	1			T77	1		T429	17		T504	1
all_values[56]	3504	1			T429	21		T504	3		T505	20
all_values[57]	3428	1			T70	3		T429	14		T504	1
all_values[58]	3422	1			T70	1		T77	1		T429	28
all_values[59]	3411	1			T70	1		T429	19		T504	2
all_values[60]	3333	1			T70	2		T77	1		T429	21
all_values[61]	3417	1			T70	1		T429	21		T504	6
all_values[62]	3507	1			T70	1		T77	1		T429	26
all_values[63]	3304	1			T70	1		T77	1		T429	20