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LINE 35385
EXPRESSION (addr_hit[550] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T389,T407,T511 |
| 1 | 1 | 1 | Covered | T46,T54,T49 |
LINE 35389
EXPRESSION (addr_hit[551] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T504,T444,T513 |
| 1 | 1 | 1 | Covered | T49,T388,T399 |
LINE 35391
EXPRESSION (addr_hit[552] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T516,T514,T362 |
| 1 | 1 | 1 | Covered | T44,T48,T369 |
LINE 35393
EXPRESSION (addr_hit[553] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T511,T514,T512 |
| 1 | 1 | 1 | Covered | T49,T340,T143 |
LINE 35395
EXPRESSION (addr_hit[554] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T409,T411 |
| 1 | 1 | 1 | Covered | T49,T408,T340 |
LINE 35397
EXPRESSION (addr_hit[555] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T504,T514 |
| 1 | 1 | 1 | Covered | T49,T340,T411 |
LINE 35399
EXPRESSION (addr_hit[556] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T388,T513 |
| 1 | 1 | 1 | Covered | T49,T408,T399 |
LINE 35401
EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T430,T433 |
| 1 | 1 | 1 | Covered | T49,T386,T340 |
LINE 35403
EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T514,T600 |
| 1 | 1 | 1 | Covered | T49,T340,T378 |
LINE 35405
EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T431,T511,T514 |
| 1 | 1 | 1 | Covered | T24,T51,T52 |
LINE 35408
EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T406,T481,T430 |
| 1 | 1 | 1 | Covered | T49,T340,T143 |
LINE 35411
EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T408,T378 |
| 1 | 1 | 1 | Covered | T49,T340,T449 |
LINE 35414
EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T513,T433 |
| 1 | 1 | 1 | Covered | T49,T386,T340 |
LINE 35417
EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T514,T437 |
| 1 | 1 | 1 | Covered | T50,T49,T429 |
LINE 35420
EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T514,T434 |
| 1 | 1 | 1 | Covered | T18,T45,T47 |
LINE 35423
EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T496,T572,T519 |
| 1 | 1 | 1 | Covered | T49,T429,T340 |
LINE 35426
EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T411,T511,T514 |
| 1 | 1 | 1 | Covered | T46,T54,T49 |
LINE 35429
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T399,T518,T553 |
| 1 | 1 | 1 | Covered | T18,T45,T47 |
LINE 38839
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T18,T45,T46 |