Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159344	1			T74	24		T75	5		T80	10
values[2]	3505	1			T456	2		T404	2		T488	1
values[3]	1601	1			T696	11		T467	1		T385	12
values[4]	1318	1			T696	11		T385	11		T762	1
values[5]	923	1			T696	8		T385	11		T762	1
values[6]	790	1			T696	18		T385	23		T762	1
values[7]	713	1			T696	22		T385	18		T762	1
values[8]	633	1			T696	17		T385	36		T762	1
values[9]	623	1			T696	27		T385	76		T762	1
values[10]	498	1			T696	27		T385	70		T762	1
values[11]	441	1			T696	45		T385	41		T762	1
values[12]	374	1			T696	48		T385	29		T762	1
values[13]	379	1			T696	64		T385	7		T762	1
values[14]	363	1			T696	71		T385	3		T762	1
values[15]	308	1			T696	40		T762	1		T760	4
values[16]	295	1			T696	29		T762	1		T760	7
values[17]	287	1			T696	15		T762	1		T760	1
values[18]	258	1			T696	11		T762	1		T760	1
values[19]	256	1			T696	2		T762	1		T760	4
values[20]	249	1			T762	1		T760	2		T772	22
values[21]	261	1			T762	1		T760	1		T772	16
values[22]	256	1			T762	1		T760	7		T772	6
values[23]	233	1			T762	1		T760	4		T772	1
values[24]	246	1			T762	1		T760	3		T772	4
values[25]	205	1			T762	1		T760	1		T772	6
values[26]	233	1			T762	1		T760	2		T772	2
values[27]	246	1			T762	1		T760	3		T772	8
values[28]	248	1			T762	1		T760	3		T772	29
values[29]	247	1			T762	1		T760	2		T772	44
values[30]	187	1			T762	1		T760	2		T772	26
values[31]	138	1			T762	1		T760	3		T772	15
values[32]	140	1			T762	1		T760	5		T772	2
values[33]	137	1			T762	1		T760	6		T761	1
values[34]	129	1			T762	1		T760	9		T761	1
values[35]	120	1			T762	1		T760	5		T761	1
values[36]	128	1			T762	1		T760	4		T761	1
values[37]	115	1			T762	1		T760	7		T761	1
values[38]	126	1			T762	1		T760	2		T761	1
values[39]	90	1			T762	1		T760	1		T761	1
values[40]	95	1			T762	1		T760	1		T761	1
values[41]	89	1			T762	1		T760	1		T761	1
values[42]	112	1			T762	2		T760	5		T761	1
values[43]	105	1			T762	1		T760	4		T761	1
values[44]	115	1			T762	1		T760	3		T761	1
values[45]	98	1			T762	1		T760	2		T761	1
values[46]	76	1			T762	1		T760	3		T761	1
values[47]	76	1			T762	1		T760	3		T761	1
values[48]	115	1			T762	1		T760	2		T761	1
values[49]	119	1			T762	1		T760	2		T761	1
values[50]	105	1			T762	1		T760	4		T761	1
values[51]	103	1			T762	1		T760	4		T761	1
values[52]	120	1			T762	1		T760	2		T761	1
values[53]	107	1			T762	1		T760	4		T761	1
values[54]	98	1			T762	1		T760	5		T761	1
values[55]	98	1			T762	1		T760	3		T761	1
values[56]	78	1			T762	1		T760	1		T761	1
values[57]	66	1			T762	1		T760	1		T761	1
values[58]	74	1			T762	1		T760	2		T761	1
values[59]	75	1			T762	1		T760	1		T761	1
values[60]	80	1			T762	1		T760	7		T761	1
values[61]	70	1			T762	1		T760	2		T761	1
values[62]	96	1			T762	1		T760	4		T761	1
values[63]	95	1			T762	1		T760	1		T761	1
values[64]	89	1			T762	1		T760	2		T761	1
values[65]	93	1			T762	1		T760	2		T761	1
values[66]	76	1			T762	1		T760	2		T761	1
values[67]	71	1			T762	1		T760	1		T761	1
values[68]	72	1			T762	1		T760	1		T761	1
values[69]	81	1			T762	1		T760	2		T761	1
values[70]	67	1			T762	1		T760	1		T761	1
values[71]	72	1			T762	1		T760	4		T761	1
values[72]	67	1			T762	1		T760	3		T761	1
values[73]	58	1			T762	1		T760	2		T761	1
values[74]	68	1			T762	1		T760	3		T761	1
values[75]	74	1			T762	1		T760	4		T761	1
values[76]	56	1			T762	1		T760	1		T761	1
values[77]	56	1			T762	1		T760	3		T761	1
values[78]	68	1			T762	1		T760	5		T761	1
values[79]	77	1			T762	1		T760	2		T761	1
values[80]	68	1			T762	1		T760	3		T761	1
values[81]	70	1			T762	1		T760	1		T761	1
values[82]	63	1			T762	1		T760	1		T761	1
values[83]	75	1			T762	1		T760	4		T761	1
values[84]	93	1			T762	1		T760	2		T761	1
values[85]	86	1			T762	1		T760	5		T761	1
values[86]	85	1			T762	1		T760	5		T761	1
values[87]	94	1			T762	1		T760	8		T761	2
values[88]	76	1			T762	1		T760	4		T761	1
values[89]	81	1			T762	1		T760	3		T761	1
values[90]	77	1			T762	1		T760	1		T761	1
values[91]	104	1			T762	1		T760	1		T761	1
values[92]	93	1			T762	1		T760	2		T761	1
values[93]	87	1			T762	1		T760	1		T761	1
values[94]	73	1			T762	1		T760	4		T761	2
values[95]	76	1			T762	1		T760	4		T761	1
values[96]	72	1			T762	1		T760	1		T761	3
values[97]	77	1			T762	2		T760	3		T761	2
values[98]	83	1			T762	1		T760	5		T761	1
values[99]	76	1			T762	1		T760	4		T761	2
values[100]	94	1			T762	1		T760	5		T761	3
values[101]	90	1			T762	1		T760	12		T761	2
values[102]	93	1			T762	1		T760	9		T761	1
values[103]	88	1			T762	1		T760	2		T761	3
values[104]	86	1			T762	1		T760	3		T761	2
values[105]	88	1			T762	1		T760	2		T761	1
values[106]	100	1			T762	1		T760	4		T761	1
values[107]	98	1			T762	1		T760	9		T761	1
values[108]	118	1			T762	1		T760	5		T761	6
values[109]	90	1			T762	1		T760	7		T761	1
values[110]	92	1			T762	3		T760	3		T761	4
values[111]	92	1			T762	5		T760	2		T761	2
values[112]	118	1			T762	2		T760	3		T761	1
values[113]	122	1			T762	2		T760	2		T761	4
values[114]	127	1			T762	3		T760	5		T761	5
values[115]	109	1			T762	2		T760	5		T761	3
values[116]	122	1			T762	2		T760	12		T761	2
values[117]	146	1			T762	1		T760	15		T761	2
values[118]	101	1			T762	2		T760	4		T761	3
values[119]	104	1			T762	1		T760	3		T761	1
values[120]	89	1			T762	1		T760	3		T761	2
values[121]	119	1			T762	3		T760	5		T761	2
values[122]	111	1			T762	2		T760	5		T761	3
values[123]	142	1			T762	2		T760	2		T761	3
values[124]	200	1			T762	4		T760	4		T761	1
values[125]	316	1			T762	3		T760	1		T761	2
values[126]	731	1			T762	26		T761	12		T498	56
values[127]	3099	1			T762	157		T761	118		T498	33
values[128]	5654	1			T762	232		T761	224		T498	2