Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	95.29	93.71	95.58		94.38	97.38	99.53

Total tests in report: 2788

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.51	40.51	44.93	44.93	42.91	42.91	34.45	34.45			57.93	57.93	62.66	62.66	0.19	0.19	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1743614282
48.93	8.41	50.24	5.32	53.39	10.47	34.72	0.27			67.18	9.25	87.06	24.40	0.96	0.78	/workspace/coverage/cover_reg_top/0.chip_csr_rw.2166754560
56.06	7.13	62.23	11.99	57.90	4.51	38.15	3.43			68.54	1.36	87.06	0.00	22.47	21.50	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1388074470
61.26	5.20	73.47	11.24	65.42	7.52	40.80	2.65			78.36	9.82	87.06	0.00	22.47	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2246003415
64.72	3.46	73.47	0.00	65.42	0.00	40.80	0.00			78.36	0.00	87.06	0.00	43.20	20.74	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3626947770
67.60	2.89	73.47	0.00	65.47	0.05	40.80	0.00			78.39	0.03	87.06	0.00	60.44	17.24	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.857352938
70.13	2.53	73.47	0.00	65.47	0.00	55.92	15.12			78.39	0.00	87.06	0.00	60.49	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2436857288
72.51	2.38	78.90	5.43	69.30	3.82	59.41	3.49			79.92	1.53	87.06	0.00	60.49	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3132887722
74.65	2.14	79.14	0.24	71.90	2.60	62.70	3.29			80.79	0.87	87.06	0.00	66.30	5.82	/workspace/coverage/cover_reg_top/57.xbar_stress_all.1520129779
76.55	1.90	79.39	0.25	72.08	0.18	72.75	10.05			80.99	0.20	87.80	0.74	66.30	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3612732113
78.13	1.58	81.64	2.25	74.95	2.87	75.02	2.27			83.06	2.07	87.80	0.00	66.33	0.02	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.832643914
79.67	1.54	84.18	2.54	78.44	3.49	75.32	0.30			85.97	2.91	87.80	0.00	66.33	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2936337307
81.03	1.36	84.18	0.00	78.90	0.46	75.32	0.00			86.06	0.10	87.80	0.00	73.92	7.59	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1801957198
82.27	1.24	85.31	1.13	79.74	0.84	76.06	0.74			86.90	0.83	91.68	3.88	73.92	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.38231856
83.48	1.22	87.17	1.87	81.13	1.39	78.16	2.10			88.84	1.94	91.68	0.00	73.92	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1856710991
84.61	1.12	89.06	1.89	82.21	1.08	80.20	2.04			90.13	1.29	91.87	0.18	74.16	0.25	/workspace/coverage/default/31.chip_sw_all_escalation_resets.374455529
85.56	0.95	89.06	0.00	82.21	0.00	80.20	0.00			90.13	0.00	91.87	0.00	79.87	5.71	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1126849754
86.47	0.92	90.28	1.22	83.22	1.01	82.32	2.12			91.29	1.16	91.87	0.00	79.87	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2985176743
87.33	0.86	91.02	0.74	83.38	0.16	82.34	0.02			91.45	0.16	95.93	4.07	79.87	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.458418367
88.12	0.79	91.02	0.00	83.58	0.20	82.35	0.01			91.45	0.00	95.93	0.00	84.38	4.51	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.964173374
88.85	0.73	91.92	0.90	84.55	0.97	83.63	1.29			92.09	0.64	95.93	0.00	84.96	0.58	/workspace/coverage/default/2.chip_jtag_csr_rw.62665555
89.38	0.54	91.92	0.01	84.71	0.17	84.33	0.69			92.12	0.03	95.93	0.00	87.29	2.33	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2051530062
89.88	0.49	91.94	0.01	87.26	2.55	84.33	0.00			92.12	0.00	95.93	0.00	87.70	0.41	/workspace/coverage/cover_reg_top/11.chip_tl_errors.209171512
90.35	0.47	92.68	0.74	88.15	0.89	84.78	0.45			92.86	0.74	95.93	0.00	87.70	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.3013428955
90.80	0.45	92.73	0.05	88.21	0.06	85.98	1.20			92.86	0.00	95.93	0.00	89.11	1.41	/workspace/coverage/default/2.chip_sw_alert_test.3781150161
91.22	0.42	92.73	0.00	88.21	0.00	85.98	0.00			92.86	0.00	95.93	0.00	91.63	2.53	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.4021209820
91.60	0.38	92.73	0.00	88.21	0.00	88.16	2.19			92.86	0.00	95.93	0.00	91.73	0.09	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1896592473
91.91	0.31	93.03	0.30	89.67	1.46	88.21	0.04			92.90	0.04	95.93	0.00	91.74	0.01	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2319234252
92.16	0.24	93.84	0.81	89.88	0.21	88.54	0.33			93.00	0.10	95.93	0.00	91.74	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.622361676
92.38	0.22	93.84	0.00	89.92	0.04	88.92	0.38			93.00	0.00	95.93	0.00	92.64	0.90	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3789159198
92.59	0.21	93.84	0.00	89.92	0.00	90.02	1.10			93.00	0.00	96.12	0.18	92.64	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1323067362
92.80	0.21	93.84	0.00	89.92	0.00	90.02	0.00			93.00	0.00	96.12	0.00	93.93	1.28	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1596535699
93.01	0.20	93.84	0.00	89.97	0.05	90.02	0.00			93.00	0.00	96.12	0.00	95.10	1.17	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3391995650
93.18	0.17	93.84	0.00	89.97	0.01	90.02	0.00			93.00	0.00	96.12	0.00	96.12	1.02	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1730649008
93.34	0.16	93.84	0.00	89.97	0.00	90.76	0.74			93.00	0.00	96.12	0.00	96.35	0.22	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1840573357
93.49	0.15	93.84	0.00	90.00	0.03	90.76	0.00			93.00	0.00	96.12	0.00	97.19	0.85	/workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1993991326
93.62	0.13	93.84	0.00	90.01	0.01	91.54	0.78			93.00	0.00	96.12	0.00	97.19	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.711618672
93.74	0.12	94.01	0.17	90.28	0.27	91.83	0.29			93.00	0.00	96.12	0.00	97.19	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1795622038
93.86	0.12	94.03	0.03	90.61	0.33	91.83	0.00			93.36	0.35	96.12	0.00	97.19	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2934535101
93.96	0.11	94.03	0.00	90.65	0.04	91.83	0.00			93.36	0.00	96.12	0.00	97.78	0.59	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3492077429
94.06	0.10	94.03	0.00	90.65	0.00	92.43	0.60			93.36	0.00	96.12	0.00	97.78	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.390830152
94.16	0.10	94.16	0.13	90.89	0.25	92.44	0.01			93.58	0.22	96.12	0.00	97.78	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3746891935
94.25	0.09	94.16	0.00	91.46	0.56	92.44	0.00			93.58	0.00	96.12	0.00	97.78	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3630761178
94.34	0.09	94.16	0.00	91.46	0.00	92.44	0.00			93.58	0.00	96.12	0.00	98.31	0.53	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3149118454
94.43	0.08	94.16	0.01	91.68	0.22	92.46	0.02			93.83	0.25	96.12	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3782922834
94.50	0.08	94.16	0.00	91.68	0.00	92.91	0.45			93.83	0.00	96.12	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4205320357
94.58	0.08	94.19	0.03	91.74	0.06	92.99	0.08			93.89	0.07	96.30	0.18	98.34	0.04	/workspace/coverage/default/7.chip_sw_all_escalation_resets.999482651
94.65	0.07	94.20	0.01	91.79	0.05	93.17	0.18			93.91	0.02	96.49	0.18	98.34	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2501844038
94.71	0.06	94.20	0.00	91.79	0.00	93.53	0.35			93.91	0.00	96.49	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.1248552826
94.76	0.05	94.26	0.06	91.87	0.08	93.67	0.14			93.93	0.02	96.49	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1393285815
94.81	0.05	94.29	0.03	91.89	0.03	93.67	0.01			93.95	0.02	96.67	0.18	98.36	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1289725652
94.85	0.05	94.42	0.13	91.90	0.01	93.79	0.12			93.97	0.02	96.67	0.00	98.36	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.50141890
94.89	0.04	94.43	0.01	91.92	0.03	93.79	0.00			93.98	0.01	96.86	0.18	98.37	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.501873882
94.93	0.04	94.43	0.00	91.93	0.01	94.02	0.23			93.98	0.00	96.86	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/60.xbar_same_source.3370849777
94.97	0.04	94.43	0.01	91.94	0.01	94.03	0.01			93.98	0.01	97.04	0.18	98.38	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.726937036
95.01	0.04	94.43	0.01	91.96	0.01	94.04	0.01			93.99	0.01	97.23	0.18	98.39	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.150312546
95.04	0.04	94.49	0.06	92.01	0.05	94.13	0.09			94.02	0.02	97.23	0.00	98.39	0.00	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1297880114
95.08	0.04	94.54	0.05	92.04	0.04	94.22	0.09			94.05	0.03	97.23	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3441180548
95.11	0.04	94.54	0.00	92.24	0.20	94.22	0.00			94.05	0.00	97.23	0.00	98.40	0.01	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2708483868
95.15	0.03	94.54	0.00	92.24	0.00	94.42	0.20			94.05	0.00	97.23	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3487099893
95.18	0.03	94.54	0.00	92.24	0.00	94.42	0.00			94.05	0.00	97.41	0.18	98.40	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.508042636
95.21	0.03	94.54	0.00	92.24	0.00	94.60	0.18			94.05	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1118558000
95.24	0.03	94.62	0.07	92.29	0.05	94.62	0.03			94.07	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1645475353
95.26	0.03	94.69	0.07	92.35	0.05	94.62	0.00			94.11	0.03	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3901562730
95.29	0.03	94.76	0.08	92.38	0.03	94.63	0.01			94.16	0.05	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2382894347
95.31	0.02	94.82	0.06	92.43	0.05	94.63	0.01			94.18	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2292505478
95.34	0.02	94.82	0.00	92.56	0.14	94.63	0.00			94.18	0.00	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.272835259
95.36	0.02	94.82	0.00	92.65	0.09	94.63	0.00			94.20	0.02	97.41	0.00	98.43	0.02	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1007451083
95.38	0.02	94.82	0.00	92.65	0.00	94.76	0.12			94.20	0.00	97.41	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3770059377
95.40	0.02	94.82	0.00	92.65	0.00	94.87	0.11			94.20	0.00	97.41	0.00	98.44	0.01	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2603722110
95.42	0.02	94.82	0.00	92.74	0.09	94.87	0.00			94.23	0.03	97.41	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/44.xbar_access_same_device.801024411
95.44	0.02	94.82	0.00	92.78	0.04	94.87	0.00			94.23	0.00	97.41	0.00	98.51	0.07	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3499752150
95.45	0.02	94.84	0.01	92.79	0.01	94.93	0.06			94.24	0.01	97.41	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.478853744
95.47	0.01	94.84	0.00	92.86	0.07	94.93	0.00			94.26	0.02	97.41	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all.2050835029
95.48	0.01	94.84	0.01	92.90	0.04	94.98	0.05			94.26	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.562846818
95.50	0.01	94.84	0.00	92.90	0.00	95.03	0.05			94.26	0.00	97.41	0.00	98.54	0.04	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1558752360
95.51	0.01	94.84	0.00	92.98	0.08	95.03	0.00			94.26	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.451782282
95.52	0.01	94.84	0.00	93.01	0.03	95.03	0.00			94.26	0.00	97.41	0.00	98.59	0.05	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2253560017
95.53	0.01	94.84	0.00	93.01	0.00	95.06	0.03			94.26	0.00	97.41	0.00	98.63	0.04	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1583263559
95.54	0.01	94.84	0.00	93.01	0.00	95.13	0.07			94.26	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2245245397
95.56	0.01	94.84	0.00	93.07	0.06	95.13	0.00			94.26	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2798405728
95.57	0.01	94.84	0.00	93.10	0.03	95.13	0.00			94.29	0.03	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2094866442
95.58	0.01	94.84	0.00	93.16	0.06	95.13	0.00			94.29	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2630201368
95.59	0.01	94.84	0.00	93.20	0.04	95.13	0.00			94.31	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2826911670
95.60	0.01	94.86	0.02	93.20	0.01	95.14	0.02			94.33	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3522928625
95.61	0.01	94.86	0.00	93.20	0.00	95.20	0.06			94.33	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4097051109
95.61	0.01	94.89	0.03	93.22	0.01	95.21	0.01			94.33	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.453063072
95.62	0.01	94.92	0.03	93.23	0.01	95.21	0.01			94.35	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.667677019
95.63	0.01	94.92	0.01	93.24	0.02	95.24	0.03			94.35	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1154520188
95.64	0.01	94.92	0.00	93.26	0.01	95.24	0.00			94.35	0.00	97.41	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1826470784
95.65	0.01	94.92	0.00	93.26	0.00	95.29	0.05			94.35	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.462374135
95.66	0.01	94.93	0.01	93.28	0.02	95.30	0.01			94.35	0.01	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.149097119
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95.67	0.01	94.93	0.00	93.32	0.00	95.34	0.04			94.35	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.628563198
95.67	0.01	94.93	0.00	93.32	0.00	95.38	0.04			94.35	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2648128863
95.68	0.01	94.93	0.01	93.32	0.01	95.40	0.03			94.35	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1619971398
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95.69	0.01	94.93	0.00	93.36	0.00	95.40	0.00			94.35	0.00	97.41	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.753782817
95.70	0.01	94.96	0.03	93.36	0.01	95.41	0.01			94.35	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_power_sleep_load.3121217406
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95.72	0.01	94.97	0.00	93.48	0.01	95.42	0.00			94.35	0.00	97.41	0.00	98.71	0.01	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1984416127
95.73	0.01	94.97	0.00	93.49	0.01	95.42	0.00			94.35	0.00	97.41	0.00	98.72	0.01	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.557320694
95.73	0.01	94.97	0.00	93.49	0.00	95.45	0.03			94.35	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2124269196
95.74	0.01	94.97	0.01	93.51	0.02	95.45	0.00			94.35	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2558384241
95.74	0.01	94.97	0.00	93.51	0.00	95.45	0.00			94.35	0.00	97.41	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2741695286
95.74	0.01	94.97	0.00	93.51	0.00	95.45	0.00			94.35	0.00	97.41	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1949340392
95.75	0.01	94.97	0.00	93.54	0.02	95.45	0.00			94.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/51.xbar_access_same_device.2675506462
95.75	0.01	94.97	0.00	93.56	0.02	95.45	0.00			94.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4127856894
95.75	0.01	94.97	0.00	93.56	0.00	95.47	0.02			94.35	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.245900534
95.76	0.01	94.97	0.00	93.56	0.00	95.47	0.01			94.35	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2612120632
95.76	0.01	94.97	0.00	93.56	0.01	95.47	0.00			94.35	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.654720536
95.76	0.01	94.97	0.00	93.58	0.01	95.47	0.00			94.35	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2450966216
95.76	0.01	94.97	0.00	93.59	0.01	95.47	0.00			94.35	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.4111548632
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95.77	0.01	94.98	0.00	93.61	0.01	95.48	0.00			94.36	0.01	97.41	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.56894901
95.77	0.01	94.98	0.00	93.61	0.00	95.49	0.01			94.36	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2983861655
95.77	0.01	94.98	0.00	93.61	0.00	95.50	0.01			94.36	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2673677776
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95.78	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3557017326
95.78	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3554919450
95.78	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2111544333
95.78	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643881776
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95.79	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906909473
95.79	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1886905023
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95.79	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747844890
95.80	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4211492226
95.80	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1566850916
95.80	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.444538412
95.80	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4111982642
95.80	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.262720774
95.81	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3820978797
95.81	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.811299799
95.81	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.4087284255
95.81	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3427868483
95.81	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.45289076
95.82	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489407770
95.82	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3934290969
95.82	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108844132
95.82	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2582370751
95.82	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3827737669
95.83	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1590870505
95.83	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1388110884
95.83	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1213891635
95.83	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.472197480
95.83	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.247003638
95.84	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.935478100
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95.84	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.4096690912
95.84	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.403916358
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95.85	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.214468702
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95.89	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/72.chip_sw_all_escalation_resets.3939835534
95.89	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3126706906
95.89	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1251742768
95.90	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.128898205
95.90	0.01	94.98	0.00	93.61	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1040001582
95.90	0.01	94.98	0.00	93.62	0.01	95.50	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.844542063
95.90	0.01	94.98	0.00	93.63	0.01	95.50	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1164978029
95.90	0.01	94.98	0.01	93.64	0.01	95.50	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2915060974
95.91	0.01	94.99	0.01	93.64	0.00	95.50	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.605524809
95.91	0.01	95.00	0.01	93.64	0.00	95.51	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3968273568
95.91	0.01	95.00	0.01	93.64	0.00	95.51	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/51.chip_sw_all_escalation_resets.340936382
95.91	0.01	95.00	0.00	93.64	0.00	95.52	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_init.42762196
95.91	0.01	95.00	0.00	93.64	0.00	95.53	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3747346376
95.91	0.01	95.00	0.00	93.64	0.00	95.54	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3604716923
95.92	0.01	95.00	0.00	93.64	0.00	95.54	0.00			94.37	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.342376065
95.92	0.01	95.00	0.00	93.64	0.00	95.54	0.00			94.38	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.575086784
95.92	0.01	95.00	0.00	93.64	0.01	95.54	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/12.xbar_same_source.3212033264
95.92	0.01	95.00	0.00	93.65	0.01	95.54	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.260874484
95.92	0.01	95.00	0.00	93.66	0.01	95.54	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_gpio.3254231385
95.92	0.01	95.01	0.01	93.66	0.00	95.54	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4293922353
95.92	0.01	95.01	0.00	93.66	0.00	95.55	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.804919928
95.92	0.01	95.01	0.00	93.66	0.00	95.56	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3111623162
95.92	0.01	95.01	0.00	93.66	0.00	95.56	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.288124748
95.93	0.01	95.01	0.00	93.66	0.00	95.57	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4232462959
95.93	0.01	95.01	0.00	93.66	0.00	95.57	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1618081300
95.93	0.01	95.01	0.00	93.66	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3778254492
95.93	0.01	95.01	0.00	93.67	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1990751906
95.93	0.01	95.01	0.00	93.67	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_rw.1547683918
95.93	0.01	95.01	0.00	93.67	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3106280045
95.93	0.01	95.01	0.00	93.68	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1440226040
95.93	0.01	95.01	0.00	93.68	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/31.xbar_error_random.1028107924
95.93	0.01	95.01	0.00	93.68	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2188529978
95.93	0.01	95.01	0.00	93.69	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/78.xbar_error_random.2453117397
95.93	0.01	95.01	0.00	93.69	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/9.xbar_error_random.3654539045
95.93	0.01	95.01	0.00	93.69	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/90.xbar_error_random.1773100512
95.93	0.01	95.01	0.00	93.70	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.4134204739
95.93	0.01	95.01	0.00	93.70	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3148248834
95.93	0.01	95.01	0.00	93.71	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2640028015
95.93	0.01	95.01	0.00	93.71	0.01	95.57	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_gpio.239645883
95.93	0.01	95.01	0.00	93.71	0.00	95.57	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2106850484
95.94	0.01	95.01	0.00	93.71	0.00	95.57	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3805771368
95.94	0.01	95.01	0.00	93.71	0.00	95.58	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1614077115
95.94	0.01	95.01	0.00	93.71	0.00	95.58	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2831219551

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3020941183
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1396472101
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4281250187
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.771532075
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.81537030
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2636983389
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.389898557
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3223811791
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.600021641
/workspace/coverage/cover_reg_top/0.xbar_error_random.2787276733
/workspace/coverage/cover_reg_top/0.xbar_random.584711629
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.296372555
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3264632339
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2280648470
/workspace/coverage/cover_reg_top/0.xbar_same_source.2270349422
/workspace/coverage/cover_reg_top/0.xbar_smoke.3084473349
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.624673947
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2849777003
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3656740140
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3022390234
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2363153031
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3686083495
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.394331210
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1482679746
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1055545119
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2593165848
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2819751545
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3646350292
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4040112577
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2530788267
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2459143254
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2732321715
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2932909854
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2358554297
/workspace/coverage/cover_reg_top/1.xbar_error_random.638952380
/workspace/coverage/cover_reg_top/1.xbar_random.3422571215
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.369569469
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2625914528
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3664499270
/workspace/coverage/cover_reg_top/1.xbar_same_source.829646655
/workspace/coverage/cover_reg_top/1.xbar_smoke.3550358440
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4181105829
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.180950980
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3196327077
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3982129856
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.993545966
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.172559979
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3170250694
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2458531969
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4136392231
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2881821348
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.178131678
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.262599431
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3519961856
/workspace/coverage/cover_reg_top/10.xbar_error_random.2977020825
/workspace/coverage/cover_reg_top/10.xbar_random.3919197659
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2814268377
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2433194341
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.688369337
/workspace/coverage/cover_reg_top/10.xbar_same_source.801227828
/workspace/coverage/cover_reg_top/10.xbar_smoke.3032619855
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3985057149
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1257032606
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1290303858
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1803638594
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.790237294
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.644393729
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1095085327
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.97790897
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2111883552
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.757507400
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3449051112
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4159209009
/workspace/coverage/cover_reg_top/11.xbar_error_random.241168768
/workspace/coverage/cover_reg_top/11.xbar_random.1348155202
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1235343581
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4042105496
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3398999125
/workspace/coverage/cover_reg_top/11.xbar_same_source.2050874571
/workspace/coverage/cover_reg_top/11.xbar_smoke.2803207133
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2707701677
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3666441368
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3348224730
/workspace/coverage/cover_reg_top/11.xbar_stress_all.283339054
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1212636150
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.405776008
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1263592010
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3081309423
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4138420148
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1262660196
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2435034790
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3224274771
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2211476093
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4224021894
/workspace/coverage/cover_reg_top/12.xbar_error_random.2259670971
/workspace/coverage/cover_reg_top/12.xbar_random.2644457191
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3165868164
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.692950526
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2837286432
/workspace/coverage/cover_reg_top/12.xbar_smoke.3943262335
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3671726020
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.875564113
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2147038449
/workspace/coverage/cover_reg_top/12.xbar_stress_all.338307236
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1160628700
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3239285868
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4017807898
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1772823383
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3734506221
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.964452230
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3842840233
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.186551643
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3583095073
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3823482596
/workspace/coverage/cover_reg_top/13.xbar_error_random.2549275342
/workspace/coverage/cover_reg_top/13.xbar_random.1492220555
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1193266733
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2375382053
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2495582063
/workspace/coverage/cover_reg_top/13.xbar_same_source.722769982
/workspace/coverage/cover_reg_top/13.xbar_smoke.405256600
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2464419957
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2959836634
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3480361382
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2321399072
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2391483432
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1321346354
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2550048781
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2794676418
/workspace/coverage/cover_reg_top/14.chip_csr_rw.4032933739
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2169373421
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3341239870
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3102670346
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.4078661059
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2963148066
/workspace/coverage/cover_reg_top/14.xbar_error_random.3074743703
/workspace/coverage/cover_reg_top/14.xbar_random.3025813741
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2371145402
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1674347446
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1284781425
/workspace/coverage/cover_reg_top/14.xbar_same_source.1061812213
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/workspace/coverage/default/65.chip_sw_all_escalation_resets.1438129998
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055821622
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3845007541
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3817891723
/workspace/coverage/default/68.chip_sw_all_escalation_resets.244585675
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3457657402
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193017417
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3720330407
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2991529642
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1315629987
/workspace/coverage/default/70.chip_sw_all_escalation_resets.991094962
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035638699
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4041511731
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111328884
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.987756784
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4149412702
/workspace/coverage/default/74.chip_sw_all_escalation_resets.169446385
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403472053
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3246458892
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810919048
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3434246811
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750236291
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1977603421
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117398357
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2661650270
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3245133334
/workspace/coverage/default/8.chip_sw_all_escalation_resets.532507121
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1010712652
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.814776601
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.484054717
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1353938785
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238548569
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3487150773
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003512964
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032600891
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1674916325
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.257054883
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3444281977
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771405532
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2497791954
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4230976397
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1764584776
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4277284074
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4278035140
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096505363
/workspace/coverage/default/88.chip_sw_all_escalation_resets.262967739
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3649554
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2405953688
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2851872307
/workspace/coverage/default/9.chip_sw_all_escalation_resets.959309506
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2285712995
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.668462922
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2077281050
/workspace/coverage/default/92.chip_sw_all_escalation_resets.4284491267
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2863970713
/workspace/coverage/default/94.chip_sw_all_escalation_resets.806638799
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1400824577
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1668006565
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3897792349
/workspace/coverage/default/98.chip_sw_all_escalation_resets.160780885
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3031610787
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.610296437
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1809171632
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2525155807
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1619364322
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4015268598
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.921096609
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.623193523
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.508502139

---

Total test records in report: 2788

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1896592473			May 02 04:49:58 PM PDT 24	May 02 05:21:37 PM PDT 24	20391313675 ps
T2	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1297880114			May 02 05:00:39 PM PDT 24	May 02 05:27:18 PM PDT 24	7691673196 ps
T3	/workspace/coverage/default/0.chip_sw_kmac_entropy.1248552826			May 02 04:42:02 PM PDT 24	May 02 04:47:26 PM PDT 24	2973893998 ps
T31	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2603722110			May 02 04:50:39 PM PDT 24	May 02 04:56:34 PM PDT 24	5081747896 ps
T53	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1743614282			May 02 04:49:49 PM PDT 24	May 02 05:21:31 PM PDT 24	15061568207 ps
T87	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.854260719			May 02 04:52:59 PM PDT 24	May 02 05:10:35 PM PDT 24	6212610785 ps
T4	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1583263559			May 02 04:55:13 PM PDT 24	May 02 05:32:45 PM PDT 24	27831102128 ps
T88	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.832643914			May 02 05:02:41 PM PDT 24	May 02 05:08:51 PM PDT 24	3411167928 ps
T15	/workspace/coverage/default/0.chip_sw_usbdev_config_host.478853744			May 02 04:39:11 PM PDT 24	May 02 05:12:15 PM PDT 24	8651089000 ps
T62	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3963867694			May 02 04:40:50 PM PDT 24	May 02 04:51:32 PM PDT 24	6215352218 ps
T59	/workspace/coverage/default/39.chip_sw_all_escalation_resets.311442865			May 02 05:04:05 PM PDT 24	May 02 05:12:52 PM PDT 24	4791914830 ps
T60	/workspace/coverage/default/31.chip_sw_all_escalation_resets.374455529			May 02 05:03:18 PM PDT 24	May 02 05:14:08 PM PDT 24	4918591752 ps
T179	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3521180740			May 02 05:02:08 PM PDT 24	May 02 05:26:28 PM PDT 24	8312468660 ps
T180	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1439446883			May 02 04:43:46 PM PDT 24	May 02 04:53:31 PM PDT 24	4845672408 ps
T401	/workspace/coverage/default/1.chip_sw_kmac_idle.2787869515			May 02 04:47:57 PM PDT 24	May 02 04:50:57 PM PDT 24	2642922250 ps
T184	/workspace/coverage/default/2.chip_sw_pattgen_ios.4275743308			May 02 04:53:36 PM PDT 24	May 02 04:59:03 PM PDT 24	2513962456 ps
T112	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.860837013			May 02 04:49:49 PM PDT 24	May 02 05:41:02 PM PDT 24	20873591799 ps
T227	/workspace/coverage/default/0.chip_sw_plic_sw_irq.605524809			May 02 04:44:24 PM PDT 24	May 02 04:49:50 PM PDT 24	3002130924 ps
T121	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2483381913			May 02 04:56:34 PM PDT 24	May 02 05:30:28 PM PDT 24	10038336778 ps
T164	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.901669612			May 02 04:49:29 PM PDT 24	May 02 04:52:32 PM PDT 24	2597937375 ps
T5	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2817733169			May 02 04:59:42 PM PDT 24	May 02 05:28:26 PM PDT 24	16970607011 ps
T269	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4277284074			May 02 05:07:35 PM PDT 24	May 02 05:14:30 PM PDT 24	4355657160 ps
T270	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.216688698			May 02 04:47:24 PM PDT 24	May 02 05:00:55 PM PDT 24	4807803330 ps
T41	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3612732113			May 02 04:40:59 PM PDT 24	May 02 05:29:08 PM PDT 24	27420505872 ps
T271	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117398357			May 02 05:10:19 PM PDT 24	May 02 05:15:11 PM PDT 24	3488455080 ps
T140	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1763737901			May 02 04:51:27 PM PDT 24	May 02 07:59:13 PM PDT 24	63554226658 ps
T272	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1315629987			May 02 05:05:54 PM PDT 24	May 02 05:11:08 PM PDT 24	3566267700 ps
T165	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.711618672			May 02 04:41:55 PM PDT 24	May 02 04:53:01 PM PDT 24	8000970609 ps
T44	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3522928625			May 02 05:00:55 PM PDT 24	May 02 05:06:35 PM PDT 24	3954979740 ps
T232	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1993775906			May 02 04:49:05 PM PDT 24	May 02 05:53:26 PM PDT 24	43868732080 ps
T391	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1438631447			May 02 04:54:31 PM PDT 24	May 02 05:07:58 PM PDT 24	9363432532 ps
T45	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1898535181			May 02 04:55:00 PM PDT 24	May 02 04:57:17 PM PDT 24	2234122452 ps
T181	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2459048518			May 02 04:41:21 PM PDT 24	May 02 04:52:25 PM PDT 24	4718886750 ps
T392	/workspace/coverage/default/0.chip_sw_example_flash.3799374802			May 02 04:39:47 PM PDT 24	May 02 04:42:42 PM PDT 24	2006000660 ps
T393	/workspace/coverage/default/0.chip_sw_kmac_idle.2176058448			May 02 04:41:12 PM PDT 24	May 02 04:46:00 PM PDT 24	3008450920 ps
T38	/workspace/coverage/default/1.chip_sw_spi_device_tpm.3261819470			May 02 04:45:47 PM PDT 24	May 02 04:53:09 PM PDT 24	3856044093 ps
T394	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.604672564			May 02 04:42:11 PM PDT 24	May 02 04:49:51 PM PDT 24	7156600770 ps
T116	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1169313369			May 02 04:39:49 PM PDT 24	May 02 05:10:58 PM PDT 24	13221620182 ps
T61	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1213891635			May 02 05:03:17 PM PDT 24	May 02 05:14:54 PM PDT 24	5482714328 ps
T191	/workspace/coverage/default/9.chip_sw_all_escalation_resets.959309506			May 02 05:02:16 PM PDT 24	May 02 05:12:48 PM PDT 24	5081994312 ps
T822	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2359670848			May 02 04:57:47 PM PDT 24	May 02 05:01:54 PM PDT 24	2297895526 ps
T306	/workspace/coverage/default/7.chip_sw_all_escalation_resets.999482651			May 02 05:01:14 PM PDT 24	May 02 05:11:15 PM PDT 24	5489633844 ps
T66	/workspace/coverage/default/0.chip_tap_straps_dev.2243732379			May 02 04:41:39 PM PDT 24	May 02 04:45:47 PM PDT 24	3201142838 ps
T189	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3966131759			May 02 05:03:41 PM PDT 24	May 02 05:08:12 PM PDT 24	3028947280 ps
T166	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1124360048			May 02 04:42:28 PM PDT 24	May 02 04:45:44 PM PDT 24	2977497649 ps
T192	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2612120632			May 02 04:45:04 PM PDT 24	May 02 04:55:08 PM PDT 24	4441158820 ps
T344	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.263424226			May 02 05:01:39 PM PDT 24	May 02 05:07:44 PM PDT 24	3772364812 ps
T81	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.472197480			May 02 05:05:26 PM PDT 24	May 02 05:12:11 PM PDT 24	3533424920 ps
T94	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2640051795			May 02 05:04:49 PM PDT 24	May 02 05:12:59 PM PDT 24	4073219976 ps
T95	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1548919509			May 02 04:55:40 PM PDT 24	May 02 04:59:59 PM PDT 24	2483872074 ps
T96	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031727544			May 02 05:06:31 PM PDT 24	May 02 05:13:53 PM PDT 24	3649516004 ps
T97	/workspace/coverage/default/5.chip_sw_all_escalation_resets.3977457925			May 02 05:02:38 PM PDT 24	May 02 05:12:42 PM PDT 24	5125949028 ps
T98	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1315250131			May 02 04:49:13 PM PDT 24	May 02 04:58:36 PM PDT 24	5567639072 ps
T99	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3434246811			May 02 05:06:18 PM PDT 24	May 02 05:16:25 PM PDT 24	5320808678 ps
T100	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.699946232			May 02 04:44:42 PM PDT 24	May 02 04:53:44 PM PDT 24	3951626522 ps
T101	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2564753919			May 02 04:53:28 PM PDT 24	May 02 05:01:09 PM PDT 24	4039273462 ps
T102	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2163135787			May 02 04:47:14 PM PDT 24	May 02 05:11:52 PM PDT 24	8568233406 ps
T263	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3761851183			May 02 04:56:10 PM PDT 24	May 02 05:13:54 PM PDT 24	5582745400 ps
T230	/workspace/coverage/default/2.chip_sw_rv_timer_irq.4180167095			May 02 04:55:53 PM PDT 24	May 02 05:00:30 PM PDT 24	2321698660 ps
T12	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3746891935			May 02 04:54:42 PM PDT 24	May 02 04:59:42 PM PDT 24	2864128234 ps
T105	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2681594251			May 02 04:45:47 PM PDT 24	May 02 04:56:45 PM PDT 24	19430791660 ps
T106	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2168536239			May 02 04:50:12 PM PDT 24	May 02 04:54:31 PM PDT 24	2538976054 ps
T107	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4044157345			May 02 05:05:07 PM PDT 24	May 02 05:11:42 PM PDT 24	3415617008 ps
T108	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1795622038			May 02 04:41:12 PM PDT 24	May 02 04:48:41 PM PDT 24	5317037530 ps
T109	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1419239497			May 02 04:43:25 PM PDT 24	May 02 05:01:21 PM PDT 24	8090438720 ps
T110	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.428870282			May 02 04:56:24 PM PDT 24	May 02 05:06:30 PM PDT 24	8950899984 ps
T42	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3555396938			May 02 05:01:08 PM PDT 24	May 02 05:15:22 PM PDT 24	11776750539 ps
T43	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.390830152			May 02 04:56:06 PM PDT 24	May 02 06:18:24 PM PDT 24	51099317099 ps
T111	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2436857288			May 02 04:57:20 PM PDT 24	May 02 06:03:06 PM PDT 24	17971557306 ps
T264	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1256163422			May 02 04:45:09 PM PDT 24	May 02 04:56:06 PM PDT 24	3927056722 ps
T265	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3568880359			May 02 04:40:25 PM PDT 24	May 02 04:51:04 PM PDT 24	7310503448 ps
T266	/workspace/coverage/default/2.chip_sw_aes_idle.2463842658			May 02 04:56:31 PM PDT 24	May 02 05:00:35 PM PDT 24	2369672688 ps
T117	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.628563198			May 02 04:40:57 PM PDT 24	May 02 04:52:16 PM PDT 24	4488371544 ps
T608	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.851389695			May 02 04:41:48 PM PDT 24	May 02 04:50:21 PM PDT 24	4406324862 ps
T823	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1696204033			May 02 04:40:26 PM PDT 24	May 02 05:00:35 PM PDT 24	5416205122 ps
T231	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.914653418			May 02 04:45:24 PM PDT 24	May 02 04:50:19 PM PDT 24	3333791200 ps
T307	/workspace/coverage/default/83.chip_sw_all_escalation_resets.1674916325			May 02 05:07:15 PM PDT 24	May 02 05:15:55 PM PDT 24	5419864428 ps
T824	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3437388636			May 02 04:45:51 PM PDT 24	May 02 04:56:13 PM PDT 24	4610878750 ps
T114	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4215759045			May 02 04:47:25 PM PDT 24	May 02 05:50:36 PM PDT 24	18781802281 ps
T346	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1388110884			May 02 05:06:08 PM PDT 24	May 02 05:12:12 PM PDT 24	3804985380 ps
T120	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1409399970			May 02 04:46:33 PM PDT 24	May 02 04:58:21 PM PDT 24	5604008168 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.38231856			May 02 05:01:07 PM PDT 24	May 02 05:09:21 PM PDT 24	7541279144 ps
T150	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003512964			May 02 05:07:06 PM PDT 24	May 02 05:13:45 PM PDT 24	4415590548 ps
T314	/workspace/coverage/default/21.chip_sw_all_escalation_resets.45289076			May 02 05:02:06 PM PDT 24	May 02 05:13:34 PM PDT 24	4268557944 ps
T156	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1892553394			May 02 04:41:21 PM PDT 24	May 02 05:00:25 PM PDT 24	11088503160 ps
T193	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4097051109			May 02 04:45:29 PM PDT 24	May 02 04:53:17 PM PDT 24	3958498928 ps
T63	/workspace/coverage/default/1.chip_tap_straps_rma.50141890			May 02 04:48:26 PM PDT 24	May 02 04:57:09 PM PDT 24	5479747718 ps
T167	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3132519556			May 02 04:59:26 PM PDT 24	May 02 05:03:09 PM PDT 24	3175768770 ps
T141	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3200796259			May 02 04:48:00 PM PDT 24	May 02 08:12:49 PM PDT 24	78400308392 ps
T69	/workspace/coverage/default/0.chip_tap_straps_prod.854792206			May 02 04:42:59 PM PDT 24	May 02 04:54:03 PM PDT 24	6429663846 ps
T6	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2936337307			May 02 04:51:37 PM PDT 24	May 02 04:56:15 PM PDT 24	3449225470 ps
T146	/workspace/coverage/default/2.chip_plic_all_irqs_10.1856710991			May 02 04:59:39 PM PDT 24	May 02 05:10:29 PM PDT 24	4414164068 ps
T194	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2610655603			May 02 05:05:09 PM PDT 24	May 02 05:14:11 PM PDT 24	3440999620 ps
T616	/workspace/coverage/default/92.chip_sw_all_escalation_resets.4284491267			May 02 05:07:10 PM PDT 24	May 02 05:14:00 PM PDT 24	5401316000 ps
T294	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1080164596			May 02 04:41:23 PM PDT 24	May 02 04:51:39 PM PDT 24	4720448844 ps
T317	/workspace/coverage/default/1.chip_sw_hmac_enc.3047683233			May 02 04:49:55 PM PDT 24	May 02 04:53:40 PM PDT 24	3046781062 ps
T725	/workspace/coverage/default/42.chip_sw_all_escalation_resets.194594853			May 02 05:04:50 PM PDT 24	May 02 05:14:53 PM PDT 24	5205574192 ps
T177	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.846477727			May 02 04:47:35 PM PDT 24	May 02 04:59:35 PM PDT 24	5251385502 ps
T645	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3324339596			May 02 04:52:58 PM PDT 24	May 02 04:59:20 PM PDT 24	3032455322 ps
T19	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3441180548			May 02 04:45:17 PM PDT 24	May 02 05:12:00 PM PDT 24	24073875650 ps
T202	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.565948547			May 02 04:54:05 PM PDT 24	May 02 05:13:40 PM PDT 24	8323366428 ps
T70	/workspace/coverage/default/4.chip_tap_straps_prod.2127624019			May 02 04:59:11 PM PDT 24	May 02 05:19:15 PM PDT 24	10386043915 ps
T619	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.987756784			May 02 05:07:02 PM PDT 24	May 02 05:13:46 PM PDT 24	2975704924 ps
T13	/workspace/coverage/default/0.chip_sw_gpio_smoketest.3013428955			May 02 04:42:51 PM PDT 24	May 02 04:46:58 PM PDT 24	2902271240 ps
T629	/workspace/coverage/default/0.chip_sw_aes_smoketest.1661545024			May 02 04:43:06 PM PDT 24	May 02 04:46:52 PM PDT 24	2644874618 ps
T118	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.397591790			May 02 04:48:21 PM PDT 24	May 02 04:59:13 PM PDT 24	4312166230 ps
T825	/workspace/coverage/default/1.chip_tap_straps_dev.1739146672			May 02 04:48:02 PM PDT 24	May 02 04:50:33 PM PDT 24	2623086908 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3968273568			May 02 04:48:44 PM PDT 24	May 02 05:38:51 PM PDT 24	21019407316 ps
T607	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.55874568			May 02 05:03:49 PM PDT 24	May 02 05:09:04 PM PDT 24	3193268656 ps
T178	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.74648871			May 02 04:40:22 PM PDT 24	May 02 04:46:09 PM PDT 24	2897248131 ps
T313	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4111982642			May 02 05:03:00 PM PDT 24	May 02 05:11:15 PM PDT 24	4860453716 ps
T304	/workspace/coverage/default/2.chip_sw_otbn_randomness.4259115750			May 02 04:55:01 PM PDT 24	May 02 05:12:07 PM PDT 24	5444296824 ps
T826	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1469456991			May 02 04:48:40 PM PDT 24	May 02 05:00:37 PM PDT 24	7033377002 ps
T82	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653835721			May 02 05:04:14 PM PDT 24	May 02 05:11:14 PM PDT 24	3862204444 ps
T827	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.197208495			May 02 04:56:48 PM PDT 24	May 02 05:02:26 PM PDT 24	2842824160 ps
T195	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2676464278			May 02 05:04:47 PM PDT 24	May 02 05:14:56 PM PDT 24	5515087800 ps
T14	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3916284426			May 02 05:03:19 PM PDT 24	May 02 05:12:56 PM PDT 24	3959972582 ps
T295	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.716112344			May 02 04:45:18 PM PDT 24	May 02 04:54:37 PM PDT 24	4013477117 ps
T175	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1132573411			May 02 04:55:11 PM PDT 24	May 02 06:20:33 PM PDT 24	48924238360 ps
T828	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2876276741			May 02 04:58:03 PM PDT 24	May 02 05:15:07 PM PDT 24	6799282107 ps
T214	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1015202237			May 02 05:05:51 PM PDT 24	May 02 05:15:55 PM PDT 24	5737032274 ps
T119	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1602946150			May 02 04:58:42 PM PDT 24	May 02 05:08:10 PM PDT 24	5125519760 ps
T157	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.892183010			May 02 04:40:07 PM PDT 24	May 02 04:42:50 PM PDT 24	3294886545 ps
T618	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177922884			May 02 05:05:00 PM PDT 24	May 02 05:11:12 PM PDT 24	3245648094 ps
T336	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1930228095			May 02 05:05:35 PM PDT 24	May 02 05:15:05 PM PDT 24	5497454938 ps
T267	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.458418367			May 02 04:49:26 PM PDT 24	May 02 04:53:44 PM PDT 24	2635711832 ps
T318	/workspace/coverage/default/0.chip_sw_hmac_enc.3790012480			May 02 04:44:54 PM PDT 24	May 02 04:48:55 PM PDT 24	2231336316 ps
T349	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.909448201			May 02 04:54:52 PM PDT 24	May 02 05:01:04 PM PDT 24	3198499100 ps
T350	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.368785599			May 02 04:49:13 PM PDT 24	May 02 05:21:18 PM PDT 24	26361604660 ps
T351	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2995025352			May 02 05:05:01 PM PDT 24	May 02 05:13:17 PM PDT 24	3914419370 ps
T352	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3653785819			May 02 04:40:40 PM PDT 24	May 02 04:59:52 PM PDT 24	5579603188 ps
T353	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1712446225			May 02 04:57:02 PM PDT 24	May 02 05:07:59 PM PDT 24	6084107656 ps
T168	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3186250899			May 02 04:45:01 PM PDT 24	May 02 04:54:09 PM PDT 24	3188361092 ps
T143	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.462374135			May 02 04:41:27 PM PDT 24	May 02 05:38:56 PM PDT 24	17547144860 ps
T324	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2002151654			May 02 05:03:32 PM PDT 24	May 02 05:11:54 PM PDT 24	5755141372 ps
T829	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2453334573			May 02 04:41:10 PM PDT 24	May 02 04:57:48 PM PDT 24	5466523864 ps
T35	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2360212834			May 02 04:41:20 PM PDT 24	May 02 04:51:17 PM PDT 24	5883041432 ps
T830	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.356736244			May 02 04:49:16 PM PDT 24	May 02 05:00:02 PM PDT 24	4802594152 ps
T322	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2111544333			May 02 05:01:30 PM PDT 24	May 02 05:11:49 PM PDT 24	5032737176 ps
T151	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3115040665			May 02 04:43:48 PM PDT 24	May 02 07:48:23 PM PDT 24	254081083224 ps
T163	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2468156077			May 02 04:57:22 PM PDT 24	May 02 05:11:00 PM PDT 24	7909779330 ps
T831	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1205555799			May 02 04:45:46 PM PDT 24	May 02 04:52:26 PM PDT 24	4569634944 ps
T474	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2816560297			May 02 04:52:59 PM PDT 24	May 02 04:59:59 PM PDT 24	5706476788 ps
T9	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4043891705			May 02 04:44:38 PM PDT 24	May 02 04:49:30 PM PDT 24	2956013446 ps
T832	/workspace/coverage/default/3.chip_tap_straps_dev.3057812269			May 02 05:00:56 PM PDT 24	May 02 05:03:48 PM PDT 24	3077272976 ps
T601	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2863970713			May 02 05:07:44 PM PDT 24	May 02 05:17:22 PM PDT 24	5592895980 ps
T833	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3359367129			May 02 04:49:48 PM PDT 24	May 02 05:08:23 PM PDT 24	5239196292 ps
T83	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3110343938			May 02 04:55:18 PM PDT 24	May 02 05:02:00 PM PDT 24	3811389419 ps
T171	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1234062538			May 02 04:41:40 PM PDT 24	May 02 04:53:02 PM PDT 24	6350839080 ps
T689	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.203053431			May 02 04:47:26 PM PDT 24	May 02 05:06:53 PM PDT 24	6646462664 ps
T205	/workspace/coverage/default/1.chip_sw_flash_init.2895589678			May 02 04:48:31 PM PDT 24	May 02 05:19:52 PM PDT 24	20805361736 ps
T694	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754722266			May 02 05:04:29 PM PDT 24	May 02 05:11:08 PM PDT 24	3653940342 ps
T137	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.722416235			May 02 04:43:24 PM PDT 24	May 02 04:49:05 PM PDT 24	2416303615 ps
T228	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3261569646			May 02 04:47:57 PM PDT 24	May 02 04:51:46 PM PDT 24	2103830108 ps
T834	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.153373161			May 02 05:01:27 PM PDT 24	May 02 05:19:08 PM PDT 24	10485941691 ps
T665	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.811299799			May 02 05:02:25 PM PDT 24	May 02 05:10:06 PM PDT 24	3661718720 ps
T675	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1182667020			May 02 04:42:15 PM PDT 24	May 02 04:47:18 PM PDT 24	3032670928 ps
T835	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.110344407			May 02 05:02:09 PM PDT 24	May 02 05:14:18 PM PDT 24	8475187428 ps
T617	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1208467051			May 02 05:01:39 PM PDT 24	May 02 05:10:10 PM PDT 24	4521301856 ps
T836	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2638322860			May 02 04:50:39 PM PDT 24	May 02 04:55:09 PM PDT 24	2299515081 ps
T236	/workspace/coverage/default/1.chip_sw_edn_boot_mode.47903768			May 02 04:46:46 PM PDT 24	May 02 04:56:17 PM PDT 24	2682719040 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1128222427			May 02 05:01:05 PM PDT 24	May 02 05:21:53 PM PDT 24	19209361528 ps
T209	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1643225487			May 02 04:42:36 PM PDT 24	May 02 06:11:46 PM PDT 24	47722089845 ps
T837	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2879260709			May 02 04:54:00 PM PDT 24	May 02 04:59:05 PM PDT 24	3789882772 ps
T838	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2565642766			May 02 04:47:27 PM PDT 24	May 02 05:03:39 PM PDT 24	8244068652 ps
T839	/workspace/coverage/default/0.chip_sw_example_concurrency.3321600222			May 02 04:44:15 PM PDT 24	May 02 04:48:15 PM PDT 24	2617995940 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2680866251			May 02 04:59:50 PM PDT 24	May 02 05:06:16 PM PDT 24	5125854106 ps
T115	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3643711386			May 02 04:41:26 PM PDT 24	May 02 05:11:11 PM PDT 24	9244718230 ps
T356	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3111623162			May 02 04:39:59 PM PDT 24	May 02 04:46:10 PM PDT 24	3033205594 ps
T840	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.832794364			May 02 04:44:05 PM PDT 24	May 02 04:47:48 PM PDT 24	1934234256 ps
T67	/workspace/coverage/default/3.chip_tap_straps_rma.1975216082			May 02 05:05:27 PM PDT 24	May 02 05:15:26 PM PDT 24	6844426028 ps
T841	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.404159487			May 02 04:40:36 PM PDT 24	May 02 04:47:34 PM PDT 24	4083180520 ps
T842	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3465033557			May 02 05:03:45 PM PDT 24	May 02 05:26:28 PM PDT 24	8125691688 ps
T690	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2520330104			May 02 05:04:25 PM PDT 24	May 02 05:13:24 PM PDT 24	4927426906 ps
T357	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3749491130			May 02 04:44:37 PM PDT 24	May 02 05:00:52 PM PDT 24	5657498413 ps
T843	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1298381264			May 02 04:44:20 PM PDT 24	May 02 04:49:52 PM PDT 24	2983285917 ps
T275	/workspace/coverage/default/0.chip_plic_all_irqs_20.2985176743			May 02 04:42:54 PM PDT 24	May 02 04:59:10 PM PDT 24	4002304464 ps
T844	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3761662907			May 02 04:43:15 PM PDT 24	May 02 04:49:36 PM PDT 24	3885635288 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.622361676			May 02 04:40:37 PM PDT 24	May 02 04:48:52 PM PDT 24	5024501476 ps
T631	/workspace/coverage/default/0.chip_sw_hmac_smoketest.28838661			May 02 04:44:21 PM PDT 24	May 02 04:50:48 PM PDT 24	3621473764 ps
T845	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2299285399			May 02 04:51:19 PM PDT 24	May 02 04:54:20 PM PDT 24	2834442030 ps
T846	/workspace/coverage/default/1.chip_sw_otbn_randomness.892005186			May 02 04:48:57 PM PDT 24	May 02 05:03:22 PM PDT 24	6156194728 ps
T847	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2124269196			May 02 04:56:05 PM PDT 24	May 02 05:04:56 PM PDT 24	6686691000 ps
T338	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3302860783			May 02 05:03:09 PM PDT 24	May 02 05:09:24 PM PDT 24	2879141708 ps
T697	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2851872307			May 02 05:01:06 PM PDT 24	May 02 05:10:52 PM PDT 24	4226744760 ps
T182	/workspace/coverage/default/1.chip_sw_pattgen_ios.2282242332			May 02 04:44:50 PM PDT 24	May 02 04:50:45 PM PDT 24	2856529584 ps
T183	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.869726608			May 02 04:45:49 PM PDT 24	May 02 05:11:21 PM PDT 24	8701023752 ps
T187	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2103172360			May 02 05:00:27 PM PDT 24	May 02 05:08:02 PM PDT 24	3891290321 ps
T621	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1211568320			May 02 05:07:27 PM PDT 24	May 02 05:13:03 PM PDT 24	3891141708 ps
T287	/workspace/coverage/default/0.chip_plic_all_irqs_0.2246003415			May 02 04:41:59 PM PDT 24	May 02 05:04:07 PM PDT 24	6455861220 ps
T660	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906909473			May 02 05:01:43 PM PDT 24	May 02 05:07:50 PM PDT 24	3342455168 ps
T24	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.389227968			May 02 04:44:14 PM PDT 24	May 02 04:48:26 PM PDT 24	2813487244 ps
T144	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3299805769			May 02 04:39:55 PM PDT 24	May 02 04:55:29 PM PDT 24	6284181696 ps
T48	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1645475353			May 02 04:46:42 PM PDT 24	May 02 04:56:31 PM PDT 24	5527012654 ps
T290	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3213675333			May 02 05:02:39 PM PDT 24	May 02 05:11:54 PM PDT 24	3812332532 ps
T368	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4149412702			May 02 05:06:53 PM PDT 24	May 02 05:11:54 PM PDT 24	3393891848 ps
T369	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3948603339			May 02 04:41:40 PM PDT 24	May 02 04:46:12 PM PDT 24	3338680552 ps
T370	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3698628964			May 02 04:44:35 PM PDT 24	May 02 05:08:30 PM PDT 24	16568334832 ps
T339	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1722635785			May 02 05:05:28 PM PDT 24	May 02 05:11:13 PM PDT 24	3851821432 ps
T188	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1698890899			May 02 05:01:07 PM PDT 24	May 02 05:39:09 PM PDT 24	13289296376 ps
T358	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1323067362			May 02 04:44:51 PM PDT 24	May 02 05:09:30 PM PDT 24	4664403144 ps
T371	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1781361840			May 02 04:49:19 PM PDT 24	May 02 04:54:14 PM PDT 24	2802910098 ps
T218	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4232462959			May 02 04:48:31 PM PDT 24	May 02 04:53:04 PM PDT 24	2262284418 ps
T579	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.777836302			May 02 04:51:30 PM PDT 24	May 02 04:55:27 PM PDT 24	2299649188 ps
T215	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1289725652			May 02 05:07:54 PM PDT 24	May 02 05:15:39 PM PDT 24	5624951032 ps
T242	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2346014102			May 02 05:01:24 PM PDT 24	May 02 05:10:06 PM PDT 24	4361250408 ps
T243	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1585705028			May 02 04:59:39 PM PDT 24	May 02 05:09:01 PM PDT 24	4204946672 ps
T208	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1710395710			May 02 04:40:27 PM PDT 24	May 02 06:06:42 PM PDT 24	48437119212 ps
T51	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.755853782			May 02 04:51:11 PM PDT 24	May 02 04:59:51 PM PDT 24	7365526072 ps
T244	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.262720774			May 02 05:01:50 PM PDT 24	May 02 05:08:13 PM PDT 24	3979138344 ps
T245	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1154520188			May 02 04:40:44 PM PDT 24	May 02 04:53:58 PM PDT 24	4116873072 ps
T246	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2969080018			May 02 04:59:03 PM PDT 24	May 02 05:03:37 PM PDT 24	2873744460 ps
T247	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.659193453			May 02 05:08:35 PM PDT 24	May 02 05:15:23 PM PDT 24	3480049044 ps
T206	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1118558000			May 02 04:46:55 PM PDT 24	May 02 06:16:15 PM PDT 24	46589519930 ps
T848	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4105760857			May 02 04:40:36 PM PDT 24	May 02 04:51:59 PM PDT 24	4583335590 ps
T685	/workspace/coverage/default/34.chip_sw_all_escalation_resets.579957817			May 02 05:03:02 PM PDT 24	May 02 05:11:04 PM PDT 24	3894770920 ps
T849	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3106842927			May 02 04:47:23 PM PDT 24	May 02 04:57:41 PM PDT 24	4903610968 ps
T850	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1017184859			May 02 04:44:32 PM PDT 24	May 02 04:56:59 PM PDT 24	5280336540 ps
T851	/workspace/coverage/default/0.rom_keymgr_functest.1837790226			May 02 04:42:34 PM PDT 24	May 02 04:48:00 PM PDT 24	4263726200 ps
T158	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3770059377			May 02 04:40:03 PM PDT 24	May 02 04:44:12 PM PDT 24	3331046209 ps
T683	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643881776			May 02 05:02:58 PM PDT 24	May 02 05:10:27 PM PDT 24	3518623576 ps
T599	/workspace/coverage/default/0.chip_sw_aes_masking_off.2264478780			May 02 04:47:24 PM PDT 24	May 02 04:52:00 PM PDT 24	2390081664 ps
T852	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.562846818			May 02 05:00:03 PM PDT 24	May 02 05:23:35 PM PDT 24	13136747771 ps
T399	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3178656039			May 02 04:52:09 PM PDT 24	May 02 04:56:43 PM PDT 24	2195932692 ps
T853	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.102632274			May 02 04:57:23 PM PDT 24	May 02 05:01:17 PM PDT 24	2608381488 ps
T734	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.935478100			May 02 05:02:58 PM PDT 24	May 02 05:08:46 PM PDT 24	3771238208 ps
T185	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3127233086			May 02 04:52:43 PM PDT 24	May 02 08:41:26 PM PDT 24	77261894980 ps
T693	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1169913402			May 02 05:03:38 PM PDT 24	May 02 05:12:38 PM PDT 24	5258359604 ps
T854	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.668462922			May 02 05:01:52 PM PDT 24	May 02 05:28:06 PM PDT 24	8194946626 ps
T396	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1682594168			May 02 04:56:21 PM PDT 24	May 02 05:00:18 PM PDT 24	3322456000 ps
T124	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.636594078			May 02 04:43:38 PM PDT 24	May 02 04:52:11 PM PDT 24	5938948240 ps
T196	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.247017083			May 02 04:57:09 PM PDT 24	May 02 05:25:28 PM PDT 24	9142590320 ps
T340	/workspace/coverage/default/58.chip_sw_all_escalation_resets.336361667			May 02 05:05:41 PM PDT 24	May 02 05:13:26 PM PDT 24	4851530056 ps
T855	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2667760448			May 02 04:41:31 PM PDT 24	May 02 05:33:01 PM PDT 24	25550890250 ps
T84	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1840573357			May 02 04:41:42 PM PDT 24	May 02 04:57:50 PM PDT 24	10057190308 ps
T856	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.192450438			May 02 04:48:09 PM PDT 24	May 02 04:52:00 PM PDT 24	2969325962 ps
T857	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3818017040			May 02 04:50:04 PM PDT 24	May 02 05:09:46 PM PDT 24	5284494600 ps
T64	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2204957714			May 02 04:57:17 PM PDT 24	May 02 05:02:09 PM PDT 24	3349862840 ps
T858	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.727876511			May 02 04:39:12 PM PDT 24	May 02 04:45:32 PM PDT 24	3383709596 ps
T691	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1566850916			May 02 05:01:36 PM PDT 24	May 02 05:07:00 PM PDT 24	3313584900 ps
T692	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.86884494			May 02 04:55:15 PM PDT 24	May 02 05:02:38 PM PDT 24	4116996844 ps
T859	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3317901530			May 02 04:46:28 PM PDT 24	May 02 04:54:15 PM PDT 24	5325550032 ps
T860	/workspace/coverage/default/1.chip_sw_hmac_smoketest.2653277593			May 02 04:50:53 PM PDT 24	May 02 04:57:23 PM PDT 24	2787740400 ps
T861	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.900406019			May 02 04:47:22 PM PDT 24	May 02 04:54:36 PM PDT 24	3663018366 ps
T68	/workspace/coverage/default/0.chip_tap_straps_rma.905024608			May 02 04:41:27 PM PDT 24	May 02 04:48:29 PM PDT 24	4966747529 ps
T862	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3734971599			May 02 04:58:58 PM PDT 24	May 02 05:02:46 PM PDT 24	2406529580 ps
T863	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2638285638			May 02 05:02:01 PM PDT 24	May 02 05:11:42 PM PDT 24	4532640858 ps
T864	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3971738323			May 02 04:40:09 PM PDT 24	May 02 05:10:04 PM PDT 24	8029764260 ps
T359	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4016159887			May 02 04:46:57 PM PDT 24	May 02 05:24:56 PM PDT 24	10684560880 ps
T248	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.923880315			May 02 04:54:30 PM PDT 24	May 02 04:56:31 PM PDT 24	1962911732 ps