Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142353	1			T74	24		T75	5		T80	9
values[2]	11927	1			T387	1		T456	2		T367	2
values[3]	5202	1			T604	7		T585	5		T786	30
values[4]	2772	1			T585	7		T786	9		T385	60
values[5]	1701	1			T585	4		T786	16		T385	16
values[6]	1154	1			T585	19		T786	1		T385	2
values[7]	913	1			T585	6		T762	1		T425	32
values[8]	774	1			T585	4		T762	1		T425	23
values[9]	503	1			T585	4		T762	1		T425	7
values[10]	483	1			T585	3		T762	1		T425	2
values[11]	447	1			T585	8		T762	1		T425	5
values[12]	313	1			T585	6		T762	1		T425	4
values[13]	369	1			T585	6		T762	1		T764	6
values[14]	396	1			T585	12		T762	1		T764	11
values[15]	321	1			T585	3		T762	1		T764	6
values[16]	308	1			T585	5		T762	1		T764	14
values[17]	289	1			T585	12		T762	1		T764	12
values[18]	342	1			T585	12		T762	1		T764	9
values[19]	321	1			T585	6		T762	1		T764	21
values[20]	344	1			T585	3		T762	1		T764	6
values[21]	389	1			T585	20		T762	1		T764	7
values[22]	297	1			T585	7		T762	1		T764	12
values[23]	336	1			T585	6		T762	1		T764	7
values[24]	300	1			T585	6		T762	1		T764	5
values[25]	280	1			T585	5		T762	1		T764	5
values[26]	393	1			T585	19		T762	1		T764	13
values[27]	336	1			T585	5		T762	1		T764	17
values[28]	279	1			T585	9		T762	1		T764	12
values[29]	313	1			T585	6		T762	1		T764	8
values[30]	312	1			T585	11		T762	1		T764	9
values[31]	344	1			T585	15		T762	1		T764	11
values[32]	296	1			T585	8		T762	1		T764	5
values[33]	294	1			T585	8		T762	1		T764	8
values[34]	298	1			T585	11		T762	1		T764	9
values[35]	294	1			T585	10		T762	1		T764	4
values[36]	257	1			T585	4		T762	1		T764	8
values[37]	282	1			T585	12		T762	1		T764	14
values[38]	254	1			T585	5		T762	1		T764	7
values[39]	278	1			T585	3		T762	1		T764	10
values[40]	318	1			T585	5		T762	1		T764	13
values[41]	270	1			T585	3		T762	1		T764	21
values[42]	287	1			T585	6		T762	1		T764	15
values[43]	313	1			T585	6		T762	1		T764	16
values[44]	268	1			T585	7		T762	1		T764	17
values[45]	258	1			T585	12		T762	1		T764	6
values[46]	263	1			T585	15		T762	1		T764	7
values[47]	235	1			T585	13		T762	1		T764	3
values[48]	242	1			T585	4		T762	1		T764	6
values[49]	266	1			T585	9		T762	1		T764	4
values[50]	220	1			T585	4		T762	1		T764	4
values[51]	261	1			T585	5		T762	1		T764	3
values[52]	275	1			T585	15		T762	1		T764	7
values[53]	297	1			T585	12		T762	1		T764	9
values[54]	252	1			T585	8		T762	1		T764	7
values[55]	278	1			T585	7		T762	1		T764	5
values[56]	241	1			T585	6		T762	1		T764	2
values[57]	287	1			T585	15		T762	1		T764	2
values[58]	234	1			T585	5		T762	1		T764	2
values[59]	247	1			T585	9		T762	1		T764	1
values[60]	256	1			T585	5		T762	1		T764	4
values[61]	239	1			T585	3		T762	1		T764	10
values[62]	226	1			T585	5		T762	1		T764	17
values[63]	258	1			T585	5		T762	1		T764	18
values[64]	239	1			T585	3		T762	1		T764	34
values[65]	213	1			T585	3		T762	1		T764	21
values[66]	187	1			T585	1		T762	1		T423	6
values[67]	197	1			T762	1		T423	4		T538	19
values[68]	152	1			T762	1		T423	18		T538	14
values[69]	128	1			T762	1		T423	9		T538	13
values[70]	114	1			T762	1		T423	12		T538	16
values[71]	112	1			T762	1		T423	19		T538	3
values[72]	98	1			T762	1		T423	11		T538	2
values[73]	112	1			T762	1		T423	8		T767	3
values[74]	94	1			T762	1		T423	4		T767	1
values[75]	73	1			T762	1		T423	3		T767	3
values[76]	64	1			T762	1		T423	6		T767	4
values[77]	85	1			T762	1		T423	5		T767	7
values[78]	87	1			T762	1		T423	6		T767	1
values[79]	78	1			T762	1		T423	5		T767	3
values[80]	70	1			T762	1		T423	9		T767	2
values[81]	90	1			T762	1		T423	10		T767	2
values[82]	87	1			T762	1		T423	8		T767	3
values[83]	69	1			T762	1		T423	10		T767	2
values[84]	78	1			T762	1		T423	3		T767	4
values[85]	87	1			T762	1		T423	4		T767	2
values[86]	102	1			T762	1		T423	8		T767	2
values[87]	104	1			T762	1		T423	10		T767	4
values[88]	83	1			T762	2		T423	7		T767	3
values[89]	81	1			T762	1		T423	2		T767	3
values[90]	82	1			T762	1		T423	3		T767	2
values[91]	74	1			T762	1		T423	3		T767	3
values[92]	77	1			T762	1		T423	6		T767	1
values[93]	74	1			T762	1		T423	4		T767	2
values[94]	98	1			T762	1		T423	4		T767	2
values[95]	107	1			T762	1		T423	6		T767	1
values[96]	108	1			T762	1		T423	7		T767	8
values[97]	95	1			T762	1		T423	2		T767	11
values[98]	83	1			T762	1		T423	3		T767	4
values[99]	81	1			T762	1		T423	8		T767	3
values[100]	84	1			T762	1		T423	3		T767	5
values[101]	78	1			T762	1		T423	3		T767	3
values[102]	93	1			T762	1		T423	9		T767	5
values[103]	75	1			T762	1		T423	4		T767	6
values[104]	76	1			T762	1		T423	3		T767	9
values[105]	73	1			T762	1		T423	1		T767	6
values[106]	72	1			T762	1		T767	4		T770	1
values[107]	66	1			T762	1		T767	4		T770	3
values[108]	68	1			T762	1		T767	3		T770	5
values[109]	67	1			T762	1		T767	4		T770	8
values[110]	81	1			T762	1		T767	10		T770	6
values[111]	73	1			T762	1		T767	3		T770	7
values[112]	72	1			T762	1		T767	3		T770	3
values[113]	74	1			T762	2		T767	2		T770	1
values[114]	69	1			T762	2		T767	1		T770	4
values[115]	58	1			T762	1		T767	2		T770	2
values[116]	66	1			T762	1		T767	2		T770	2
values[117]	81	1			T762	2		T767	1		T770	3
values[118]	74	1			T762	2		T767	4		T770	2
values[119]	82	1			T762	2		T767	5		T770	5
values[120]	74	1			T762	12		T767	2		T770	4
values[121]	82	1			T762	3		T767	4		T770	3
values[122]	83	1			T762	1		T767	5		T770	2
values[123]	79	1			T762	1		T767	3		T770	1
values[124]	72	1			T762	1		T767	1		T770	5
values[125]	70	1			T762	1		T767	7		T770	2
values[126]	125	1			T762	1		T767	18		T770	5
values[127]	793	1			T762	30		T767	57		T770	14
values[128]	6786	1			T762	373		T767	20		T770	3