Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142037	1			T74	21		T75	3		T80	9
values[2]	10182	1			T122	13		T456	1		T367	3
values[3]	3934	1			T476	23		T475	40		T366	42
values[4]	2155	1			T476	9		T475	25		T366	3
values[5]	1414	1			T476	3		T475	21		T604	9
values[6]	916	1			T475	12		T604	6		T585	11
values[7]	756	1			T475	9		T604	9		T585	17
values[8]	632	1			T475	3		T604	9		T585	4
values[9]	509	1			T475	4		T604	3		T585	5
values[10]	537	1			T475	4		T604	3		T585	9
values[11]	448	1			T475	3		T604	3		T585	3
values[12]	379	1			T475	4		T604	4		T585	7
values[13]	420	1			T475	3		T604	15		T585	13
values[14]	447	1			T475	1		T604	23		T585	11
values[15]	442	1			T475	10		T604	4		T585	5
values[16]	411	1			T475	5		T604	6		T585	6
values[17]	414	1			T475	2		T604	5		T585	3
values[18]	372	1			T475	2		T604	11		T585	7
values[19]	441	1			T475	2		T604	8		T585	5
values[20]	434	1			T475	6		T604	6		T585	14
values[21]	395	1			T475	2		T604	6		T585	6
values[22]	413	1			T475	7		T604	5		T585	8
values[23]	368	1			T475	5		T604	7		T585	7
values[24]	358	1			T475	5		T604	4		T585	7
values[25]	409	1			T475	4		T604	13		T585	2
values[26]	406	1			T475	3		T604	22		T585	4
values[27]	383	1			T475	2		T604	8		T585	5
values[28]	404	1			T475	4		T604	6		T585	4
values[29]	368	1			T475	5		T604	8		T585	4
values[30]	390	1			T475	1		T604	5		T585	6
values[31]	344	1			T475	1		T604	4		T585	5
values[32]	341	1			T475	2		T604	2		T585	10
values[33]	374	1			T475	3		T604	3		T585	8
values[34]	408	1			T475	2		T604	8		T585	8
values[35]	328	1			T475	3		T604	9		T585	5
values[36]	384	1			T475	14		T604	8		T585	9
values[37]	331	1			T475	5		T604	17		T585	7
values[38]	372	1			T475	2		T604	12		T585	5
values[39]	343	1			T604	4		T585	4		T384	3
values[40]	382	1			T604	5		T585	14		T384	7
values[41]	335	1			T604	8		T585	5		T384	5
values[42]	410	1			T604	4		T585	9		T384	7
values[43]	382	1			T604	5		T585	3		T384	11
values[44]	381	1			T604	4		T585	4		T384	3
values[45]	374	1			T604	6		T585	14		T384	5
values[46]	326	1			T604	6		T585	4		T384	9
values[47]	373	1			T604	4		T585	3		T384	7
values[48]	342	1			T604	9		T585	8		T384	3
values[49]	368	1			T604	9		T585	17		T384	5
values[50]	322	1			T604	12		T585	14		T384	6
values[51]	340	1			T604	8		T585	9		T384	8
values[52]	318	1			T604	1		T585	9		T384	4
values[53]	345	1			T585	15		T384	13		T762	1
values[54]	328	1			T585	7		T384	8		T762	1
values[55]	311	1			T585	4		T384	10		T762	1
values[56]	296	1			T585	4		T384	3		T762	1
values[57]	266	1			T585	12		T384	14		T762	1
values[58]	245	1			T585	6		T384	4		T762	1
values[59]	222	1			T585	5		T384	6		T762	1
values[60]	243	1			T585	15		T384	3		T762	1
values[61]	224	1			T585	9		T384	6		T762	1
values[62]	241	1			T585	6		T384	5		T762	1
values[63]	187	1			T585	4		T384	3		T762	1
values[64]	156	1			T585	8		T384	8		T762	1
values[65]	177	1			T585	4		T384	6		T762	1
values[66]	214	1			T585	10		T384	1		T762	1
values[67]	184	1			T585	1		T762	1		T782	3
values[68]	164	1			T762	1		T782	3		T412	1
values[69]	149	1			T762	1		T782	4		T412	1
values[70]	160	1			T762	1		T782	7		T412	1
values[71]	145	1			T762	1		T782	9		T412	1
values[72]	135	1			T762	1		T782	7		T412	1
values[73]	133	1			T762	1		T782	7		T412	1
values[74]	125	1			T762	1		T782	1		T412	1
values[75]	121	1			T762	1		T412	1		T538	1
values[76]	109	1			T762	1		T412	1		T441	1
values[77]	112	1			T762	1		T412	1		T441	1
values[78]	101	1			T762	1		T412	1		T441	1
values[79]	127	1			T762	1		T412	1		T441	1
values[80]	118	1			T762	1		T412	1		T441	1
values[81]	118	1			T762	1		T412	1		T441	1
values[82]	102	1			T762	1		T412	1		T441	1
values[83]	98	1			T762	1		T412	1		T441	1
values[84]	95	1			T762	1		T412	1		T441	1
values[85]	76	1			T762	1		T412	2		T441	1
values[86]	89	1			T762	1		T412	1		T441	1
values[87]	100	1			T762	1		T412	1		T441	1
values[88]	87	1			T762	1		T412	1		T441	1
values[89]	92	1			T762	1		T412	3		T441	1
values[90]	107	1			T762	1		T412	5		T441	1
values[91]	89	1			T762	1		T412	2		T441	1
values[92]	108	1			T762	1		T412	8		T441	1
values[93]	86	1			T762	1		T412	2		T441	1
values[94]	81	1			T762	1		T412	6		T441	1
values[95]	89	1			T762	1		T412	5		T441	1
values[96]	97	1			T762	1		T412	4		T441	1
values[97]	91	1			T762	1		T412	2		T441	1
values[98]	79	1			T762	1		T412	2		T441	1
values[99]	90	1			T762	1		T412	2		T441	1
values[100]	108	1			T762	1		T412	2		T441	1
values[101]	81	1			T762	1		T412	2		T441	1
values[102]	91	1			T762	2		T412	1		T441	1
values[103]	93	1			T762	1		T412	1		T441	1
values[104]	111	1			T762	1		T412	5		T441	1
values[105]	104	1			T762	1		T412	4		T441	1
values[106]	100	1			T762	1		T412	9		T441	1
values[107]	92	1			T762	1		T412	1		T441	4
values[108]	84	1			T762	1		T412	2		T441	2
values[109]	69	1			T762	1		T412	1		T441	1
values[110]	75	1			T762	1		T412	1		T441	1
values[111]	95	1			T762	1		T412	7		T441	2
values[112]	91	1			T762	1		T412	1		T441	2
values[113]	76	1			T762	1		T412	1		T441	1
values[114]	83	1			T762	1		T412	3		T441	1
values[115]	73	1			T762	1		T412	1		T441	1
values[116]	88	1			T762	1		T412	1		T441	2
values[117]	81	1			T762	1		T412	1		T441	3
values[118]	63	1			T762	1		T412	1		T441	2
values[119]	69	1			T762	1		T412	1		T441	1
values[120]	85	1			T762	1		T412	3		T441	2
values[121]	82	1			T762	1		T412	2		T441	1
values[122]	114	1			T762	1		T412	2		T441	4
values[123]	104	1			T762	1		T412	3		T441	2
values[124]	95	1			T762	1		T412	1		T441	3
values[125]	88	1			T762	1		T412	1		T441	3
values[126]	138	1			T762	1		T412	4		T441	5
values[127]	892	1			T762	31		T412	27		T441	26
values[128]	6962	1			T762	260		T412	285		T441	314