Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141959	1			T74	28		T75	1		T80	16
values[2]	9182	1			T80	1		T122	1		T456	2
values[3]	4515	1			T585	22		T696	69		T384	51
values[4]	2674	1			T585	21		T696	60		T384	46
values[5]	1692	1			T585	23		T696	14		T384	11
values[6]	1052	1			T585	20		T696	11		T384	17
values[7]	840	1			T585	30		T696	4		T384	4
values[8]	812	1			T585	28		T696	1		T764	1
values[9]	747	1			T585	8		T548	24		T788	1
values[10]	631	1			T585	38		T548	18		T788	1
values[11]	620	1			T585	26		T548	36		T788	1
values[12]	594	1			T585	19		T548	22		T788	1
values[13]	592	1			T585	12		T548	11		T788	1
values[14]	481	1			T585	15		T548	11		T788	1
values[15]	607	1			T585	22		T548	10		T788	1
values[16]	640	1			T585	26		T548	26		T788	1
values[17]	588	1			T585	12		T548	18		T788	1
values[18]	542	1			T585	29		T548	19		T788	1
values[19]	531	1			T585	29		T548	20		T788	1
values[20]	561	1			T585	23		T548	41		T788	1
values[21]	579	1			T585	22		T548	24		T788	1
values[22]	590	1			T585	20		T548	7		T788	1
values[23]	529	1			T585	18		T548	12		T788	1
values[24]	466	1			T585	19		T548	13		T788	1
values[25]	505	1			T585	14		T548	36		T788	1
values[26]	534	1			T585	14		T548	13		T788	1
values[27]	549	1			T585	20		T548	4		T788	1
values[28]	510	1			T585	33		T548	4		T788	1
values[29]	558	1			T585	38		T548	9		T788	1
values[30]	530	1			T585	12		T548	7		T788	1
values[31]	455	1			T585	21		T548	10		T788	1
values[32]	503	1			T585	18		T548	11		T788	1
values[33]	402	1			T585	7		T548	5		T788	1
values[34]	406	1			T585	20		T548	3		T788	1
values[35]	505	1			T585	26		T548	15		T788	1
values[36]	511	1			T585	15		T548	7		T788	1
values[37]	476	1			T585	10		T548	27		T788	1
values[38]	540	1			T585	18		T548	4		T788	1
values[39]	474	1			T585	13		T548	8		T788	1
values[40]	451	1			T585	24		T548	7		T788	1
values[41]	432	1			T585	16		T548	9		T788	1
values[42]	408	1			T585	27		T548	18		T788	1
values[43]	341	1			T585	18		T548	6		T788	1
values[44]	358	1			T585	18		T788	1		T771	1
values[45]	305	1			T585	21		T788	1		T771	1
values[46]	427	1			T585	34		T788	1		T771	1
values[47]	320	1			T585	12		T788	1		T771	1
values[48]	306	1			T585	4		T788	1		T771	1
values[49]	255	1			T788	1		T771	1		T789	10
values[50]	207	1			T788	1		T771	1		T789	7
values[51]	193	1			T788	1		T771	1		T789	9
values[52]	160	1			T788	1		T771	1		T789	11
values[53]	151	1			T788	1		T771	1		T789	1
values[54]	102	1			T788	1		T771	1		T411	7
values[55]	106	1			T788	1		T771	1		T411	13
values[56]	129	1			T788	1		T771	1		T411	11
values[57]	101	1			T788	1		T771	1		T411	6
values[58]	87	1			T788	1		T771	1		T411	4
values[59]	76	1			T788	1		T771	1		T411	1
values[60]	77	1			T788	1		T771	1		T411	7
values[61]	86	1			T788	1		T771	1		T411	9
values[62]	101	1			T788	1		T771	1		T411	18
values[63]	78	1			T788	1		T771	1		T411	7
values[64]	70	1			T788	1		T771	1		T411	7
values[65]	76	1			T788	1		T771	1		T411	8
values[66]	77	1			T788	1		T771	1		T411	5
values[67]	77	1			T788	1		T771	1		T411	5
values[68]	91	1			T788	1		T771	1		T411	6
values[69]	93	1			T788	1		T771	1		T411	4
values[70]	84	1			T788	1		T771	1		T411	8
values[71]	99	1			T788	1		T771	1		T411	7
values[72]	103	1			T788	1		T771	1		T411	16
values[73]	116	1			T788	1		T771	1		T411	17
values[74]	122	1			T788	1		T771	1		T411	23
values[75]	113	1			T788	1		T771	1		T411	16
values[76]	119	1			T788	1		T771	1		T411	21
values[77]	139	1			T788	1		T771	1		T411	17
values[78]	129	1			T788	1		T771	1		T411	16
values[79]	106	1			T788	1		T771	1		T411	5
values[80]	99	1			T788	1		T771	1		T790	1
values[81]	98	1			T788	1		T771	1		T790	1
values[82]	101	1			T788	1		T771	1		T790	1
values[83]	89	1			T788	1		T771	1		T790	1
values[84]	63	1			T788	1		T771	1		T790	1
values[85]	77	1			T788	1		T771	1		T790	1
values[86]	83	1			T788	1		T771	1		T790	1
values[87]	85	1			T788	1		T771	2		T790	1
values[88]	82	1			T788	1		T771	1		T790	1
values[89]	94	1			T788	1		T771	1		T790	1
values[90]	84	1			T788	1		T771	1		T790	1
values[91]	85	1			T788	1		T771	1		T790	1
values[92]	81	1			T788	1		T771	2		T790	1
values[93]	97	1			T788	1		T771	1		T790	1
values[94]	76	1			T788	1		T771	1		T790	1
values[95]	94	1			T788	1		T771	1		T790	1
values[96]	101	1			T788	1		T771	1		T790	1
values[97]	82	1			T788	2		T771	1		T790	1
values[98]	84	1			T788	1		T771	1		T790	1
values[99]	78	1			T788	1		T771	1		T790	1
values[100]	77	1			T788	1		T771	1		T790	1
values[101]	73	1			T788	1		T771	1		T790	1
values[102]	72	1			T788	1		T771	1		T790	1
values[103]	84	1			T788	1		T771	1		T790	1
values[104]	56	1			T788	1		T771	1		T790	1
values[105]	60	1			T788	1		T771	1		T790	1
values[106]	62	1			T788	1		T771	1		T790	1
values[107]	58	1			T788	1		T771	1		T790	1
values[108]	62	1			T788	1		T771	1		T790	1
values[109]	71	1			T788	1		T771	1		T790	1
values[110]	80	1			T788	5		T771	1		T790	1
values[111]	71	1			T788	8		T771	1		T790	1
values[112]	70	1			T788	3		T771	1		T790	1
values[113]	60	1			T788	3		T771	1		T790	1
values[114]	57	1			T788	1		T771	1		T790	1
values[115]	67	1			T788	3		T771	1		T790	1
values[116]	76	1			T788	1		T771	1		T790	1
values[117]	71	1			T788	1		T771	1		T790	2
values[118]	85	1			T788	1		T771	1		T790	1
values[119]	62	1			T788	5		T771	1		T790	1
values[120]	56	1			T788	2		T771	1		T790	1
values[121]	63	1			T788	1		T771	1		T790	1
values[122]	79	1			T788	3		T771	4		T790	1
values[123]	64	1			T788	2		T771	6		T790	1
values[124]	73	1			T788	1		T771	3		T790	1
values[125]	67	1			T788	1		T771	5		T790	1
values[126]	145	1			T788	7		T771	4		T790	5
values[127]	1734	1			T788	58		T771	56		T790	53
values[128]	8160	1			T788	250		T771	296		T790	293