Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	481	1			T76	1		T80	1		T122	1
all_values[1]	494	1			T80	1		T122	2		T791	1
all_values[2]	473	1			T80	2		T122	3		T404	2
all_values[3]	471	1			T80	2		T122	3		T404	2
all_values[4]	533	1			T80	2		T122	3		T475	2
all_values[5]	481	1			T122	1		T476	1		T488	3
all_values[6]	527	1			T122	4		T404	1		T488	2
all_values[7]	457	1			T76	1		T80	2		T122	2
all_values[8]	467	1			T122	2		T488	3		T604	3
all_values[9]	506	1			T80	2		T224	1		T122	3
all_values[10]	484	1			T224	1		T122	2		T404	2
all_values[11]	518	1			T80	4		T366	1		T488	3
all_values[12]	481	1			T80	1		T122	1		T404	3
all_values[13]	526	1			T80	1		T122	2		T488	1
all_values[14]	493	1			T122	2		T404	1		T488	7
all_values[15]	442	1			T122	2		T404	2		T791	2
all_values[16]	501	1			T122	4		T404	3		T488	3
all_values[17]	480	1			T80	2		T122	2		T488	4
all_values[18]	487	1			T80	1		T122	1		T404	2
all_values[19]	484	1			T80	1		T122	1		T404	5
all_values[20]	496	1			T76	1		T122	2		T404	2
all_values[21]	517	1			T80	1		T122	2		T404	3
all_values[22]	497	1			T80	2		T224	1		T404	1
all_values[23]	486	1			T80	1		T122	2		T404	1
all_values[24]	500	1			T80	2		T224	1		T122	1
all_values[25]	507	1			T76	1		T80	1		T122	1
all_values[26]	469	1			T80	1		T224	1		T122	3
all_values[27]	524	1			T80	1		T122	4		T404	2
all_values[28]	465	1			T76	1		T80	2		T122	1
all_values[29]	500	1			T76	2		T80	1		T122	4
all_values[30]	468	1			T122	3		T404	2		T791	1
all_values[31]	515	1			T80	1		T122	2		T404	1
all_values[32]	449	1			T76	1		T80	1		T123	1
all_values[33]	508	1			T76	1		T80	3		T122	4
all_values[34]	495	1			T80	1		T404	1		T475	1
all_values[35]	473	1			T76	1		T80	1		T122	3
all_values[36]	474	1			T80	2		T224	1		T122	2
all_values[37]	514	1			T80	4		T122	2		T404	2
all_values[38]	485	1			T80	1		T122	1		T404	1
all_values[39]	486	1			T80	1		T122	2		T404	1
all_values[40]	516	1			T122	1		T404	1		T366	1
all_values[41]	468	1			T80	1		T122	1		T404	4
all_values[42]	481	1			T80	3		T122	3		T404	2
all_values[43]	503	1			T76	1		T80	1		T122	3
all_values[44]	507	1			T80	2		T122	1		T404	3
all_values[45]	501	1			T80	2		T122	2		T404	3
all_values[46]	493	1			T122	4		T404	1		T476	2
all_values[47]	535	1			T80	3		T122	1		T404	2
all_values[48]	440	1			T80	2		T122	1		T404	3
all_values[49]	508	1			T80	2		T122	1		T372	1