Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3583	1			T80	1		T122	17		T367	9
all_values[1]	3563	1			T74	3		T80	8		T122	17
all_values[2]	3659	1			T80	9		T122	25		T387	2
all_values[3]	3610	1			T80	11		T122	29		T456	2
all_values[4]	3583	1			T74	1		T80	8		T122	30
all_values[5]	3666	1			T74	2		T80	6		T122	14
all_values[6]	3638	1			T80	5		T122	32		T456	3
all_values[7]	3599	1			T74	3		T80	9		T122	27
all_values[8]	3637	1			T80	4		T122	18		T387	1
all_values[9]	3496	1			T74	1		T80	5		T122	20
all_values[10]	3627	1			T80	6		T122	18		T456	1
all_values[11]	3524	1			T80	6		T122	17		T367	7
all_values[12]	3595	1			T80	9		T122	20		T456	2
all_values[13]	3689	1			T74	3		T80	7		T122	10
all_values[14]	3618	1			T80	7		T122	23		T456	1
all_values[15]	3540	1			T74	1		T80	6		T122	25
all_values[16]	3607	1			T74	1		T80	6		T122	15
all_values[17]	3651	1			T74	1		T80	4		T122	19
all_values[18]	3618	1			T74	1		T80	7		T122	22
all_values[19]	3572	1			T80	4		T122	13		T456	2
all_values[20]	3623	1			T80	4		T122	18		T456	2
all_values[21]	3569	1			T80	8		T122	24		T387	2
all_values[22]	3565	1			T74	1		T80	9		T122	19
all_values[23]	3558	1			T80	7		T122	21		T456	1
all_values[24]	3612	1			T74	1		T80	7		T122	20
all_values[25]	3661	1			T74	2		T80	2		T122	19
all_values[26]	3597	1			T80	6		T122	21		T456	1
all_values[27]	3584	1			T80	4		T122	22		T456	1
all_values[28]	3566	1			T80	9		T122	23		T387	1
all_values[29]	3614	1			T80	8		T122	25		T387	1
all_values[30]	3659	1			T74	1		T80	1		T122	21
all_values[31]	3606	1			T80	8		T122	25		T387	1
all_values[32]	3578	1			T74	1		T80	7		T122	18
all_values[33]	3634	1			T80	7		T122	21		T456	2
all_values[34]	3698	1			T80	4		T122	29		T387	2
all_values[35]	3618	1			T74	1		T80	7		T122	20
all_values[36]	3529	1			T74	1		T80	10		T122	20
all_values[37]	3678	1			T80	5		T122	19		T387	2
all_values[38]	3520	1			T74	1		T80	4		T122	18
all_values[39]	3621	1			T80	6		T122	16		T387	1
all_values[40]	3512	1			T80	8		T122	19		T456	1
all_values[41]	3628	1			T80	5		T122	21		T387	1
all_values[42]	3727	1			T80	11		T122	16		T387	1
all_values[43]	3676	1			T80	9		T122	23		T456	1
all_values[44]	3584	1			T74	1		T80	7		T122	23
all_values[45]	3777	1			T80	8		T122	23		T387	1
all_values[46]	3590	1			T74	1		T80	5		T122	22
all_values[47]	3619	1			T80	8		T122	15		T456	1
all_values[48]	3680	1			T80	6		T122	20		T387	4
all_values[49]	3571	1			T74	2		T80	6		T122	24
all_values[50]	3483	1			T74	1		T80	10		T122	22
all_values[51]	3463	1			T74	1		T80	4		T122	16
all_values[52]	3698	1			T74	3		T80	5		T122	22
all_values[53]	3656	1			T74	1		T80	5		T122	18
all_values[54]	3616	1			T80	5		T122	28		T387	1
all_values[55]	3667	1			T80	7		T122	19		T387	1
all_values[56]	3577	1			T80	7		T122	15		T456	2
all_values[57]	3742	1			T80	7		T122	26		T456	3
all_values[58]	3664	1			T80	6		T122	25		T387	1
all_values[59]	3587	1			T80	7		T122	18		T367	8
all_values[60]	3526	1			T80	5		T122	13		T456	1
all_values[61]	3500	1			T74	2		T80	5		T122	14
all_values[62]	3581	1			T74	1		T80	3		T122	16
all_values[63]	3611	1			T80	5		T122	21		T387	1