Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	132279	1			T70	64		T71	65		T72	83
values[2]	8528	1			T71	2		T72	4		T222	4
values[3]	3176	1			T71	1		T434	1		T424	1
values[4]	1981	1			T424	1		T480	11		T705	3
values[5]	1263	1			T424	1		T480	10		T705	8
values[6]	746	1			T424	1		T480	11		T705	9
values[7]	538	1			T424	1		T480	10		T705	8
values[8]	411	1			T424	1		T480	3		T705	3
values[9]	367	1			T424	1		T480	5		T705	3
values[10]	319	1			T424	1		T480	4		T705	4
values[11]	346	1			T424	1		T480	21		T705	13
values[12]	264	1			T424	1		T480	5		T705	7
values[13]	244	1			T424	1		T480	13		T705	5
values[14]	253	1			T424	1		T480	6		T705	5
values[15]	237	1			T424	1		T480	5		T705	8
values[16]	246	1			T424	1		T480	3		T705	5
values[17]	240	1			T424	1		T480	3		T705	6
values[18]	211	1			T424	1		T480	9		T705	9
values[19]	213	1			T424	1		T480	4		T705	7
values[20]	232	1			T424	1		T480	8		T705	5
values[21]	233	1			T424	1		T480	6		T705	8
values[22]	240	1			T424	1		T480	5		T705	9
values[23]	223	1			T424	1		T480	8		T705	10
values[24]	175	1			T424	1		T480	5		T705	4
values[25]	228	1			T424	1		T480	13		T705	6
values[26]	220	1			T424	1		T480	13		T705	20
values[27]	210	1			T424	1		T480	6		T705	16
values[28]	183	1			T424	1		T480	5		T705	3
values[29]	210	1			T424	1		T480	12		T705	16
values[30]	149	1			T424	1		T480	12		T705	4
values[31]	187	1			T424	1		T480	11		T705	5
values[32]	210	1			T424	1		T480	5		T705	5
values[33]	218	1			T424	1		T480	5		T705	7
values[34]	203	1			T424	1		T480	7		T705	4
values[35]	189	1			T424	1		T480	8		T705	6
values[36]	202	1			T424	2		T480	7		T705	11
values[37]	224	1			T424	1		T480	6		T705	7
values[38]	246	1			T424	1		T480	16		T705	8
values[39]	255	1			T424	1		T480	13		T705	9
values[40]	227	1			T424	1		T480	13		T705	9
values[41]	224	1			T424	1		T480	8		T705	7
values[42]	173	1			T424	1		T480	10		T705	9
values[43]	196	1			T424	1		T480	7		T705	20
values[44]	185	1			T424	1		T480	9		T705	7
values[45]	204	1			T424	1		T480	4		T705	4
values[46]	147	1			T424	1		T480	4		T705	5
values[47]	156	1			T424	1		T480	6		T705	3
values[48]	169	1			T424	1		T480	5		T705	6
values[49]	195	1			T424	1		T480	8		T705	11
values[50]	200	1			T424	1		T480	4		T705	8
values[51]	203	1			T424	1		T480	3		T705	7
values[52]	198	1			T424	1		T480	11		T705	11
values[53]	186	1			T424	1		T480	3		T705	27
values[54]	175	1			T424	1		T480	16		T705	6
values[55]	171	1			T424	1		T480	2		T705	3
values[56]	218	1			T424	1		T480	9		T705	6
values[57]	174	1			T424	1		T480	4		T705	9
values[58]	187	1			T424	1		T480	16		T705	9
values[59]	134	1			T424	1		T480	4		T705	8
values[60]	176	1			T424	1		T705	10		T677	1
values[61]	127	1			T424	1		T705	8		T677	2
values[62]	130	1			T424	1		T705	4		T677	1
values[63]	149	1			T424	1		T705	5		T677	6
values[64]	183	1			T424	1		T705	12		T677	2
values[65]	124	1			T424	1		T705	6		T677	2
values[66]	115	1			T424	1		T705	4		T677	2
values[67]	96	1			T424	1		T705	4		T677	1
values[68]	113	1			T424	1		T705	6		T677	2
values[69]	131	1			T424	1		T705	11		T677	2
values[70]	98	1			T424	1		T705	4		T677	5
values[71]	94	1			T424	1		T677	16		T825	4
values[72]	77	1			T424	1		T677	11		T825	1
values[73]	77	1			T424	1		T677	11		T501	2
values[74]	71	1			T424	1		T677	3		T501	2
values[75]	69	1			T424	1		T677	1		T501	2
values[76]	75	1			T424	1		T677	2		T501	3
values[77]	63	1			T424	1		T677	2		T501	2
values[78]	64	1			T424	1		T677	3		T501	2
values[79]	77	1			T424	1		T677	1		T501	3
values[80]	86	1			T424	1		T677	3		T501	2
values[81]	75	1			T424	1		T677	2		T501	2
values[82]	61	1			T424	1		T677	4		T501	2
values[83]	50	1			T424	1		T677	2		T501	2
values[84]	50	1			T424	1		T677	6		T501	2
values[85]	57	1			T424	1		T677	10		T501	2
values[86]	54	1			T424	1		T677	3		T501	2
values[87]	62	1			T424	1		T677	2		T501	2
values[88]	55	1			T424	1		T677	8		T501	2
values[89]	54	1			T424	1		T677	6		T501	2
values[90]	67	1			T424	1		T677	3		T501	2
values[91]	65	1			T424	1		T677	7		T501	2
values[92]	52	1			T424	1		T677	3		T501	3
values[93]	65	1			T424	1		T677	12		T501	2
values[94]	55	1			T424	1		T677	7		T501	2
values[95]	39	1			T424	1		T677	3		T501	2
values[96]	58	1			T424	1		T677	5		T501	2
values[97]	79	1			T424	1		T677	5		T501	2
values[98]	73	1			T424	1		T677	5		T501	2
values[99]	70	1			T424	1		T677	7		T501	3
values[100]	60	1			T424	1		T677	9		T501	2
values[101]	67	1			T424	1		T677	7		T501	2
values[102]	63	1			T424	1		T677	6		T501	3
values[103]	58	1			T424	1		T677	6		T501	2
values[104]	53	1			T424	1		T677	2		T501	4
values[105]	68	1			T424	1		T677	6		T501	7
values[106]	70	1			T424	1		T677	5		T501	11
values[107]	69	1			T424	1		T677	5		T501	8
values[108]	68	1			T424	1		T677	8		T501	4
values[109]	90	1			T424	1		T677	15		T501	3
values[110]	65	1			T424	1		T677	8		T501	4
values[111]	59	1			T424	1		T677	11		T501	2
values[112]	85	1			T424	1		T677	7		T501	4
values[113]	58	1			T424	1		T677	8		T501	2
values[114]	67	1			T424	1		T677	10		T501	4
values[115]	53	1			T424	1		T677	6		T501	3
values[116]	54	1			T424	1		T677	12		T501	7
values[117]	49	1			T424	1		T677	2		T501	4
values[118]	63	1			T424	1		T501	6		T574	6
values[119]	51	1			T424	1		T501	3		T574	4
values[120]	64	1			T424	1		T501	3		T574	6
values[121]	64	1			T424	1		T501	4		T574	6
values[122]	56	1			T424	1		T501	4		T574	4
values[123]	58	1			T424	1		T501	3		T574	5
values[124]	62	1			T424	1		T501	4		T574	7
values[125]	54	1			T424	1		T501	3		T574	7
values[126]	82	1			T424	1		T501	6		T574	8
values[127]	875	1			T424	34		T501	68		T574	23
values[128]	7679	1			T424	312		T501	587		T574	14