Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.32	93.72	95.59		94.49	97.38	99.52

Total tests in report: 2762

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.59	40.59	45.68	45.68	44.24	44.24	32.53	32.53			58.51	58.51	62.11	62.11	0.45	0.45	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.768745483
50.52	9.94	51.68	6.00	56.92	12.68	34.58	2.06			69.92	11.41	88.72	26.62	1.33	0.88	/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1900512631
56.69	6.17	64.65	12.98	65.47	8.55	38.48	3.90			81.49	11.57	88.72	0.00	1.33	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1756395600
62.12	5.42	76.79	12.14	67.87	2.40	46.20	7.72			81.95	0.46	88.72	0.00	11.16	9.83	/workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.844434291
66.82	4.71	76.90	0.10	69.88	2.01	46.20	0.00			82.26	0.30	88.72	0.00	36.99	25.83	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.354053330
69.60	2.78	76.90	0.00	70.12	0.24	46.20	0.00			82.26	0.00	88.72	0.00	53.42	16.44	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1145390814
72.13	2.52	76.90	0.00	70.12	0.00	61.33	15.13			82.26	0.00	88.72	0.00	53.44	0.01	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.501961322
74.51	2.38	82.30	5.40	73.98	3.86	64.80	3.47			83.80	1.54	88.72	0.00	53.44	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1905331090
76.66	2.15	82.54	0.24	74.14	0.16	76.35	11.55			83.98	0.18	89.46	0.74	53.48	0.05	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2353355633
78.46	1.80	82.54	0.00	74.34	0.20	76.35	0.00			84.00	0.02	89.46	0.00	64.06	10.57	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1938256103
79.88	1.42	84.78	2.24	77.57	3.22	76.65	0.30			86.74	2.74	89.46	0.00	64.06	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4015668058
81.15	1.27	84.78	0.00	77.94	0.37	76.65	0.00			86.76	0.02	89.46	0.00	71.31	7.25	/workspace/coverage/cover_reg_top/86.xbar_stress_all.673342134
82.27	1.12	86.79	2.02	79.56	1.62	77.48	0.83			88.44	1.68	90.02	0.55	71.34	0.04	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4006103868
83.32	1.05	88.10	1.31	80.60	1.04	80.24	2.76			89.62	1.19	90.02	0.00	71.34	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2910221087
84.23	0.91	88.89	0.79	80.86	0.26	80.26	0.02			89.93	0.30	94.09	4.07	71.34	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3277168488
85.12	0.89	88.89	0.00	80.86	0.00	80.26	0.00			89.93	0.00	94.09	0.00	76.68	5.33	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3712819454
85.91	0.79	88.89	0.00	80.86	0.00	80.26	0.00			89.93	0.00	94.09	0.00	81.41	4.74	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.654233803
86.67	0.76	88.94	0.05	80.92	0.06	82.73	2.46			89.93	0.00	94.09	0.00	83.42	2.01	/workspace/coverage/default/1.chip_sw_alert_test.2701784610
87.39	0.72	89.98	1.04	81.65	0.73	82.93	0.21			90.61	0.68	95.75	1.66	83.42	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.786734391
88.08	0.69	89.98	0.00	81.65	0.00	82.93	0.00			90.61	0.00	95.75	0.00	87.53	4.11	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2670932654
88.75	0.67	90.63	0.64	84.38	2.73	83.28	0.35			90.93	0.31	95.75	0.00	87.53	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2147059048
89.31	0.56	90.63	0.01	84.50	0.12	83.99	0.71			90.96	0.03	95.75	0.00	90.05	2.51	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3554292256
89.85	0.53	90.63	0.00	84.50	0.00	83.99	0.00			90.96	0.00	95.75	0.00	93.24	3.20	/workspace/coverage/cover_reg_top/40.xbar_access_same_device.4051916915
90.25	0.40	91.45	0.82	84.67	0.17	84.39	0.40			90.97	0.01	95.75	0.00	94.25	1.01	/workspace/coverage/cover_reg_top/94.xbar_same_source.2715398176
90.65	0.40	91.45	0.00	84.67	0.00	86.78	2.39			90.97	0.00	95.75	0.00	94.25	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.894003418
91.04	0.39	92.00	0.55	85.44	0.76	87.25	0.47			91.53	0.56	95.75	0.00	94.27	0.01	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.945042987
91.42	0.38	92.01	0.01	87.32	1.88	87.25	0.00			91.53	0.00	95.75	0.00	94.68	0.41	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2448135259
91.78	0.36	92.48	0.47	87.82	0.50	87.94	0.68			92.02	0.49	95.75	0.00	94.68	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3972493307
92.09	0.31	92.99	0.50	88.19	0.37	88.21	0.27			92.23	0.21	96.12	0.37	94.83	0.15	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1946313931
92.35	0.26	93.38	0.39	88.72	0.53	88.42	0.21			92.64	0.41	96.12	0.00	94.83	0.00	/workspace/coverage/default/2.chip_sw_gpio_smoketest.238203066
92.60	0.25	93.39	0.01	88.73	0.01	89.73	1.31			92.64	0.00	96.30	0.18	94.83	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3744980550
92.83	0.23	93.39	0.00	88.73	0.01	89.73	0.00			92.64	0.00	96.30	0.00	96.20	1.37	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1114662649
92.99	0.15	93.45	0.06	89.13	0.40	89.81	0.08			93.03	0.39	96.30	0.00	96.20	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2824436252
93.14	0.15	93.52	0.07	89.15	0.01	90.61	0.81			93.04	0.01	96.30	0.00	96.20	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3090164384
93.29	0.15	93.62	0.10	89.87	0.72	90.65	0.04			93.06	0.02	96.30	0.00	96.20	0.00	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2326587583
93.43	0.14	93.62	0.00	90.01	0.14	90.65	0.00			93.08	0.02	96.30	0.00	96.90	0.69	/workspace/coverage/cover_reg_top/74.xbar_random_large_delays.885942717
93.55	0.13	93.86	0.24	90.20	0.19	90.66	0.01			93.40	0.32	96.30	0.00	96.90	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1927275920
93.67	0.11	94.05	0.19	90.35	0.15	90.85	0.19			93.56	0.16	96.30	0.00	96.90	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1367533249
93.78	0.11	94.05	0.00	90.54	0.18	90.85	0.00			93.58	0.02	96.30	0.00	97.37	0.47	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2809473895
93.88	0.10	94.05	0.00	91.14	0.61	90.85	0.00			93.58	0.00	96.30	0.00	97.37	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.3142458029
93.98	0.10	94.06	0.01	91.20	0.05	91.16	0.31			93.60	0.02	96.49	0.18	97.37	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2606846609
94.07	0.10	94.16	0.10	91.21	0.01	91.61	0.45			93.60	0.01	96.49	0.00	97.38	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2202876324
94.16	0.09	94.28	0.13	91.39	0.19	91.71	0.10			93.72	0.12	96.49	0.00	97.38	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.651461967
94.25	0.09	94.28	0.00	91.39	0.00	92.20	0.49			93.72	0.00	96.49	0.00	97.42	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2767043655
94.34	0.09	94.36	0.08	91.39	0.00	92.63	0.43			93.73	0.01	96.49	0.00	97.42	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.4228058313
94.42	0.08	94.36	0.00	91.42	0.03	92.63	0.00			93.73	0.00	96.49	0.00	97.90	0.48	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1730424679
94.50	0.08	94.48	0.13	91.52	0.10	92.81	0.18			93.82	0.09	96.49	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3939876950
94.58	0.08	94.48	0.00	91.52	0.00	93.29	0.48			93.82	0.00	96.49	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3572638101
94.66	0.08	94.48	0.00	91.52	0.00	93.74	0.45			93.82	0.00	96.49	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3852643726
94.73	0.07	94.48	0.00	91.71	0.19	93.75	0.01			94.03	0.21	96.49	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1686777528
94.78	0.05	94.57	0.09	91.78	0.07	93.82	0.07			94.11	0.07	96.49	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.1995124880
94.83	0.05	94.57	0.00	91.79	0.01	93.82	0.00			94.11	0.00	96.49	0.00	98.19	0.29	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3597342098
94.87	0.05	94.57	0.00	91.79	0.00	94.10	0.28			94.11	0.00	96.49	0.00	98.19	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1382394847
94.92	0.05	94.59	0.02	91.82	0.03	94.11	0.01			94.13	0.02	96.67	0.18	98.19	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1124204882
94.96	0.04	94.59	0.00	91.82	0.00	94.35	0.24			94.13	0.00	96.67	0.00	98.20	0.01	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2487808625
95.00	0.04	94.63	0.03	91.82	0.01	94.36	0.01			94.15	0.02	96.86	0.18	98.21	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3082104903
95.04	0.04	94.63	0.00	91.97	0.14	94.36	0.00			94.20	0.05	96.86	0.00	98.25	0.04	/workspace/coverage/cover_reg_top/53.xbar_stress_all.1260629881
95.08	0.04	94.63	0.01	91.98	0.01	94.36	0.00			94.21	0.01	97.04	0.18	98.26	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3670082921
95.12	0.04	94.64	0.01	91.99	0.01	94.36	0.01			94.21	0.01	97.23	0.18	98.27	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2075792037
95.16	0.04	94.64	0.01	92.00	0.01	94.37	0.01			94.22	0.01	97.41	0.18	98.28	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3662488052
95.19	0.03	94.64	0.00	92.21	0.21	94.37	0.00			94.22	0.00	97.41	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.3267270034
95.22	0.03	94.64	0.00	92.21	0.00	94.54	0.17			94.22	0.00	97.41	0.00	98.30	0.01	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2219033803
95.25	0.03	94.64	0.00	92.22	0.01	94.54	0.00			94.22	0.00	97.41	0.00	98.46	0.16	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3535645774
95.28	0.03	94.64	0.00	92.39	0.17	94.54	0.00			94.22	0.00	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.585763756
95.30	0.03	94.71	0.07	92.44	0.05	94.54	0.01			94.26	0.03	97.41	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1137048795
95.33	0.03	94.74	0.03	92.49	0.05	94.59	0.05			94.28	0.02	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1842164027
95.35	0.03	94.81	0.07	92.54	0.05	94.59	0.00			94.31	0.03	97.41	0.00	98.46	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.56110619
95.38	0.02	94.82	0.01	92.64	0.10	94.60	0.01			94.33	0.02	97.41	0.00	98.47	0.01	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1484975522
95.40	0.02	94.82	0.00	92.64	0.00	94.74	0.14			94.33	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.944455647
95.43	0.02	94.82	0.00	92.64	0.00	94.88	0.14			94.33	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.166707979
95.45	0.02	94.85	0.03	92.69	0.05	94.90	0.01			94.35	0.02	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.889273803
95.46	0.02	94.85	0.00	92.69	0.00	95.00	0.10			94.35	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1251140323
95.48	0.02	94.85	0.00	92.79	0.10	95.00	0.00			94.35	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.2421260325
95.49	0.02	94.86	0.01	92.80	0.02	95.04	0.05			94.37	0.02	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2846384367
95.51	0.02	94.86	0.00	92.85	0.05	95.04	0.00			94.37	0.00	97.41	0.00	98.52	0.05	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2285812634
95.52	0.01	94.90	0.03	92.87	0.02	95.07	0.03			94.37	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.59481600
95.54	0.01	94.90	0.00	92.95	0.08	95.07	0.00			94.37	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3237802526
95.55	0.01	94.90	0.00	92.98	0.03	95.07	0.00			94.37	0.00	97.41	0.00	98.57	0.05	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1861451306
95.56	0.01	94.90	0.00	93.05	0.07	95.07	0.00			94.37	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1468570518
95.57	0.01	94.90	0.00	93.07	0.03	95.08	0.01			94.40	0.02	97.41	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.569150039
95.58	0.01	94.90	0.00	93.13	0.06	95.08	0.00			94.40	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3261954740
95.59	0.01	94.90	0.00	93.13	0.00	95.08	0.00			94.40	0.00	97.41	0.00	98.63	0.06	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1102821007
95.60	0.01	94.90	0.00	93.19	0.05	95.08	0.00			94.40	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all.864943744
95.61	0.01	94.91	0.02	93.19	0.01	95.09	0.01			94.41	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1326812444
95.62	0.01	94.94	0.03	93.20	0.01	95.10	0.01			94.43	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.195309318
95.63	0.01	94.96	0.03	93.21	0.01	95.10	0.01			94.45	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2595977201
95.63	0.01	94.96	0.00	93.21	0.00	95.10	0.00			94.45	0.00	97.41	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.636158961
95.64	0.01	94.96	0.00	93.23	0.02	95.10	0.00			94.45	0.00	97.41	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2783277034
95.65	0.01	94.96	0.00	93.23	0.00	95.14	0.04			94.45	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3749209206
95.66	0.01	94.96	0.00	93.27	0.04	95.14	0.00			94.45	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1108416364
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95.68	0.01	94.97	0.01	93.37	0.03	95.15	0.01			94.45	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.265811978
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95.70	0.01	94.97	0.00	93.41	0.00	95.22	0.00			94.45	0.00	97.41	0.00	98.74	0.04	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2118058962
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95.73	0.01	94.97	0.00	93.47	0.00	95.35	0.03			94.46	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2081868461
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95.75	0.01	94.97	0.00	93.54	0.01	95.38	0.00			94.47	0.01	97.41	0.00	98.74	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4209754745
95.76	0.01	94.97	0.00	93.55	0.01	95.38	0.00			94.47	0.00	97.41	0.00	98.75	0.01	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3860115873
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95.77	0.01	94.97	0.00	93.57	0.02	95.42	0.00			94.47	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.968677831
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95.77	0.01	94.99	0.00	93.59	0.00	95.44	0.02			94.47	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2668310416
95.78	0.01	94.99	0.00	93.59	0.00	95.44	0.01			94.47	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2053142255
95.78	0.01	94.99	0.00	93.59	0.00	95.45	0.01			94.47	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1386802694
95.78	0.01	94.99	0.00	93.59	0.01	95.45	0.00			94.47	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1791499719
95.79	0.01	94.99	0.00	93.59	0.01	95.45	0.00			94.47	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3352654071
95.79	0.01	94.99	0.00	93.61	0.01	95.45	0.00			94.47	0.00	97.41	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.709043021
95.79	0.01	94.99	0.00	93.62	0.01	95.45	0.00			94.47	0.00	97.41	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1381229168
95.79	0.01	94.99	0.00	93.64	0.01	95.45	0.00			94.47	0.00	97.41	0.00	98.80	0.00	/workspace/coverage/default/1.chip_sw_gpio.618617915
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95.81	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3420431847
95.81	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3687368659
95.81	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/4.chip_tl_errors.3890265031
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95.82	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2632947938
95.82	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2818370160
95.82	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426189359
95.82	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3188581918
95.82	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392308904
95.83	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223399065
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95.83	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.781778813
95.83	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2452302104
95.83	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.370822243
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95.84	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082800271
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95.84	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1084451289
95.84	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314234758
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95.86	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.40983017
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95.87	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.291720061
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95.90	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.1683174234
95.91	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1869309458
95.91	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096902811
95.91	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.289647146
95.91	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1588199509
95.91	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3673296881
95.92	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3196245246
95.92	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269070544
95.92	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3500602907
95.92	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.1468495442
95.92	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3111135297
95.93	0.01	95.00	0.00	93.64	0.00	95.50	0.00			94.48	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.34545406
95.93	0.01	95.00	0.00	93.65	0.01	95.50	0.00			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.717742643
95.93	0.01	95.00	0.00	93.66	0.01	95.50	0.00			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3147872039
95.93	0.01	95.01	0.01	93.66	0.00	95.51	0.01			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/29.chip_sw_all_escalation_resets.342978917
95.93	0.01	95.01	0.00	93.66	0.00	95.52	0.01			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3407483003
95.93	0.01	95.01	0.00	93.66	0.00	95.53	0.01			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4109849880
95.94	0.01	95.01	0.00	93.66	0.00	95.54	0.01			94.48	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.859876409
95.94	0.01	95.01	0.00	93.66	0.00	95.54	0.00			94.49	0.01	97.41	0.00	99.52	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.2170451090
95.94	0.01	95.01	0.00	93.67	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2811037287
95.94	0.01	95.01	0.00	93.68	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1844512393
95.94	0.01	95.01	0.00	93.68	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/31.xbar_random.494742845
95.94	0.01	95.01	0.00	93.69	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1827355184
95.94	0.01	95.01	0.01	93.69	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_rw.3597510558
95.94	0.01	95.02	0.01	93.69	0.00	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1800661265
95.95	0.01	95.02	0.01	93.69	0.00	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2389019411
95.95	0.01	95.03	0.01	93.69	0.00	95.54	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2817739667
95.95	0.01	95.03	0.00	93.69	0.00	95.54	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.116554037
95.95	0.01	95.03	0.00	93.69	0.00	95.55	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4081544170
95.95	0.01	95.03	0.00	93.69	0.00	95.55	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3698641619
95.95	0.01	95.03	0.00	93.69	0.00	95.56	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2387667112
95.95	0.01	95.03	0.00	93.69	0.00	95.56	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.477057537
95.95	0.01	95.03	0.00	93.69	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2079503959
95.95	0.01	95.03	0.00	93.69	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3385103662
95.95	0.01	95.03	0.00	93.69	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3759274279
95.95	0.01	95.03	0.00	93.69	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.340692304
95.95	0.01	95.03	0.00	93.70	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4165376959
95.96	0.01	95.03	0.00	93.70	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3203000494
95.96	0.01	95.03	0.00	93.71	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/45.xbar_error_random.288363261
95.96	0.01	95.03	0.00	93.71	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_gpio.3019720796
95.96	0.01	95.03	0.00	93.71	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.774289760
95.96	0.01	95.03	0.00	93.72	0.01	95.58	0.00			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.4201884015
95.96	0.01	95.03	0.00	93.72	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3419440927
95.96	0.01	95.03	0.00	93.72	0.00	95.59	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1815121304
95.96	0.01	95.03	0.00	93.72	0.00	95.59	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3721045955
95.96	0.01	95.03	0.00	93.72	0.00	95.59	0.01			94.49	0.00	97.41	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2360838919

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1313213262
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2673903619
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1345052243
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3708839766
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3118921155
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2776949174
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1520594612
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3965539235
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2341611748
/workspace/coverage/cover_reg_top/0.xbar_error_random.1170177196
/workspace/coverage/cover_reg_top/0.xbar_random.4241572539
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3073658952
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.432120702
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4290927830
/workspace/coverage/cover_reg_top/0.xbar_same_source.705693067
/workspace/coverage/cover_reg_top/0.xbar_smoke.3879783103
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1409684194
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.464802923
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3249798678
/workspace/coverage/cover_reg_top/0.xbar_stress_all.479647136
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.808583999
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.830987565
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3005223496
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3794028583
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3560647922
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1135852767
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2513970868
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1607511194
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.157487973
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1440516628
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1669391178
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.340498897
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1472657600
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1503127110
/workspace/coverage/cover_reg_top/1.xbar_error_random.900952841
/workspace/coverage/cover_reg_top/1.xbar_random.1562286278
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.243104026
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3702531940
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2353716126
/workspace/coverage/cover_reg_top/1.xbar_same_source.3062254154
/workspace/coverage/cover_reg_top/1.xbar_smoke.2419886891
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2666615464
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4252002630
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2928810638
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3361582853
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4235351756
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3540153977
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1057600066
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3454348808
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3506666997
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.640850348
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1865783655
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1082866559
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3163792490
/workspace/coverage/cover_reg_top/10.xbar_error_random.658186508
/workspace/coverage/cover_reg_top/10.xbar_random.3541675301
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4056726723
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.840995958
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1777083349
/workspace/coverage/cover_reg_top/10.xbar_same_source.2097620770
/workspace/coverage/cover_reg_top/10.xbar_smoke.831188496
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.717829471
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1607561866
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.441016378
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4110156195
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2183242377
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2310469759
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.886585
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1752344360
/workspace/coverage/cover_reg_top/11.chip_tl_errors.50434686
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2547400349
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2034071569
/workspace/coverage/cover_reg_top/11.xbar_error_random.717662217
/workspace/coverage/cover_reg_top/11.xbar_random.3821939440
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1267952665
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1821556707
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2802264897
/workspace/coverage/cover_reg_top/11.xbar_same_source.2063235364
/workspace/coverage/cover_reg_top/11.xbar_smoke.3796851406
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.337906519
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2950566912
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4200507618
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2821156113
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1853526984
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3921912412
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4033692668
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1553103983
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1412544276
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2080937132
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1680936247
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3531235663
/workspace/coverage/cover_reg_top/12.xbar_error_random.3316573459
/workspace/coverage/cover_reg_top/12.xbar_random.746446208
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3148002311
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1850505376
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.583740208
/workspace/coverage/cover_reg_top/12.xbar_same_source.21581535
/workspace/coverage/cover_reg_top/12.xbar_smoke.2294484266
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.236148243
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.985354233
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2131586423
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4072789425
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.188311748
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.847222236
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1277535999
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1087078966
/workspace/coverage/cover_reg_top/13.chip_csr_rw.659853058
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2999391606
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3173967721
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1599925157
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.61107233
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2704267363
/workspace/coverage/cover_reg_top/13.xbar_error_random.4142930325
/workspace/coverage/cover_reg_top/13.xbar_random.1658573898
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.622353188
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2317679192
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.96635903
/workspace/coverage/cover_reg_top/13.xbar_same_source.2168276561
/workspace/coverage/cover_reg_top/13.xbar_smoke.2858227123
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.348527599
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1456071121
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3718304463
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2063217090
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.57167914
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4096027562
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2984602376
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2591051217
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2718143381
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2976988838
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.68773034
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1291343739
/workspace/coverage/cover_reg_top/14.xbar_error_random.2670653270
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/workspace/coverage/default/73.chip_sw_all_escalation_resets.2798151882
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.12594944
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2429402886
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627961523
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3365998398
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3524674157
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1772085940
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3760271895
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3473961382
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3532799673
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4131207941
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4118584711
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009708579
/workspace/coverage/default/80.chip_sw_all_escalation_resets.299606175
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2167762464
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3753993141
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3506677930
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1735604414
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.850537571
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3327640544
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4042315615
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1903241894
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3419318232
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3513840732
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199917895
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4153737622
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.800070923
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3323441134
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3408202078
/workspace/coverage/default/89.chip_sw_all_escalation_resets.415178747
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862153196
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3139623332
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2470839997
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3752857599
/workspace/coverage/default/90.chip_sw_all_escalation_resets.285573705
/workspace/coverage/default/92.chip_sw_all_escalation_resets.54032742
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2895256903
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3438891305
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2144901818
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1086265832
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1726852115
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2181961049
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3646183724
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2614538608
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3973019835
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.472188112
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3008458943
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3619487869
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4105484134
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1782660881
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2662404730

---

Total test records in report: 2762

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.569150039			May 05 04:33:32 PM PDT 24	May 05 04:43:48 PM PDT 24	6533857709 ps
T2	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.945042987			May 05 04:46:31 PM PDT 24	May 05 04:54:09 PM PDT 24	3163548350 ps
T3	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2202876324			May 05 04:53:03 PM PDT 24	May 05 05:04:01 PM PDT 24	5135647060 ps
T34	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4051019215			May 05 04:32:29 PM PDT 24	May 05 04:43:52 PM PDT 24	7215012586 ps
T82	/workspace/coverage/default/0.chip_sw_example_rom.3357921898			May 05 04:22:10 PM PDT 24	May 05 04:24:15 PM PDT 24	2301049740 ps
T83	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4217956323			May 05 04:37:57 PM PDT 24	May 05 04:42:31 PM PDT 24	2908496840 ps
T59	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.768745483			May 05 04:39:40 PM PDT 24	May 05 07:41:32 PM PDT 24	254756594532 ps
T84	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2489532151			May 05 04:31:03 PM PDT 24	May 05 04:35:49 PM PDT 24	3691900815 ps
T44	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4158001739			May 05 04:21:48 PM PDT 24	May 05 04:23:56 PM PDT 24	2649828001 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2846384367			May 05 04:21:10 PM PDT 24	May 05 04:25:37 PM PDT 24	2921810556 ps
T110	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2978701819			May 05 04:22:54 PM PDT 24	May 05 04:27:50 PM PDT 24	3161895927 ps
T4	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2353355633			May 05 04:23:21 PM PDT 24	May 05 05:53:57 PM PDT 24	46149104442 ps
T67	/workspace/coverage/default/1.chip_tap_straps_dev.2170451090			May 05 04:33:03 PM PDT 24	May 05 05:00:25 PM PDT 24	14498799255 ps
T5	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2295759464			May 05 04:21:13 PM PDT 24	May 05 04:55:42 PM PDT 24	28637247488 ps
T172	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2247945332			May 05 04:45:25 PM PDT 24	May 05 04:52:54 PM PDT 24	3755895270 ps
T223	/workspace/coverage/default/1.chip_sw_plic_sw_irq.4177416855			May 05 04:32:12 PM PDT 24	May 05 04:35:53 PM PDT 24	2625289216 ps
T118	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2719059053			May 05 04:30:24 PM PDT 24	May 05 05:15:26 PM PDT 24	11242849552 ps
T60	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2950082042			May 05 04:53:14 PM PDT 24	May 05 05:04:31 PM PDT 24	5379444404 ps
T114	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1265815737			May 05 04:23:40 PM PDT 24	May 05 04:34:21 PM PDT 24	4260311720 ps
T365	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1291095206			May 05 04:30:57 PM PDT 24	May 05 04:34:27 PM PDT 24	2391710550 ps
T366	/workspace/coverage/default/1.chip_sw_uart_smoketest.1325893661			May 05 04:35:57 PM PDT 24	May 05 04:38:41 PM PDT 24	1981527914 ps
T68	/workspace/coverage/default/4.chip_tap_straps_dev.3995828039			May 05 04:45:00 PM PDT 24	May 05 05:02:14 PM PDT 24	12382402308 ps
T367	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2153479984			May 05 04:46:10 PM PDT 24	May 05 04:50:21 PM PDT 24	2774246540 ps
T103	/workspace/coverage/default/1.chip_sw_power_sleep_load.1995124880			May 05 04:34:39 PM PDT 24	May 05 04:40:48 PM PDT 24	4093328384 ps
T307	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.761536859			May 05 04:47:41 PM PDT 24	May 05 04:55:04 PM PDT 24	3842660930 ps
T368	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2081868461			May 05 04:41:25 PM PDT 24	May 05 04:47:10 PM PDT 24	2620524470 ps
T123	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4006103868			May 05 04:23:25 PM PDT 24	May 05 04:28:55 PM PDT 24	4917010304 ps
T168	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.514563228			May 05 04:39:05 PM PDT 24	May 05 04:42:33 PM PDT 24	2454099180 ps
T121	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1894176406			May 05 04:30:23 PM PDT 24	May 05 05:34:18 PM PDT 24	17742426492 ps
T173	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2487808625			May 05 04:23:45 PM PDT 24	May 05 04:32:18 PM PDT 24	5487554436 ps
T6	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.894003418			May 05 04:26:42 PM PDT 24	May 05 05:45:43 PM PDT 24	44586050602 ps
T180	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.265811978			May 05 04:21:08 PM PDT 24	May 05 04:34:17 PM PDT 24	4398706874 ps
T339	/workspace/coverage/default/0.chip_sw_aes_entropy.1149539133			May 05 04:22:21 PM PDT 24	May 05 04:26:58 PM PDT 24	3147721552 ps
T111	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1800470431			May 05 04:43:17 PM PDT 24	May 05 04:54:03 PM PDT 24	4975931274 ps
T314	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1984245400			May 05 04:29:14 PM PDT 24	May 05 04:33:45 PM PDT 24	3081923488 ps
T167	/workspace/coverage/default/89.chip_sw_all_escalation_resets.415178747			May 05 04:54:05 PM PDT 24	May 05 05:06:44 PM PDT 24	5813042136 ps
T869	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3158663843			May 05 04:40:53 PM PDT 24	May 05 04:45:37 PM PDT 24	2746445080 ps
T169	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2478728829			May 05 04:29:45 PM PDT 24	May 05 04:37:29 PM PDT 24	5173165466 ps
T64	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1015690878			May 05 04:33:51 PM PDT 24	May 05 04:40:08 PM PDT 24	4874130084 ps
T177	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2322227109			May 05 04:30:34 PM PDT 24	May 05 04:39:35 PM PDT 24	4460352803 ps
T13	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.889273803			May 05 04:21:53 PM PDT 24	May 05 04:32:16 PM PDT 24	4164400902 ps
T396	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.97432438			May 05 04:40:00 PM PDT 24	May 05 04:44:26 PM PDT 24	2492480996 ps
T115	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.972050614			May 05 04:32:34 PM PDT 24	May 05 04:41:28 PM PDT 24	4955017316 ps
T45	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1137048795			May 05 04:26:17 PM PDT 24	May 05 04:33:34 PM PDT 24	4594280896 ps
T96	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3081224361			May 05 04:27:59 PM PDT 24	May 05 04:38:46 PM PDT 24	7476623832 ps
T97	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2640364586			May 05 04:23:28 PM PDT 24	May 05 04:55:57 PM PDT 24	20042417900 ps
T98	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1903241894			May 05 04:53:55 PM PDT 24	May 05 05:02:04 PM PDT 24	4138793992 ps
T69	/workspace/coverage/default/2.chip_tap_straps_prod.2081651511			May 05 04:41:46 PM PDT 24	May 05 05:01:23 PM PDT 24	12472954740 ps
T99	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4070968185			May 05 04:32:23 PM PDT 24	May 05 05:11:43 PM PDT 24	24952001353 ps
T100	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.944455647			May 05 04:28:59 PM PDT 24	May 05 04:31:59 PM PDT 24	2703667549 ps
T46	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3015583858			May 05 04:20:48 PM PDT 24	May 05 04:24:09 PM PDT 24	2897693836 ps
T101	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1712406046			May 05 04:29:07 PM PDT 24	May 05 04:38:00 PM PDT 24	3362590072 ps
T102	/workspace/coverage/default/0.chip_plic_all_irqs_20.2910221087			May 05 04:22:48 PM PDT 24	May 05 04:35:11 PM PDT 24	4663361928 ps
T264	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.800070923			May 05 04:54:07 PM PDT 24	May 05 05:00:39 PM PDT 24	3893379474 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1367533249			May 05 04:24:01 PM PDT 24	May 05 04:48:49 PM PDT 24	23011710920 ps
T194	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1086265832			May 05 04:54:20 PM PDT 24	May 05 05:03:10 PM PDT 24	5697046820 ps
T227	/workspace/coverage/default/2.chip_plic_all_irqs_0.1756395600			May 05 04:46:17 PM PDT 24	May 05 05:02:50 PM PDT 24	6640970300 ps
T14	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.521620869			May 05 04:50:30 PM PDT 24	May 05 05:01:08 PM PDT 24	4721869386 ps
T65	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3090164384			May 05 04:21:37 PM PDT 24	May 05 07:24:45 PM PDT 24	57545174286 ps
T265	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2428205693			May 05 04:49:09 PM PDT 24	May 05 04:56:10 PM PDT 24	4045926072 ps
T266	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1197084709			May 05 04:52:05 PM PDT 24	May 05 05:02:23 PM PDT 24	4776047620 ps
T320	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1946313931			May 05 04:55:05 PM PDT 24	May 05 05:03:09 PM PDT 24	4765255220 ps
T41	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1406966244			May 05 04:26:44 PM PDT 24	May 05 04:32:34 PM PDT 24	3366631844 ps
T225	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3490880631			May 05 04:38:49 PM PDT 24	May 05 04:44:48 PM PDT 24	3073385438 ps
T181	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.41659740			May 05 04:48:03 PM PDT 24	May 05 05:09:53 PM PDT 24	7584223780 ps
T146	/workspace/coverage/default/0.chip_plic_all_irqs_10.3972493307			May 05 04:23:19 PM PDT 24	May 05 04:32:03 PM PDT 24	4272506680 ps
T122	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.501961322			May 05 04:43:35 PM PDT 24	May 05 05:28:15 PM PDT 24	12164080542 ps
T143	/workspace/coverage/default/0.chip_sw_otbn_smoketest.722237834			May 05 04:25:12 PM PDT 24	May 05 04:45:30 PM PDT 24	5964350498 ps
T346	/workspace/coverage/default/1.chip_sw_kmac_smoketest.131774667			May 05 04:37:55 PM PDT 24	May 05 04:42:34 PM PDT 24	3099021120 ps
T347	/workspace/coverage/default/0.chip_sw_kmac_entropy.693562865			May 05 04:21:55 PM PDT 24	May 05 04:25:07 PM PDT 24	2628976012 ps
T171	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4131207941			May 05 04:46:05 PM PDT 24	May 05 04:54:35 PM PDT 24	5931786123 ps
T870	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3896381058			May 05 04:47:29 PM PDT 24	May 05 04:58:29 PM PDT 24	5926594890 ps
T157	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4224217240			May 05 04:42:38 PM PDT 24	May 05 05:10:03 PM PDT 24	19623755753 ps
T671	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2651985039			May 05 04:44:09 PM PDT 24	May 05 04:54:22 PM PDT 24	5008245584 ps
T104	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.15607186			May 05 04:40:36 PM PDT 24	May 05 04:49:58 PM PDT 24	17694529580 ps
T688	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3524674157			May 05 04:53:37 PM PDT 24	May 05 05:02:54 PM PDT 24	6125387010 ps
T119	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3744980550			May 05 04:22:19 PM PDT 24	May 05 04:34:16 PM PDT 24	3545061164 ps
T506	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3196245246			May 05 04:46:03 PM PDT 24	May 05 04:56:49 PM PDT 24	4245048056 ps
T78	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.812172813			May 05 04:51:43 PM PDT 24	May 05 04:58:30 PM PDT 24	3746666584 ps
T89	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2112451346			May 05 04:37:54 PM PDT 24	May 05 04:47:54 PM PDT 24	4001200262 ps
T61	/workspace/coverage/default/3.chip_tap_straps_rma.4228058313			May 05 04:49:24 PM PDT 24	May 05 04:57:45 PM PDT 24	5347555600 ps
T90	/workspace/coverage/default/2.chip_sw_kmac_idle.2217067670			May 05 04:41:06 PM PDT 24	May 05 04:44:50 PM PDT 24	2919040788 ps
T91	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.289647146			May 05 04:51:59 PM PDT 24	May 05 04:58:52 PM PDT 24	3764242960 ps
T92	/workspace/coverage/default/2.chip_sw_hmac_enc.1700223234			May 05 04:40:29 PM PDT 24	May 05 04:44:11 PM PDT 24	2657894400 ps
T10	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.651461967			May 05 04:28:55 PM PDT 24	May 05 04:36:24 PM PDT 24	4290801949 ps
T93	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1962717756			May 05 04:23:10 PM PDT 24	May 05 04:45:45 PM PDT 24	6739042228 ps
T94	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3014149861			May 05 04:50:30 PM PDT 24	May 05 05:00:45 PM PDT 24	5628454500 ps
T95	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1991114470			May 05 04:23:22 PM PDT 24	May 05 04:25:28 PM PDT 24	2455589926 ps
T871	/workspace/coverage/default/0.chip_sw_kmac_idle.3436804195			May 05 04:23:18 PM PDT 24	May 05 04:28:57 PM PDT 24	3425390148 ps
T158	/workspace/coverage/default/1.chip_sw_flash_init.4176919463			May 05 04:26:23 PM PDT 24	May 05 05:03:10 PM PDT 24	19368555820 ps
T159	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1414629825			May 05 04:21:56 PM PDT 24	May 05 04:24:14 PM PDT 24	3069412530 ps
T362	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2494894145			May 05 04:21:20 PM PDT 24	May 05 04:38:51 PM PDT 24	5397470152 ps
T507	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2290911688			May 05 04:47:35 PM PDT 24	May 05 04:52:01 PM PDT 24	3042451304 ps
T872	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3054688335			May 05 04:46:41 PM PDT 24	May 05 04:52:47 PM PDT 24	6860596066 ps
T186	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1517988221			May 05 04:47:59 PM PDT 24	May 05 05:10:44 PM PDT 24	8416418160 ps
T415	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1961460783			May 05 04:21:32 PM PDT 24	May 05 04:41:25 PM PDT 24	6139229807 ps
T15	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1424585381			May 05 04:38:38 PM PDT 24	May 05 05:05:38 PM PDT 24	8167858800 ps
T116	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1842164027			May 05 04:22:27 PM PDT 24	May 05 05:07:51 PM PDT 24	12981547639 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2489993314			May 05 04:21:57 PM PDT 24	May 05 04:25:22 PM PDT 24	3110364960 ps
T201	/workspace/coverage/default/2.rom_keymgr_functest.2071401114			May 05 04:44:16 PM PDT 24	May 05 04:52:40 PM PDT 24	4098423616 ps
T289	/workspace/coverage/default/2.chip_plic_all_irqs_20.3147872039			May 05 04:40:53 PM PDT 24	May 05 04:50:37 PM PDT 24	4516962920 ps
T691	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082800271			May 05 04:50:15 PM PDT 24	May 05 04:57:39 PM PDT 24	3486067656 ps
T288	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.38570971			May 05 04:46:13 PM PDT 24	May 05 04:53:52 PM PDT 24	6883597112 ps
T112	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1928667756			May 05 04:42:20 PM PDT 24	May 05 04:51:22 PM PDT 24	5458809092 ps
T873	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.272883232			May 05 04:28:10 PM PDT 24	May 05 04:39:22 PM PDT 24	4772625400 ps
T668	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2685110396			May 05 04:51:51 PM PDT 24	May 05 05:03:36 PM PDT 24	6098979020 ps
T696	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2947033913			May 05 04:42:05 PM PDT 24	May 05 04:50:51 PM PDT 24	3118696872 ps
T105	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2888465962			May 05 04:30:32 PM PDT 24	May 05 04:36:55 PM PDT 24	19110946348 ps
T187	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.119118064			May 05 04:44:46 PM PDT 24	May 05 05:26:27 PM PDT 24	13345280623 ps
T874	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3705132230			May 05 04:39:13 PM PDT 24	May 05 04:47:35 PM PDT 24	5619411956 ps
T670	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314031807			May 05 04:48:04 PM PDT 24	May 05 04:54:22 PM PDT 24	3685824490 ps
T195	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862153196			May 05 04:48:02 PM PDT 24	May 05 04:55:34 PM PDT 24	3681656292 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.409913113			May 05 04:21:17 PM PDT 24	May 05 06:12:29 PM PDT 24	31860568560 ps
T120	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3313866845			May 05 04:34:59 PM PDT 24	May 05 04:44:37 PM PDT 24	2485598370 ps
T875	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1879025234			May 05 04:24:34 PM PDT 24	May 05 04:35:46 PM PDT 24	5364262980 ps
T285	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1985223815			May 05 04:49:48 PM PDT 24	May 05 04:57:16 PM PDT 24	4813108734 ps
T698	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.822998724			May 05 04:56:07 PM PDT 24	May 05 05:03:14 PM PDT 24	3775021328 ps
T124	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4042205048			May 05 04:43:35 PM PDT 24	May 05 04:50:55 PM PDT 24	4327748328 ps
T286	/workspace/coverage/default/83.chip_sw_all_escalation_resets.3327640544			May 05 04:55:18 PM PDT 24	May 05 05:03:45 PM PDT 24	4929704200 ps
T750	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2690192428			May 05 04:50:41 PM PDT 24	May 05 04:55:45 PM PDT 24	3473420832 ps
T213	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1124204882			May 05 04:20:51 PM PDT 24	May 05 04:32:26 PM PDT 24	5156877240 ps
T73	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.228735806			May 05 04:38:54 PM PDT 24	May 05 07:31:52 PM PDT 24	58006063645 ps
T252	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1588199509			May 05 04:52:49 PM PDT 24	May 05 05:01:58 PM PDT 24	5988097912 ps
T191	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2847333639			May 05 04:42:34 PM PDT 24	May 05 05:17:40 PM PDT 24	26602372041 ps
T253	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1217286687			May 05 04:33:12 PM PDT 24	May 05 04:51:25 PM PDT 24	6904399626 ps
T254	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.234097145			May 05 04:28:38 PM PDT 24	May 05 04:45:30 PM PDT 24	9568397128 ps
T255	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2452302104			May 05 04:48:42 PM PDT 24	May 05 04:59:21 PM PDT 24	4513926848 ps
T256	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.40983017			May 05 04:49:31 PM PDT 24	May 05 04:56:50 PM PDT 24	3987373544 ps
T153	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.340692304			May 05 04:30:28 PM PDT 24	May 05 04:32:05 PM PDT 24	1741535369 ps
T257	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096902811			May 05 04:52:32 PM PDT 24	May 05 04:59:30 PM PDT 24	3913643960 ps
T292	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3352654071			May 05 04:51:04 PM PDT 24	May 05 05:02:27 PM PDT 24	6074390084 ps
T293	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3698641619			May 05 04:24:38 PM PDT 24	May 05 04:29:48 PM PDT 24	3986890828 ps
T294	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4059511007			May 05 04:23:43 PM PDT 24	May 05 05:00:22 PM PDT 24	19374693040 ps
T42	/workspace/coverage/default/2.chip_sw_spi_device_tpm.831115240			May 05 04:39:20 PM PDT 24	May 05 04:45:38 PM PDT 24	3433703819 ps
T295	/workspace/coverage/default/1.chip_sw_aes_enc.1281030280			May 05 04:29:15 PM PDT 24	May 05 04:33:51 PM PDT 24	3332713752 ps
T296	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3408202078			May 05 04:54:08 PM PDT 24	May 05 05:00:59 PM PDT 24	3129512112 ps
T182	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1669118628			May 05 04:26:54 PM PDT 24	May 05 04:36:59 PM PDT 24	3913239246 ps
T297	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.580020361			May 05 04:32:55 PM PDT 24	May 05 04:41:47 PM PDT 24	3955443764 ps
T109	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2219033803			May 05 04:41:43 PM PDT 24	May 05 04:59:50 PM PDT 24	6742273071 ps
T160	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2051021619			May 05 04:38:20 PM PDT 24	May 05 04:40:44 PM PDT 24	3352000697 ps
T175	/workspace/coverage/default/1.chip_sw_power_idle_load.2588123762			May 05 04:35:41 PM PDT 24	May 05 04:45:40 PM PDT 24	4332681480 ps
T321	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1084451289			May 05 04:48:21 PM PDT 24	May 05 04:59:32 PM PDT 24	6171922260 ps
T876	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3353424645			May 05 04:44:21 PM PDT 24	May 05 04:53:01 PM PDT 24	3547709100 ps
T11	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3084575998			May 05 04:27:05 PM PDT 24	May 05 04:38:37 PM PDT 24	5316005887 ps
T326	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3027957172			May 05 04:49:54 PM PDT 24	May 05 04:59:55 PM PDT 24	5115370840 ps
T21	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2316843500			May 05 04:30:25 PM PDT 24	May 05 04:55:35 PM PDT 24	22730891974 ps
T690	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3685023861			May 05 04:48:54 PM PDT 24	May 05 04:54:52 PM PDT 24	4547681972 ps
T877	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1978633010			May 05 04:49:57 PM PDT 24	May 05 04:59:04 PM PDT 24	4195895420 ps
T699	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2632947938			May 05 04:34:04 PM PDT 24	May 05 04:40:44 PM PDT 24	4150606460 ps
T878	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1833940969			May 05 04:45:55 PM PDT 24	May 05 04:55:16 PM PDT 24	5543395610 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2916687776			May 05 04:21:42 PM PDT 24	May 05 04:29:45 PM PDT 24	4104148304 ps
T117	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3301569531			May 05 04:42:41 PM PDT 24	May 05 04:55:53 PM PDT 24	3697186208 ps
T408	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.644248112			May 05 04:43:57 PM PDT 24	May 05 04:48:04 PM PDT 24	2901212176 ps
T319	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3760271895			May 05 04:53:53 PM PDT 24	May 05 05:02:57 PM PDT 24	5262569018 ps
T879	/workspace/coverage/default/2.chip_sw_example_rom.3009653823			May 05 04:35:41 PM PDT 24	May 05 04:37:55 PM PDT 24	2886484030 ps
T58	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3316262413			May 05 04:36:20 PM PDT 24	May 05 04:44:53 PM PDT 24	5586710360 ps
T170	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4002011480			May 05 04:28:23 PM PDT 24	May 05 04:32:31 PM PDT 24	3247592666 ps
T409	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2019938579			May 05 04:25:47 PM PDT 24	May 05 04:29:46 PM PDT 24	2299672092 ps
T880	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3544386285			May 05 04:31:59 PM PDT 24	May 05 04:36:24 PM PDT 24	3206616874 ps
T113	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2606846609			May 05 04:26:55 PM PDT 24	May 05 04:35:32 PM PDT 24	5274963612 ps
T881	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1334622474			May 05 04:32:09 PM PDT 24	May 05 04:39:16 PM PDT 24	3913940324 ps
T38	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3784769760			May 05 04:25:22 PM PDT 24	May 05 04:33:29 PM PDT 24	4415487504 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.869230882			May 05 04:21:38 PM PDT 24	May 05 04:33:36 PM PDT 24	3590980352 ps
T882	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3012506110			May 05 04:26:57 PM PDT 24	May 05 04:44:41 PM PDT 24	5636254900 ps
T883	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2251255522			May 05 04:35:17 PM PDT 24	May 05 04:40:43 PM PDT 24	2886793904 ps
T317	/workspace/coverage/default/0.chip_sival_flash_info_access.1684640164			May 05 04:23:46 PM PDT 24	May 05 04:28:46 PM PDT 24	2571945040 ps
T884	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2221368337			May 05 04:32:10 PM PDT 24	May 05 04:45:39 PM PDT 24	4464417704 ps
T328	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3533948073			May 05 04:22:32 PM PDT 24	May 05 04:29:28 PM PDT 24	3951237566 ps
T74	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.859876409			May 05 04:24:45 PM PDT 24	May 05 04:32:03 PM PDT 24	5200635624 ps
T192	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3574666402			May 05 04:23:46 PM PDT 24	May 05 04:56:39 PM PDT 24	8903745922 ps
T885	/workspace/coverage/default/0.chip_sw_csrng_kat_test.1285599778			May 05 04:23:58 PM PDT 24	May 05 04:27:52 PM PDT 24	3067192112 ps
T886	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1014773496			May 05 04:28:36 PM PDT 24	May 05 04:39:22 PM PDT 24	5862366096 ps
T198	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2266191910			May 05 04:30:11 PM PDT 24	May 05 04:40:27 PM PDT 24	4896581260 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4015668058			May 05 04:26:34 PM PDT 24	May 05 04:30:32 PM PDT 24	2699068575 ps
T887	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3426249090			May 05 04:24:15 PM PDT 24	May 05 04:33:24 PM PDT 24	4381253606 ps
T755	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044049365			May 05 04:52:41 PM PDT 24	May 05 04:59:47 PM PDT 24	3801959760 ps
T370	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.200329484			May 05 04:22:45 PM PDT 24	May 05 04:27:50 PM PDT 24	2668680749 ps
T416	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2053142255			May 05 04:47:28 PM PDT 24	May 05 04:59:13 PM PDT 24	5422108088 ps
T162	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3277168488			May 05 04:24:35 PM PDT 24	May 05 04:28:47 PM PDT 24	2192171400 ps
T278	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1418562242			May 05 04:44:33 PM PDT 24	May 05 04:52:49 PM PDT 24	3456392832 ps
T203	/workspace/coverage/default/0.chip_sw_flash_init.371028313			May 05 04:21:59 PM PDT 24	May 05 05:02:52 PM PDT 24	26079992524 ps
T35	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.59481600			May 05 04:22:41 PM PDT 24	May 05 04:27:30 PM PDT 24	2644656020 ps
T279	/workspace/coverage/default/0.chip_tap_straps_testunlock0.825203516			May 05 04:25:14 PM PDT 24	May 05 04:32:39 PM PDT 24	5424820505 ps
T184	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2142302432			May 05 04:21:54 PM PDT 24	May 05 04:39:26 PM PDT 24	9341517524 ps
T280	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1471095878			May 05 04:25:41 PM PDT 24	May 05 04:39:15 PM PDT 24	4014822640 ps
T281	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.4259797269			May 05 04:44:31 PM PDT 24	May 05 05:05:47 PM PDT 24	8386426930 ps
T282	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.974436391			May 05 04:34:28 PM PDT 24	May 05 04:37:43 PM PDT 24	2724160357 ps
T226	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1817565860			May 05 04:26:04 PM PDT 24	May 05 04:29:58 PM PDT 24	2217272124 ps
T327	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3188581918			May 05 04:47:35 PM PDT 24	May 05 04:56:20 PM PDT 24	4901140904 ps
T700	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2181961049			May 05 04:54:32 PM PDT 24	May 05 05:05:17 PM PDT 24	6122936384 ps
T151	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1100164420			May 05 04:50:56 PM PDT 24	May 05 05:00:01 PM PDT 24	5620424384 ps
T62	/workspace/coverage/default/4.chip_tap_straps_testunlock0.6655825			May 05 04:44:35 PM PDT 24	May 05 04:58:39 PM PDT 24	8948759858 ps
T156	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3726368476			May 05 04:38:18 PM PDT 24	May 05 05:10:49 PM PDT 24	21403963552 ps
T161	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1809388831			May 05 04:23:51 PM PDT 24	May 05 04:34:55 PM PDT 24	4488874200 ps
T144	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2588627439			May 05 04:22:27 PM PDT 24	May 05 05:18:38 PM PDT 24	16429284920 ps
T250	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3587265335			May 05 04:44:49 PM PDT 24	May 05 04:53:42 PM PDT 24	4892410008 ps
T340	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1815121304			May 05 04:23:25 PM PDT 24	May 05 04:29:45 PM PDT 24	2710515846 ps
T25	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.786734391			May 05 04:21:58 PM PDT 24	May 05 04:27:15 PM PDT 24	4426272834 ps
T376	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3646183724			May 05 04:54:30 PM PDT 24	May 05 05:03:45 PM PDT 24	4724131412 ps
T107	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1665447697			May 05 04:26:12 PM PDT 24	May 05 04:54:28 PM PDT 24	10227490881 ps
T377	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2861537458			May 05 04:29:52 PM PDT 24	May 05 04:42:50 PM PDT 24	4138754374 ps
T125	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.789222153			May 05 04:33:37 PM PDT 24	May 05 04:40:03 PM PDT 24	5542314412 ps
T378	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2253796618			May 05 04:54:20 PM PDT 24	May 05 05:05:59 PM PDT 24	4756274278 ps
T8	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1686777528			May 05 04:38:09 PM PDT 24	May 05 04:43:11 PM PDT 24	2829980885 ps
T303	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.717742643			May 05 04:25:55 PM PDT 24	May 05 04:40:22 PM PDT 24	5519916278 ps
T379	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425311024			May 05 04:53:23 PM PDT 24	May 05 04:59:27 PM PDT 24	3185245696 ps
T163	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4213719901			May 05 04:43:44 PM PDT 24	May 05 04:47:19 PM PDT 24	2548128106 ps
T341	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1382394847			May 05 04:30:06 PM PDT 24	May 05 04:42:04 PM PDT 24	5007419720 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1882269262			May 05 04:21:22 PM PDT 24	May 05 04:54:40 PM PDT 24	8204387160 ps
T888	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.328695498			May 05 04:37:02 PM PDT 24	May 05 04:46:45 PM PDT 24	4382770120 ps
T889	/workspace/coverage/default/1.chip_sw_kmac_entropy.2149396434			May 05 04:28:24 PM PDT 24	May 05 04:33:10 PM PDT 24	2702645360 ps
T740	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199917895			May 05 04:52:47 PM PDT 24	May 05 04:56:42 PM PDT 24	4007475600 ps
T174	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3923954904			May 05 04:21:21 PM PDT 24	May 05 04:30:08 PM PDT 24	3950120360 ps
T349	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.330602326			May 05 04:51:55 PM PDT 24	May 05 04:59:39 PM PDT 24	3570530862 ps
T36	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2611588804			May 05 04:38:02 PM PDT 24	May 05 04:43:12 PM PDT 24	2754817980 ps
T890	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2177913849			May 05 04:38:29 PM PDT 24	May 05 04:46:59 PM PDT 24	4530161943 ps
T891	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3551166051			May 05 04:43:55 PM PDT 24	May 05 04:56:08 PM PDT 24	4449376440 ps
T196	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1868893777			May 05 04:42:26 PM PDT 24	May 05 05:11:25 PM PDT 24	7554552060 ps
T892	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.37685054			May 05 04:24:10 PM PDT 24	May 05 04:37:12 PM PDT 24	7456418300 ps
T893	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3931925584			May 05 04:44:28 PM PDT 24	May 05 04:53:18 PM PDT 24	4310626928 ps
T694	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2899063543			May 05 04:36:57 PM PDT 24	May 05 04:47:15 PM PDT 24	5224908732 ps
T894	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301621761			May 05 04:23:36 PM PDT 24	May 05 04:30:10 PM PDT 24	3989587840 ps
T895	/workspace/coverage/default/2.chip_sw_aon_timer_irq.2230032671			May 05 04:39:12 PM PDT 24	May 05 04:47:11 PM PDT 24	4275979028 ps
T693	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3473961382			May 05 04:47:46 PM PDT 24	May 05 04:54:45 PM PDT 24	3346483310 ps
T363	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1743549009			May 05 04:40:09 PM PDT 24	May 05 05:31:01 PM PDT 24	15731811490 ps
T188	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.34032170			May 05 04:48:35 PM PDT 24	May 05 05:15:41 PM PDT 24	8428620486 ps
T217	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2271568349			May 05 04:23:05 PM PDT 24	May 05 04:30:42 PM PDT 24	5025220000 ps
T896	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1683752702			May 05 04:43:56 PM PDT 24	May 05 04:51:49 PM PDT 24	4569816984 ps
T214	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3650367990			May 05 04:28:40 PM PDT 24	May 05 04:41:37 PM PDT 24	6150221350 ps
T239	/workspace/coverage/default/2.chip_sw_aes_enc.3551232153			May 05 04:39:28 PM PDT 24	May 05 04:43:13 PM PDT 24	2486873864 ps
T240	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2865552421			May 05 04:23:13 PM PDT 24	May 05 04:30:35 PM PDT 24	6880308542 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3587660981			May 05 04:39:13 PM PDT 24	May 05 04:47:56 PM PDT 24	4628619433 ps
T241	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3502468930			May 05 04:39:55 PM PDT 24	May 05 04:53:57 PM PDT 24	6224162128 ps
T183	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2550984734			May 05 04:40:02 PM PDT 24	May 05 04:44:33 PM PDT 24	3583460453 ps
T242	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2497705400			May 05 04:54:09 PM PDT 24	May 05 05:01:33 PM PDT 24	4941463664 ps
T243	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2798151882			May 05 04:54:09 PM PDT 24	May 05 05:05:26 PM PDT 24	4885349416 ps
T244	/workspace/coverage/default/90.chip_sw_all_escalation_resets.285573705			May 05 04:53:24 PM PDT 24	May 05 05:04:48 PM PDT 24	5344984804 ps
T245	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1752128791			May 05 04:50:03 PM PDT 24	May 05 05:00:46 PM PDT 24	4996774992 ps
T749	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1772085940			May 05 04:53:47 PM PDT 24	May 05 04:59:38 PM PDT 24	3603712150 ps
T689	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366717951			May 05 04:51:18 PM PDT 24	May 05 04:56:49 PM PDT 24	4148462680 ps
T692	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1386802694			May 05 04:51:09 PM PDT 24	May 05 05:01:50 PM PDT 24	4740787280 ps
T329	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.768904017			May 05 04:26:40 PM PDT 24	May 05 04:32:20 PM PDT 24	2678129000 ps
T230	/workspace/coverage/default/57.chip_sw_all_escalation_resets.924505843			May 05 04:56:46 PM PDT 24	May 05 05:05:57 PM PDT 24	4533655440 ps
T258	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.676429889			May 05 04:36:29 PM PDT 24	May 05 04:49:09 PM PDT 24	4713318318 ps
T695	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.750673302			May 05 04:21:06 PM PDT 24	May 05 04:32:10 PM PDT 24	6086065384 ps
T897	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2360838919			May 05 04:24:37 PM PDT 24	May 05 04:32:19 PM PDT 24	4955312504 ps
T246	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.62904745			May 05 04:26:41 PM PDT 24	May 05 04:28:11 PM PDT 24	2184604520 ps
T754	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1940750687			May 05 04:53:10 PM PDT 24	May 05 04:59:00 PM PDT 24	4104267588 ps
T898	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.581270614			May 05 04:40:01 PM PDT 24	May 05 04:54:31 PM PDT 24	4854821177 ps
T697	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2095380291			May 05 04:52:47 PM PDT 24	May 05 04:58:23 PM PDT 24	3974144568 ps