Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136618	1			T70	86		T71	77		T72	81
values[2]	8605	1			T70	3		T71	3		T72	5
values[3]	2769	1			T424	1		T417	1		T380	2
values[4]	1567	1			T424	1		T380	3		T512	3
values[5]	1065	1			T424	1		T380	4		T512	5
values[6]	765	1			T424	1		T380	1		T512	5
values[7]	605	1			T424	1		T380	4		T512	7
values[8]	536	1			T424	1		T380	1		T512	3
values[9]	465	1			T424	1		T380	1		T512	6
values[10]	458	1			T424	1		T380	1		T512	3
values[11]	422	1			T424	1		T380	2		T512	3
values[12]	460	1			T424	1		T380	1		T512	2
values[13]	438	1			T424	1		T380	1		T512	1
values[14]	358	1			T424	1		T380	1		T512	1
values[15]	389	1			T424	1		T380	3		T512	6
values[16]	391	1			T424	1		T380	1		T512	3
values[17]	401	1			T424	1		T380	1		T512	2
values[18]	377	1			T424	1		T380	3		T512	3
values[19]	336	1			T424	1		T380	2		T512	6
values[20]	371	1			T424	1		T380	6		T512	6
values[21]	330	1			T424	1		T380	5		T512	6
values[22]	360	1			T424	1		T380	5		T512	7
values[23]	314	1			T424	1		T380	4		T512	13
values[24]	308	1			T424	1		T380	5		T512	7
values[25]	308	1			T424	1		T380	1		T512	2
values[26]	286	1			T424	1		T380	2		T512	2
values[27]	298	1			T424	1		T380	1		T512	2
values[28]	318	1			T424	1		T380	1		T512	2
values[29]	300	1			T424	1		T380	5		T512	2
values[30]	331	1			T424	1		T380	2		T512	5
values[31]	331	1			T424	1		T380	2		T512	3
values[32]	360	1			T424	1		T380	4		T512	1
values[33]	316	1			T424	1		T380	8		T512	2
values[34]	363	1			T424	1		T380	4		T512	7
values[35]	333	1			T424	1		T380	2		T512	7
values[36]	315	1			T424	1		T380	3		T512	7
values[37]	295	1			T424	1		T380	4		T512	6
values[38]	317	1			T424	1		T380	1		T512	13
values[39]	299	1			T424	1		T380	2		T512	9
values[40]	302	1			T424	1		T380	1		T512	7
values[41]	314	1			T424	1		T380	1		T512	6
values[42]	315	1			T424	1		T380	3		T512	1
values[43]	345	1			T424	1		T380	3		T512	2
values[44]	303	1			T424	1		T380	2		T512	4
values[45]	301	1			T424	1		T380	4		T512	10
values[46]	266	1			T424	1		T380	5		T512	1
values[47]	298	1			T424	1		T380	5		T512	4
values[48]	263	1			T424	1		T380	8		T512	4
values[49]	267	1			T424	1		T380	6		T512	1
values[50]	222	1			T424	1		T380	2		T512	1
values[51]	241	1			T424	1		T380	1		T512	2
values[52]	246	1			T424	1		T380	2		T512	3
values[53]	276	1			T424	1		T380	4		T512	2
values[54]	272	1			T424	1		T380	2		T512	1
values[55]	269	1			T424	1		T380	10		T429	18
values[56]	269	1			T424	1		T380	6		T429	15
values[57]	260	1			T424	1		T380	2		T429	10
values[58]	188	1			T424	1		T380	1		T429	7
values[59]	217	1			T424	1		T380	1		T429	14
values[60]	199	1			T424	1		T380	2		T429	5
values[61]	202	1			T424	1		T380	1		T429	3
values[62]	174	1			T424	1		T380	2		T429	8
values[63]	171	1			T424	1		T380	4		T429	3
values[64]	169	1			T424	1		T380	4		T429	3
values[65]	187	1			T424	1		T380	8		T429	3
values[66]	146	1			T424	1		T380	5		T429	1
values[67]	163	1			T424	1		T380	8		T432	3
values[68]	142	1			T424	1		T380	4		T425	11
values[69]	132	1			T424	1		T380	3		T425	3
values[70]	118	1			T424	2		T380	2		T425	3
values[71]	116	1			T424	1		T380	3		T425	7
values[72]	122	1			T424	1		T380	7		T425	4
values[73]	109	1			T424	1		T380	11		T501	1
values[74]	118	1			T424	1		T380	15		T501	1
values[75]	125	1			T424	1		T380	13		T501	1
values[76]	94	1			T424	1		T380	4		T501	1
values[77]	83	1			T424	1		T380	10		T501	1
values[78]	68	1			T424	1		T380	10		T501	1
values[79]	111	1			T424	1		T380	2		T501	1
values[80]	98	1			T424	1		T501	1		T461	11
values[81]	89	1			T424	1		T501	1		T461	3
values[82]	82	1			T424	1		T501	1		T461	2
values[83]	78	1			T424	1		T501	1		T461	2
values[84]	69	1			T424	1		T501	1		T461	4
values[85]	66	1			T424	1		T501	1		T461	5
values[86]	76	1			T424	1		T501	2		T461	4
values[87]	88	1			T424	1		T501	3		T461	4
values[88]	83	1			T424	1		T501	3		T461	2
values[89]	101	1			T424	1		T501	1		T461	4
values[90]	111	1			T424	1		T501	9		T461	4
values[91]	95	1			T424	1		T501	1		T461	5
values[92]	89	1			T424	1		T501	2		T461	5
values[93]	79	1			T424	1		T501	2		T461	5
values[94]	90	1			T424	1		T501	6		T461	8
values[95]	77	1			T424	1		T501	1		T461	11
values[96]	80	1			T424	1		T501	2		T461	8
values[97]	72	1			T424	1		T501	2		T461	3
values[98]	60	1			T424	1		T501	1		T471	1
values[99]	76	1			T424	1		T501	6		T471	1
values[100]	98	1			T424	1		T501	4		T471	1
values[101]	76	1			T424	1		T501	1		T471	1
values[102]	78	1			T424	2		T501	5		T471	2
values[103]	61	1			T424	3		T501	8		T471	4
values[104]	63	1			T424	2		T501	3		T471	2
values[105]	62	1			T424	1		T501	4		T471	5
values[106]	71	1			T424	2		T501	7		T471	1
values[107]	67	1			T424	5		T501	4		T471	2
values[108]	54	1			T424	5		T501	2		T471	1
values[109]	49	1			T424	1		T501	1		T471	2
values[110]	72	1			T424	3		T501	4		T471	8
values[111]	46	1			T424	1		T501	2		T471	1
values[112]	61	1			T424	2		T501	1		T471	5
values[113]	53	1			T424	1		T501	1		T471	6
values[114]	60	1			T424	2		T501	1		T471	5
values[115]	67	1			T424	5		T501	4		T471	1
values[116]	48	1			T424	1		T501	1		T471	1
values[117]	53	1			T424	1		T501	1		T471	1
values[118]	55	1			T424	1		T501	3		T471	1
values[119]	58	1			T424	2		T501	5		T471	2
values[120]	65	1			T424	2		T501	1		T471	3
values[121]	47	1			T424	2		T501	4		T471	1
values[122]	81	1			T424	3		T501	4		T471	4
values[123]	69	1			T424	4		T501	1		T471	8
values[124]	55	1			T424	2		T501	1		T471	1
values[125]	54	1			T424	1		T501	1		T471	2
values[126]	84	1			T424	4		T501	5		T471	3
values[127]	779	1			T424	32		T501	32		T471	40
values[128]	6880	1			T424	311		T501	283		T471	339