Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137703	1			T70	65		T71	71		T72	75
values[2]	10293	1			T72	3		T222	4		T386	5
values[3]	4542	1			T72	1		T424	1		T508	1
values[4]	2396	1			T424	1		T508	2		T480	32
values[5]	1504	1			T424	1		T508	1		T480	24
values[6]	959	1			T424	1		T508	4		T480	29
values[7]	699	1			T424	1		T508	1		T480	32
values[8]	621	1			T424	1		T508	3		T480	17
values[9]	600	1			T424	1		T508	3		T480	28
values[10]	512	1			T424	1		T508	4		T480	20
values[11]	455	1			T424	1		T508	2		T480	14
values[12]	460	1			T424	1		T508	1		T480	12
values[13]	436	1			T424	1		T508	6		T480	26
values[14]	400	1			T424	1		T508	13		T480	4
values[15]	361	1			T424	1		T508	6		T480	22
values[16]	348	1			T424	1		T508	2		T480	5
values[17]	310	1			T424	1		T508	10		T480	5
values[18]	358	1			T424	1		T508	13		T480	7
values[19]	315	1			T424	1		T508	13		T480	14
values[20]	330	1			T424	1		T508	6		T480	11
values[21]	395	1			T424	1		T508	8		T480	5
values[22]	321	1			T424	1		T508	7		T480	4
values[23]	335	1			T424	1		T508	10		T480	6
values[24]	286	1			T424	1		T508	5		T480	8
values[25]	276	1			T424	1		T508	6		T480	14
values[26]	253	1			T424	1		T508	3		T480	7
values[27]	314	1			T424	1		T508	9		T480	22
values[28]	319	1			T424	1		T508	3		T480	16
values[29]	288	1			T424	1		T508	4		T480	5
values[30]	256	1			T424	1		T508	3		T480	4
values[31]	283	1			T424	1		T508	4		T480	12
values[32]	272	1			T424	1		T508	4		T480	8
values[33]	288	1			T424	2		T508	2		T480	5
values[34]	272	1			T424	1		T508	1		T480	11
values[35]	241	1			T424	1		T508	2		T480	5
values[36]	296	1			T424	1		T508	3		T480	19
values[37]	240	1			T424	1		T508	1		T480	10
values[38]	293	1			T424	1		T508	2		T480	15
values[39]	285	1			T424	1		T508	2		T480	8
values[40]	221	1			T424	1		T508	7		T480	6
values[41]	216	1			T424	1		T508	6		T480	13
values[42]	229	1			T424	1		T508	5		T480	19
values[43]	202	1			T424	1		T508	2		T480	6
values[44]	188	1			T424	1		T508	8		T480	5
values[45]	291	1			T424	1		T508	4		T480	21
values[46]	184	1			T424	1		T508	3		T480	9
values[47]	164	1			T424	1		T508	1		T480	18
values[48]	136	1			T424	1		T508	1		T480	6
values[49]	118	1			T424	1		T508	2		T480	8
values[50]	95	1			T424	1		T508	2		T480	5
values[51]	117	1			T424	1		T508	3		T480	3
values[52]	103	1			T424	1		T508	3		T480	9
values[53]	118	1			T424	1		T508	4		T480	3
values[54]	93	1			T424	1		T508	5		T501	1
values[55]	88	1			T424	1		T508	3		T501	1
values[56]	76	1			T424	1		T508	4		T501	1
values[57]	58	1			T424	1		T508	4		T501	1
values[58]	67	1			T424	1		T508	9		T501	1
values[59]	71	1			T424	1		T508	6		T501	1
values[60]	55	1			T424	1		T508	4		T501	1
values[61]	50	1			T424	1		T508	2		T501	1
values[62]	49	1			T424	1		T508	5		T501	1
values[63]	46	1			T424	1		T508	2		T501	1
values[64]	53	1			T424	1		T508	1		T501	1
values[65]	62	1			T424	1		T508	6		T501	1
values[66]	65	1			T424	1		T508	14		T501	1
values[67]	73	1			T424	1		T508	5		T501	1
values[68]	64	1			T424	1		T508	2		T501	1
values[69]	60	1			T424	1		T508	3		T501	1
values[70]	83	1			T424	1		T508	2		T501	1
values[71]	58	1			T424	1		T508	6		T501	1
values[72]	70	1			T424	1		T508	13		T501	1
values[73]	64	1			T424	1		T508	13		T501	1
values[74]	41	1			T424	1		T508	4		T501	1
values[75]	56	1			T424	1		T508	8		T501	1
values[76]	72	1			T424	1		T508	11		T501	1
values[77]	63	1			T424	1		T508	8		T501	1
values[78]	66	1			T424	1		T508	9		T501	1
values[79]	85	1			T424	1		T508	13		T501	1
values[80]	75	1			T424	1		T508	14		T501	1
values[81]	54	1			T424	1		T508	9		T501	1
values[82]	78	1			T424	2		T508	11		T501	1
values[83]	57	1			T424	1		T508	2		T501	1
values[84]	49	1			T424	1		T508	3		T501	1
values[85]	63	1			T424	3		T508	1		T501	1
values[86]	61	1			T424	3		T508	4		T501	1
values[87]	56	1			T424	3		T508	5		T501	1
values[88]	69	1			T424	2		T508	2		T501	1
values[89]	80	1			T424	2		T508	2		T501	1
values[90]	82	1			T424	7		T508	3		T501	1
values[91]	89	1			T424	3		T508	4		T501	1
values[92]	85	1			T424	2		T508	1		T501	1
values[93]	87	1			T424	6		T508	2		T501	1
values[94]	66	1			T424	3		T508	2		T501	1
values[95]	55	1			T424	1		T508	2		T501	1
values[96]	68	1			T424	1		T508	3		T501	1
values[97]	75	1			T424	4		T508	6		T501	1
values[98]	61	1			T424	2		T508	1		T501	2
values[99]	66	1			T424	2		T508	9		T501	1
values[100]	54	1			T424	2		T508	7		T501	1
values[101]	64	1			T424	3		T508	2		T501	1
values[102]	48	1			T424	1		T508	6		T501	1
values[103]	57	1			T424	1		T508	13		T501	1
values[104]	74	1			T424	3		T508	13		T501	1
values[105]	66	1			T424	1		T508	2		T501	1
values[106]	57	1			T424	3		T501	1		T474	2
values[107]	42	1			T424	1		T501	1		T474	2
values[108]	61	1			T424	3		T501	1		T474	3
values[109]	62	1			T424	8		T501	3		T474	2
values[110]	42	1			T424	1		T501	8		T474	2
values[111]	40	1			T424	4		T501	1		T474	2
values[112]	37	1			T424	1		T501	1		T474	2
values[113]	37	1			T424	2		T501	3		T474	2
values[114]	30	1			T424	3		T501	4		T474	2
values[115]	30	1			T424	2		T501	3		T474	3
values[116]	29	1			T424	1		T501	3		T474	2
values[117]	29	1			T424	1		T501	2		T474	2
values[118]	29	1			T424	1		T501	3		T474	2
values[119]	29	1			T424	1		T501	2		T474	2
values[120]	33	1			T424	1		T501	1		T474	2
values[121]	34	1			T424	1		T501	5		T474	2
values[122]	37	1			T424	2		T501	1		T474	2
values[123]	39	1			T424	5		T501	1		T474	6
values[124]	31	1			T424	5		T501	1		T474	4
values[125]	40	1			T424	2		T501	6		T474	6
values[126]	86	1			T424	5		T501	5		T474	8
values[127]	989	1			T424	63		T501	56		T474	126
values[128]	4521	1			T424	230		T501	237		T474	655