| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| big_delay | 200 | 1 | T71 | 1 | T221 | 1 | T222 | 1 | ||||
| small_delay | 967 | 1 | T70 | 1 | T72 | 1 | T462 | 1 | ||||
| zero | 633 | 1 | T511 | 1 | T516 | 1 | T520 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |