Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T418	2		T380	6		T395	2
all_values[1]	423	1			T434	2		T424	1		T418	1
all_values[2]	484	1			T424	1		T380	3		T508	1
all_values[3]	436	1			T434	7		T395	3		T480	2
all_values[4]	469	1			T434	3		T380	4		T395	3
all_values[5]	461	1			T380	2		T395	4		T512	2
all_values[6]	455	1			T434	1		T424	1		T380	1
all_values[7]	470	1			T434	5		T424	2		T380	4
all_values[8]	446	1			T434	3		T380	3		T395	3
all_values[9]	494	1			T434	3		T418	2		T380	2
all_values[10]	430	1			T434	1		T380	3		T508	1
all_values[11]	456	1			T434	3		T380	2		T508	1
all_values[12]	432	1			T434	3		T380	3		T801	1
all_values[13]	468	1			T434	4		T380	2		T801	1
all_values[14]	437	1			T434	3		T380	4		T508	1
all_values[15]	430	1			T434	4		T424	1		T380	6
all_values[16]	431	1			T434	3		T380	6		T512	4
all_values[17]	432	1			T434	1		T424	1		T380	4
all_values[18]	442	1			T434	5		T380	6		T508	1
all_values[19]	456	1			T380	2		T801	2		T395	2
all_values[20]	448	1			T434	4		T380	4		T508	1
all_values[21]	472	1			T434	2		T380	3		T395	1
all_values[22]	487	1			T434	4		T418	1		T380	3
all_values[23]	444	1			T434	1		T380	3		T395	3
all_values[24]	457	1			T434	3		T418	1		T380	5
all_values[25]	460	1			T434	3		T424	1		T418	2
all_values[26]	488	1			T434	2		T418	2		T380	6
all_values[27]	501	1			T434	5		T424	1		T508	1
all_values[28]	437	1			T434	3		T424	1		T380	3
all_values[29]	453	1			T434	1		T418	2		T380	3
all_values[30]	463	1			T434	4		T380	4		T395	2
all_values[31]	429	1			T380	4		T801	1		T395	3
all_values[32]	449	1			T434	4		T418	1		T380	8
all_values[33]	507	1			T434	1		T380	6		T395	4
all_values[34]	481	1			T434	4		T424	1		T380	3
all_values[35]	470	1			T434	1		T418	2		T380	7
all_values[36]	434	1			T434	2		T424	1		T380	4
all_values[37]	473	1			T434	1		T380	6		T395	1
all_values[38]	444	1			T434	4		T424	1		T380	4
all_values[39]	507	1			T434	2		T418	1		T380	7
all_values[40]	474	1			T434	3		T380	4		T395	5
all_values[41]	447	1			T434	2		T418	1		T380	6
all_values[42]	459	1			T418	2		T380	5		T395	3
all_values[43]	428	1			T434	3		T424	1		T418	1
all_values[44]	431	1			T434	1		T424	1		T418	1
all_values[45]	496	1			T434	3		T380	5		T395	1
all_values[46]	441	1			T434	4		T380	2		T395	3
all_values[47]	464	1			T434	1		T418	1		T380	4
all_values[48]	492	1			T434	3		T380	8		T801	1
all_values[49]	465	1			T434	4		T424	1		T380	1