Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3502	1			T70	1		T386	6		T434	31
all_values[1]	3395	1			T70	1		T462	1		T386	14
all_values[2]	3489	1			T462	4		T386	7		T434	17
all_values[3]	3502	1			T70	1		T386	12		T434	25
all_values[4]	3504	1			T70	1		T462	2		T386	7
all_values[5]	3399	1			T70	3		T386	17		T434	16
all_values[6]	3588	1			T70	5		T462	1		T386	6
all_values[7]	3453	1			T70	1		T462	1		T386	7
all_values[8]	3453	1			T70	3		T462	3		T386	7
all_values[9]	3474	1			T462	2		T386	7		T434	26
all_values[10]	3481	1			T70	3		T386	6		T434	20
all_values[11]	3385	1			T70	4		T386	6		T434	19
all_values[12]	3432	1			T70	3		T462	1		T386	5
all_values[13]	3464	1			T70	1		T462	1		T386	11
all_values[14]	3469	1			T462	1		T386	8		T434	19
all_values[15]	3533	1			T70	4		T386	11		T434	24
all_values[16]	3502	1			T70	3		T462	3		T386	5
all_values[17]	3504	1			T70	2		T386	13		T434	27
all_values[18]	3492	1			T70	4		T462	1		T386	8
all_values[19]	3455	1			T70	2		T462	1		T386	7
all_values[20]	3514	1			T70	3		T462	1		T386	4
all_values[21]	3500	1			T70	5		T462	1		T386	14
all_values[22]	3603	1			T70	3		T462	2		T386	7
all_values[23]	3435	1			T462	1		T386	4		T434	19
all_values[24]	3496	1			T70	2		T462	3		T386	5
all_values[25]	3504	1			T70	1		T462	1		T386	7
all_values[26]	3404	1			T462	1		T386	9		T434	20
all_values[27]	3551	1			T70	3		T386	6		T434	19
all_values[28]	3473	1			T70	2		T462	2		T386	8
all_values[29]	3505	1			T70	1		T462	1		T386	13
all_values[30]	3369	1			T70	3		T462	3		T386	5
all_values[31]	3397	1			T70	1		T462	3		T386	5
all_values[32]	3565	1			T70	1		T462	4		T386	8
all_values[33]	3597	1			T70	1		T462	1		T386	6
all_values[34]	3376	1			T70	1		T462	3		T386	5
all_values[35]	3389	1			T70	1		T386	8		T434	14
all_values[36]	3468	1			T70	3		T386	4		T434	22
all_values[37]	3457	1			T70	5		T462	1		T386	7
all_values[38]	3505	1			T70	5		T462	3		T386	8
all_values[39]	3479	1			T70	3		T386	8		T434	26
all_values[40]	3367	1			T70	1		T462	1		T386	9
all_values[41]	3367	1			T70	2		T462	1		T386	9
all_values[42]	3488	1			T70	4		T462	4		T386	10
all_values[43]	3531	1			T70	2		T386	7		T434	21
all_values[44]	3476	1			T70	2		T462	2		T386	5
all_values[45]	3415	1			T70	4		T462	1		T386	8
all_values[46]	3372	1			T70	2		T462	4		T386	5
all_values[47]	3545	1			T462	2		T386	4		T434	26
all_values[48]	3585	1			T70	5		T386	4		T434	17
all_values[49]	3483	1			T70	2		T462	2		T386	13
all_values[50]	3436	1			T70	4		T462	2		T386	11
all_values[51]	3500	1			T70	4		T386	4		T434	24
all_values[52]	3558	1			T70	4		T386	6		T434	24
all_values[53]	3445	1			T70	2		T462	2		T386	8
all_values[54]	3461	1			T70	1		T386	9		T434	19
all_values[55]	3528	1			T70	2		T462	1		T386	3
all_values[56]	3476	1			T70	3		T462	1		T386	7
all_values[57]	3491	1			T70	2		T462	3		T386	7
all_values[58]	3492	1			T70	1		T462	3		T386	4
all_values[59]	3442	1			T70	3		T462	2		T386	16
all_values[60]	3457	1			T70	2		T462	1		T386	4
all_values[61]	3464	1			T70	6		T462	3		T386	7
all_values[62]	3516	1			T70	2		T462	3		T386	10
all_values[63]	3351	1			T70	2		T462	2		T386	10