Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139979	1			T71	86		T72	4		T73	33
values[2]	9210	1			T146	4		T222	3		T510	1
values[3]	3563	1			T499	1		T505	73		T820	81
values[4]	2013	1			T505	79		T820	41		T606	1
values[5]	1265	1			T505	60		T820	36		T606	3
values[6]	825	1			T505	35		T820	17		T606	1
values[7]	637	1			T505	24		T820	2		T606	3
values[8]	471	1			T505	29		T606	4		T432	1
values[9]	349	1			T505	12		T606	6		T432	1
values[10]	357	1			T505	4		T606	7		T432	1
values[11]	267	1			T505	1		T606	2		T432	1
values[12]	259	1			T606	4		T432	1		T412	1
values[13]	266	1			T606	4		T432	1		T412	1
values[14]	265	1			T606	4		T432	1		T412	2
values[15]	252	1			T606	8		T432	1		T412	1
values[16]	193	1			T606	3		T432	1		T412	1
values[17]	230	1			T606	6		T432	1		T412	1
values[18]	189	1			T606	3		T432	1		T412	1
values[19]	202	1			T606	2		T432	1		T412	1
values[20]	230	1			T606	4		T432	1		T412	1
values[21]	209	1			T606	1		T432	1		T412	1
values[22]	246	1			T606	2		T432	1		T412	1
values[23]	213	1			T606	6		T432	1		T412	1
values[24]	216	1			T606	3		T432	1		T412	1
values[25]	217	1			T606	1		T432	1		T412	1
values[26]	189	1			T606	2		T432	1		T412	1
values[27]	233	1			T606	2		T432	1		T412	1
values[28]	168	1			T606	2		T432	1		T412	1
values[29]	199	1			T606	4		T432	1		T412	1
values[30]	261	1			T606	5		T432	1		T412	1
values[31]	234	1			T606	2		T432	1		T412	1
values[32]	179	1			T606	3		T432	1		T412	1
values[33]	187	1			T606	7		T432	1		T412	1
values[34]	202	1			T606	10		T432	1		T412	1
values[35]	216	1			T606	3		T432	1		T412	1
values[36]	214	1			T606	7		T432	1		T412	1
values[37]	223	1			T606	7		T432	1		T412	1
values[38]	265	1			T606	6		T432	1		T412	1
values[39]	216	1			T606	6		T432	1		T412	1
values[40]	207	1			T606	4		T432	1		T412	1
values[41]	187	1			T606	4		T432	1		T412	1
values[42]	188	1			T606	1		T432	1		T412	1
values[43]	180	1			T606	6		T432	1		T412	1
values[44]	197	1			T606	1		T432	2		T412	1
values[45]	210	1			T606	2		T432	1		T412	1
values[46]	213	1			T606	2		T432	1		T412	1
values[47]	179	1			T606	2		T432	1		T412	1
values[48]	181	1			T606	2		T432	1		T412	1
values[49]	190	1			T606	1		T432	1		T412	1
values[50]	228	1			T606	3		T432	1		T412	1
values[51]	185	1			T606	5		T432	1		T412	1
values[52]	215	1			T606	7		T432	1		T412	1
values[53]	201	1			T606	11		T432	1		T412	1
values[54]	191	1			T606	2		T432	1		T412	1
values[55]	174	1			T606	2		T432	1		T412	1
values[56]	128	1			T606	1		T432	1		T412	1
values[57]	139	1			T606	4		T432	1		T412	1
values[58]	146	1			T606	1		T432	1		T412	1
values[59]	151	1			T606	3		T432	1		T412	1
values[60]	143	1			T606	6		T432	1		T412	1
values[61]	165	1			T606	5		T432	1		T412	1
values[62]	151	1			T606	7		T432	1		T412	1
values[63]	133	1			T606	3		T432	1		T412	1
values[64]	166	1			T606	1		T432	1		T412	1
values[65]	218	1			T606	2		T432	1		T412	1
values[66]	203	1			T606	3		T432	1		T412	2
values[67]	133	1			T606	4		T432	1		T412	1
values[68]	118	1			T606	2		T432	1		T412	1
values[69]	86	1			T606	1		T432	1		T412	1
values[70]	115	1			T606	2		T432	1		T412	1
values[71]	96	1			T606	1		T432	1		T412	1
values[72]	76	1			T606	1		T432	1		T412	1
values[73]	89	1			T606	1		T432	1		T412	1
values[74]	91	1			T606	2		T432	1		T412	1
values[75]	76	1			T606	4		T432	1		T412	1
values[76]	70	1			T606	4		T432	1		T412	1
values[77]	82	1			T606	2		T432	1		T412	1
values[78]	75	1			T606	4		T432	1		T412	1
values[79]	79	1			T606	3		T432	1		T412	1
values[80]	92	1			T606	4		T432	1		T412	1
values[81]	67	1			T606	5		T432	1		T412	1
values[82]	55	1			T606	3		T432	1		T412	1
values[83]	66	1			T606	9		T432	1		T412	1
values[84]	66	1			T606	4		T432	1		T412	1
values[85]	60	1			T606	5		T432	1		T412	1
values[86]	66	1			T606	2		T432	1		T412	1
values[87]	70	1			T606	1		T432	1		T412	1
values[88]	69	1			T606	2		T432	1		T412	1
values[89]	75	1			T606	1		T432	1		T412	1
values[90]	89	1			T606	1		T432	1		T412	1
values[91]	61	1			T606	2		T432	1		T412	1
values[92]	68	1			T606	2		T432	1		T412	1
values[93]	52	1			T606	2		T432	1		T412	1
values[94]	55	1			T606	1		T432	1		T412	1
values[95]	52	1			T606	4		T432	1		T412	1
values[96]	60	1			T606	3		T432	1		T412	1
values[97]	51	1			T606	2		T432	1		T412	1
values[98]	55	1			T606	3		T432	1		T412	1
values[99]	68	1			T606	2		T432	1		T412	1
values[100]	62	1			T606	1		T432	1		T412	1
values[101]	51	1			T606	1		T432	1		T412	1
values[102]	48	1			T606	5		T432	1		T412	1
values[103]	72	1			T606	2		T432	1		T412	1
values[104]	54	1			T606	5		T432	1		T412	1
values[105]	62	1			T606	10		T432	1		T412	1
values[106]	57	1			T606	3		T432	1		T412	1
values[107]	67	1			T606	3		T432	1		T412	3
values[108]	46	1			T606	1		T432	1		T412	1
values[109]	71	1			T606	7		T432	1		T412	2
values[110]	64	1			T606	12		T432	1		T412	1
values[111]	64	1			T606	3		T432	1		T412	3
values[112]	48	1			T606	6		T432	1		T412	1
values[113]	62	1			T606	1		T432	1		T412	1
values[114]	69	1			T606	1		T432	1		T412	1
values[115]	71	1			T606	3		T432	1		T412	4
values[116]	50	1			T606	2		T432	1		T412	1
values[117]	67	1			T606	13		T432	3		T412	3
values[118]	74	1			T606	13		T432	4		T412	1
values[119]	63	1			T606	7		T432	2		T412	3
values[120]	71	1			T606	8		T432	2		T412	1
values[121]	39	1			T606	2		T432	1		T412	1
values[122]	65	1			T606	2		T432	2		T412	1
values[123]	62	1			T606	5		T432	1		T412	8
values[124]	58	1			T606	2		T432	1		T412	2
values[125]	89	1			T606	5		T432	1		T412	4
values[126]	132	1			T606	19		T432	4		T412	4
values[127]	783	1			T606	30		T432	22		T412	35
values[128]	6710	1			T606	11		T432	272		T412	361