Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	95.41	94.46	95.56		95.36	97.38	99.57

Total tests in report: 2771

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.50	40.50	45.92	45.92	43.19	43.19	32.19	32.19			58.30	58.30	63.03	63.03	0.39	0.39	/workspace/coverage/default/58.chip_sw_all_escalation_resets.2862159297
50.34	9.84	54.93	9.02	53.06	9.87	35.59	3.39			67.12	8.82	90.76	27.73	0.59	0.20	/workspace/coverage/default/1.chip_jtag_csr_rw.3413351315
56.67	6.33	64.04	9.10	56.74	3.68	42.03	6.44			67.46	0.34	90.76	0.00	19.00	18.41	/workspace/coverage/cover_reg_top/55.xbar_stress_all.2359219815
61.91	5.24	75.32	11.28	64.20	7.46	44.89	2.86			77.29	9.83	90.76	0.00	19.00	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3060623558
66.03	4.12	75.32	0.00	65.40	1.20	44.89	0.00			77.69	0.40	90.76	0.00	42.09	23.09	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.495346785
68.89	2.87	75.32	0.00	66.61	1.21	44.89	0.00			78.20	0.51	90.76	0.00	57.58	15.50	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1485121401
71.48	2.59	75.32	0.00	66.61	0.00	60.41	15.51			78.20	0.00	90.76	0.00	57.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3634389374
73.84	2.36	80.60	5.27	70.45	3.85	63.90	3.49			79.76	1.56	90.76	0.00	57.58	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4129466637
76.16	2.32	83.13	2.54	76.53	6.08	64.24	0.33			83.77	4.01	90.76	0.00	58.52	0.94	/workspace/coverage/cover_reg_top/3.chip_csr_rw.453862975
78.42	2.26	85.51	2.37	79.50	2.97	68.56	4.33			85.93	2.16	90.94	0.18	60.06	1.54	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3813968483
80.25	1.83	85.51	0.00	79.50	0.00	68.56	0.00			85.93	0.00	90.94	0.00	71.04	10.97	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1396298723
81.81	1.56	85.74	0.24	79.66	0.16	76.99	8.43			86.11	0.18	91.31	0.37	71.04	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1365924519
83.17	1.36	87.81	2.07	81.13	1.47	79.43	2.43			88.09	1.98	91.50	0.18	71.04	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1889731346
84.27	1.11	87.81	0.00	81.13	0.00	79.43	0.00			88.09	0.00	91.50	0.00	77.68	6.64	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4187854364
85.38	1.10	87.81	0.00	81.13	0.00	79.43	0.00			88.09	0.00	91.50	0.00	84.30	6.63	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3840663711
86.47	1.09	89.23	1.42	83.23	2.10	80.52	1.10			90.04	1.94	91.50	0.00	84.30	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1196465456
87.37	0.90	90.45	1.22	84.18	0.96	82.60	2.08			91.20	1.16	91.50	0.00	84.30	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2149350729
88.11	0.74	90.60	0.15	84.27	0.09	82.62	0.02			91.31	0.11	95.56	4.07	84.30	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4149842176
88.75	0.64	91.56	0.96	85.05	0.78	83.24	0.62			92.18	0.87	96.12	0.55	84.33	0.02	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.880077889
89.36	0.61	91.60	0.04	85.77	0.72	83.95	0.71			92.22	0.04	96.12	0.00	86.48	2.15	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3429276548
89.93	0.58	92.64	1.04	86.79	1.02	84.38	0.44			93.18	0.96	96.12	0.00	86.48	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.2735520595
90.44	0.51	92.65	0.01	86.79	0.01	87.42	3.03			93.18	0.00	96.12	0.00	86.51	0.04	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2338287376
90.95	0.50	92.65	0.00	86.79	0.00	87.42	0.00			93.18	0.00	96.12	0.00	89.53	3.02	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2908597289
91.41	0.46	92.65	0.00	87.08	0.29	87.42	0.00			93.21	0.03	96.12	0.00	91.98	2.44	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1615572867
91.83	0.43	92.66	0.01	89.21	2.13	87.42	0.00			93.21	0.00	96.12	0.00	92.39	0.41	/workspace/coverage/cover_reg_top/6.chip_tl_errors.2087205715
92.20	0.37	92.66	0.00	89.32	0.11	87.44	0.03			93.22	0.01	96.12	0.00	94.44	2.06	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.57142804
92.54	0.34	92.72	0.06	89.37	0.05	89.33	1.89			93.25	0.03	96.12	0.00	94.44	0.00	/workspace/coverage/default/1.rom_e2e_smoke.2091287318
92.79	0.25	92.80	0.08	90.09	0.72	89.35	0.02			93.91	0.66	96.12	0.00	94.44	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.373361550
93.03	0.24	93.64	0.83	90.27	0.18	89.69	0.34			94.00	0.09	96.12	0.00	94.44	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.81185639
93.24	0.21	93.64	0.00	90.36	0.09	89.69	0.00			94.02	0.02	96.12	0.00	95.59	1.15	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.521397080
93.43	0.19	93.64	0.01	90.38	0.02	90.64	0.95			94.02	0.00	96.30	0.18	95.59	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3713373222
93.61	0.18	93.64	0.00	90.38	0.00	91.72	1.08			94.02	0.00	96.30	0.00	95.59	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.836517468
93.78	0.17	93.64	0.00	90.38	0.00	91.72	0.00			94.02	0.00	96.30	0.00	96.59	1.00	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.170789422
93.94	0.16	93.92	0.28	90.64	0.26	91.81	0.09			94.34	0.32	96.30	0.00	96.62	0.02	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.604832056
94.07	0.13	93.92	0.00	90.67	0.03	91.81	0.00			94.34	0.00	96.30	0.00	97.38	0.76	/workspace/coverage/cover_reg_top/76.xbar_random_large_delays.989772417
94.19	0.12	94.10	0.17	90.93	0.26	92.10	0.28			94.34	0.00	96.30	0.00	97.38	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3669056822
94.31	0.12	94.28	0.19	91.31	0.38	92.11	0.01			94.40	0.07	96.30	0.00	97.44	0.06	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3922030334
94.41	0.10	94.49	0.21	91.45	0.13	92.25	0.14			94.53	0.12	96.30	0.00	97.44	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2641670186
94.51	0.10	94.49	0.00	92.01	0.57	92.25	0.00			94.53	0.00	96.30	0.00	97.45	0.01	/workspace/coverage/cover_reg_top/19.chip_tl_errors.560942272
94.59	0.09	94.49	0.00	92.25	0.23	92.26	0.01			94.79	0.26	96.30	0.00	97.45	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.879916654
94.68	0.08	94.49	0.00	92.25	0.00	92.76	0.50			94.79	0.00	96.30	0.00	97.45	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.4180660241
94.76	0.08	94.51	0.02	92.28	0.03	92.78	0.02			94.79	0.00	96.30	0.00	97.87	0.42	/workspace/coverage/default/0.chip_sw_alert_test.1794307188
94.84	0.08	94.51	0.01	92.28	0.00	93.27	0.48			94.79	0.00	96.30	0.00	97.87	0.00	/workspace/coverage/default/94.chip_sw_all_escalation_resets.27866490
94.90	0.06	94.51	0.00	92.28	0.00	93.63	0.36			94.79	0.00	96.30	0.00	97.87	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3909773518
94.95	0.06	94.56	0.05	92.31	0.03	93.66	0.03			94.82	0.02	96.49	0.18	97.89	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3684223628
95.00	0.05	94.58	0.01	92.36	0.05	93.67	0.01			94.85	0.03	96.67	0.18	97.90	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1180762114
95.05	0.05	94.58	0.00	92.37	0.01	93.67	0.00			94.85	0.00	96.67	0.00	98.18	0.28	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1984783244
95.10	0.05	94.64	0.06	92.51	0.14	93.67	0.00			94.93	0.08	96.67	0.00	98.18	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1755877612
95.15	0.05	94.64	0.00	92.51	0.00	93.95	0.28			94.93	0.00	96.67	0.00	98.18	0.00	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2923908448
95.19	0.04	94.67	0.04	92.63	0.12	93.96	0.01			95.01	0.07	96.67	0.00	98.19	0.01	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3519406592
95.23	0.04	94.68	0.01	92.65	0.01	93.97	0.01			95.03	0.02	96.86	0.18	98.20	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.181303096
95.27	0.04	94.73	0.05	92.71	0.06	94.07	0.10			95.06	0.02	96.86	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1092628758
95.31	0.04	94.73	0.00	92.71	0.00	94.11	0.04			95.06	0.00	97.04	0.18	98.20	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1219329019
95.35	0.04	94.74	0.01	92.72	0.01	94.11	0.01			95.06	0.01	97.23	0.18	98.21	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.260493436
95.38	0.04	94.74	0.01	92.73	0.01	94.12	0.01			95.07	0.01	97.41	0.18	98.23	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2295703267
95.42	0.04	94.74	0.00	92.95	0.22	94.12	0.00			95.07	0.00	97.41	0.00	98.23	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.746783248
95.46	0.04	94.74	0.00	92.95	0.00	94.34	0.21			95.07	0.00	97.41	0.00	98.23	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1402377664
95.49	0.03	94.74	0.00	93.03	0.08	94.34	0.00			95.09	0.02	97.41	0.00	98.32	0.09	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.138680205
95.52	0.03	94.74	0.00	93.11	0.09	94.34	0.00			95.19	0.10	97.41	0.00	98.32	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2914046209
95.55	0.03	94.74	0.00	93.29	0.18	94.34	0.00			95.19	0.00	97.41	0.00	98.32	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1668940397
95.58	0.03	94.82	0.08	93.29	0.00	94.42	0.08			95.20	0.01	97.41	0.00	98.32	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3812618136
95.60	0.02	94.82	0.00	93.29	0.00	94.42	0.00			95.20	0.00	97.41	0.00	98.46	0.14	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.4269688494
95.62	0.02	94.84	0.03	93.31	0.02	94.50	0.08			95.21	0.02	97.41	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.460513492
95.65	0.02	94.88	0.04	93.33	0.01	94.55	0.05			95.23	0.02	97.41	0.00	98.47	0.01	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3972187274
95.67	0.02	94.91	0.03	93.38	0.06	94.57	0.02			95.25	0.02	97.41	0.00	98.47	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1640312633
95.69	0.02	94.93	0.02	93.42	0.03	94.64	0.06			95.27	0.02	97.41	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.112915923
95.71	0.02	94.93	0.00	93.53	0.11	94.64	0.00			95.27	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.291967285
95.73	0.02	94.93	0.00	93.64	0.11	94.64	0.00			95.27	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2701309509
95.75	0.02	94.93	0.00	93.64	0.00	94.74	0.11			95.27	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.320684966
95.76	0.02	94.93	0.00	93.64	0.01	94.74	0.00			95.27	0.00	97.41	0.00	98.57	0.09	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2613398733
95.78	0.01	94.93	0.00	93.64	0.00	94.83	0.09			95.27	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.427114939
95.79	0.01	94.97	0.03	93.68	0.04	94.85	0.02			95.27	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1886329681
95.81	0.01	94.97	0.00	93.73	0.05	94.85	0.00			95.29	0.02	97.41	0.00	98.59	0.02	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2288110464
95.82	0.01	94.97	0.00	93.73	0.00	94.93	0.08			95.29	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3313677036
95.83	0.01	94.97	0.01	93.76	0.03	94.98	0.05			95.29	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4234445307
95.85	0.01	95.01	0.04	93.78	0.03	94.99	0.01			95.29	0.01	97.41	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3378156886
95.86	0.01	95.01	0.00	93.78	0.00	95.02	0.03			95.29	0.00	97.41	0.00	98.64	0.05	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2208090332
95.87	0.01	95.01	0.00	93.82	0.04	95.02	0.00			95.31	0.02	97.41	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1567643018
95.88	0.01	95.03	0.03	93.83	0.01	95.04	0.02			95.33	0.02	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1552197161
95.89	0.01	95.03	0.01	93.86	0.03	95.06	0.03			95.33	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2978996501
95.90	0.01	95.04	0.01	93.92	0.05	95.06	0.01			95.33	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3758121225
95.91	0.01	95.04	0.00	93.94	0.02	95.06	0.00			95.33	0.00	97.41	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3042016877
95.92	0.01	95.06	0.03	93.95	0.01	95.07	0.01			95.34	0.02	97.41	0.00	98.68	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3071028528
95.93	0.01	95.06	0.00	93.95	0.00	95.11	0.05			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2397384845
95.94	0.01	95.06	0.00	93.95	0.00	95.16	0.05			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.743124415
95.94	0.01	95.06	0.00	93.99	0.05	95.16	0.00			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/cover_reg_top/26.chip_tl_errors.12541598
95.95	0.01	95.06	0.00	94.04	0.05	95.16	0.00			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2548627288
95.96	0.01	95.06	0.00	94.04	0.00	95.21	0.04			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.746988195
95.97	0.01	95.06	0.00	94.08	0.04	95.21	0.00			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1932495556
95.97	0.01	95.06	0.00	94.09	0.01	95.24	0.04			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2885467198
95.98	0.01	95.06	0.00	94.09	0.00	95.29	0.04			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2537985992
95.99	0.01	95.06	0.00	94.09	0.00	95.33	0.04			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.158907809
95.99	0.01	95.06	0.00	94.09	0.01	95.36	0.03			95.34	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3516878638
96.00	0.01	95.06	0.00	94.09	0.00	95.36	0.00			95.34	0.00	97.41	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.298270124
96.00	0.01	95.06	0.00	94.11	0.02	95.36	0.00			95.34	0.00	97.41	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2562182508
96.01	0.01	95.06	0.00	94.14	0.03	95.36	0.00			95.34	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.579222092
96.01	0.01	95.06	0.00	94.17	0.03	95.36	0.00			95.34	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2684608333
96.02	0.01	95.06	0.00	94.17	0.00	95.39	0.03			95.34	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1280221708
96.02	0.01	95.06	0.00	94.18	0.01	95.39	0.00			95.34	0.00	97.41	0.00	98.74	0.01	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1669149047
96.03	0.01	95.06	0.00	94.21	0.03	95.39	0.00			95.34	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4192788544
96.03	0.01	95.06	0.00	94.23	0.03	95.39	0.00			95.34	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1534659303
96.03	0.01	95.08	0.01	94.24	0.01	95.39	0.01			95.34	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2195620628
96.04	0.01	95.08	0.00	94.24	0.00	95.39	0.00			95.34	0.00	97.41	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1448436999
96.04	0.01	95.08	0.01	94.25	0.01	95.39	0.01			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2266852597
96.05	0.01	95.08	0.00	94.25	0.00	95.41	0.02			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.482994952
96.05	0.01	95.08	0.00	94.27	0.02	95.42	0.01			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_gpio.501495346
96.05	0.01	95.08	0.00	94.29	0.01	95.42	0.01			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1181603481
96.05	0.01	95.09	0.01	94.29	0.00	95.43	0.01			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.2050980859
96.06	0.01	95.09	0.00	94.29	0.00	95.45	0.02			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_flash_init.765792241
96.06	0.01	95.09	0.00	94.30	0.02	95.45	0.00			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1835815929
96.06	0.01	95.09	0.00	94.30	0.00	95.47	0.02			95.34	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3800547140
96.07	0.01	95.09	0.00	94.30	0.00	95.47	0.01			95.34	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.43533404
96.07	0.01	95.09	0.00	94.31	0.01	95.47	0.00			95.34	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1405743471
96.07	0.01	95.09	0.00	94.31	0.01	95.47	0.00			95.34	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.982842248
96.07	0.01	95.09	0.00	94.31	0.01	95.47	0.00			95.34	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.2781901597
96.08	0.01	95.09	0.00	94.33	0.01	95.47	0.00			95.34	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/94.xbar_stress_all.783154994
96.08	0.01	95.09	0.00	94.34	0.01	95.47	0.00			95.34	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.581050454
96.08	0.01	95.09	0.00	94.34	0.00	95.47	0.01			95.34	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1534647
96.08	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.822043825
96.09	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029252956
96.09	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1871011621
96.09	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2710093928
96.09	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.230214434
96.09	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2273158929
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219529725
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3860472900
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308158374
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072470533
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3323247230
96.10	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2961009448
96.11	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.955557949
96.11	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1660388267
96.11	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1815308463
96.11	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1631521208
96.11	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.153409270
96.12	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2435304319
96.12	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012231088
96.12	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2532004798
96.12	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1870648706
96.12	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3436349636
96.13	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2009420883
96.13	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.899251771
96.13	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1579475202
96.13	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.617317786
96.13	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2185180744
96.14	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068988628
96.14	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699622808
96.14	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2608014223
96.14	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2369062238
96.14	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3448827522
96.15	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1232428971
96.15	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765127090
96.15	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.105563442
96.15	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3987803260
96.15	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.4073147737
96.16	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.313376523
96.16	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1305572112
96.16	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2015356088
96.16	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818272017
96.16	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630443776
96.17	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2471476060
96.17	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.287238359
96.17	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1685230742
96.17	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2865004825
96.17	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3620493009
96.18	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3939465401
96.18	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1831546259
96.18	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3653071790
96.18	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942119282
96.18	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.766797344
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.1631195288
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4212677847
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074080361
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854205411
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1135032801
96.19	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/74.chip_sw_all_escalation_resets.948849471
96.20	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2652330874
96.20	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2834850607
96.20	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.371076407
96.20	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.4223801561
96.20	0.01	95.09	0.00	94.34	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1049632137
96.21	0.01	95.09	0.00	94.35	0.01	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1765197265
96.21	0.01	95.09	0.00	94.37	0.01	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.405159976
96.21	0.01	95.09	0.00	94.38	0.01	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1316696143
96.21	0.01	95.10	0.01	94.38	0.01	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.983938408
96.21	0.01	95.11	0.01	94.38	0.00	95.47	0.00			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1875505066
96.22	0.01	95.11	0.01	94.38	0.00	95.48	0.01			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1157403943
96.22	0.01	95.11	0.00	94.38	0.00	95.49	0.01			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.377770775
96.22	0.01	95.11	0.00	94.38	0.00	95.50	0.01			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.265417997
96.22	0.01	95.11	0.00	94.38	0.00	95.51	0.01			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3486971811
96.22	0.01	95.11	0.00	94.38	0.00	95.52	0.01			95.34	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.838003225
96.22	0.01	95.11	0.00	94.38	0.00	95.52	0.00			95.35	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1961008679
96.22	0.01	95.11	0.00	94.38	0.00	95.52	0.00			95.36	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.2374826946
96.23	0.01	95.11	0.00	94.39	0.01	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.3965626200
96.23	0.01	95.11	0.00	94.39	0.01	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.468388614
96.23	0.01	95.11	0.00	94.40	0.01	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1957959954
96.23	0.01	95.11	0.00	94.41	0.01	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.2730157705
96.23	0.01	95.12	0.01	94.41	0.00	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1779170681
96.23	0.01	95.12	0.01	94.41	0.00	95.52	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.494606952
96.23	0.01	95.12	0.00	94.41	0.00	95.53	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3203503235
96.23	0.01	95.12	0.00	94.41	0.00	95.53	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2419749820
96.23	0.01	95.12	0.00	94.41	0.00	95.54	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.3008511651
96.24	0.01	95.12	0.00	94.41	0.00	95.54	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3915769055
96.24	0.01	95.12	0.00	94.41	0.00	95.55	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2515541029
96.24	0.01	95.12	0.00	94.41	0.00	95.55	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1191064751
96.24	0.01	95.12	0.00	94.41	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_rw.4031881752
96.24	0.01	95.12	0.00	94.42	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1887623251
96.24	0.01	95.12	0.00	94.42	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.xbar_error_random.1540146508
96.24	0.01	95.12	0.00	94.42	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1865838638
96.24	0.01	95.12	0.00	94.43	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3669025099
96.24	0.01	95.12	0.00	94.43	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.4003497200
96.24	0.01	95.12	0.00	94.43	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/44.xbar_error_random.1881311083
96.24	0.01	95.12	0.00	94.44	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3264850219
96.24	0.01	95.12	0.00	94.44	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.4173154062
96.24	0.01	95.12	0.00	94.44	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.33068016
96.24	0.01	95.12	0.00	94.45	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1790338713
96.24	0.01	95.12	0.00	94.45	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.42259705
96.24	0.01	95.12	0.00	94.46	0.01	95.55	0.00			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.827395053
96.25	0.01	95.12	0.00	94.46	0.00	95.55	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2240718268
96.25	0.01	95.12	0.00	94.46	0.00	95.55	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.469759615
96.25	0.01	95.12	0.00	94.46	0.00	95.56	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.350484829
96.25	0.01	95.12	0.00	94.46	0.00	95.56	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3332943991
96.25	0.01	95.12	0.00	94.46	0.00	95.56	0.01			95.36	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1878350921

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3579521299
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1341951687
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1589219665
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.299880437
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4188735173
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3890776903
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.212246450
/workspace/coverage/cover_reg_top/0.xbar_error_random.2310645406
/workspace/coverage/cover_reg_top/0.xbar_random.2316524238
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3107871004
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1307822635
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1846873556
/workspace/coverage/cover_reg_top/0.xbar_same_source.3211317467
/workspace/coverage/cover_reg_top/0.xbar_smoke.128907368
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2590497810
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1967987783
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.73138044
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2468862570
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.28409238
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3300666158
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3519569536
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3819346286
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.537651368
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3738167612
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2291700995
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.968225407
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.602796179
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1398164744
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1313802421
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1609220833
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2586790884
/workspace/coverage/cover_reg_top/1.xbar_error_random.3841616158
/workspace/coverage/cover_reg_top/1.xbar_random.374267016
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3394014496
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.283276732
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.418179435
/workspace/coverage/cover_reg_top/1.xbar_same_source.225535685
/workspace/coverage/cover_reg_top/1.xbar_smoke.3923837931
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1688987879
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.253455352
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.846162701
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1000127503
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4091728061
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.622527454
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2503233827
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3904045869
/workspace/coverage/cover_reg_top/10.chip_csr_rw.904551832
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1030856132
/workspace/coverage/cover_reg_top/10.chip_tl_errors.236442770
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2967783158
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4230520694
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2936374899
/workspace/coverage/cover_reg_top/10.xbar_error_random.3288078869
/workspace/coverage/cover_reg_top/10.xbar_random.4197074606
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1058013600
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1251676449
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3171313984
/workspace/coverage/cover_reg_top/10.xbar_same_source.2755922751
/workspace/coverage/cover_reg_top/10.xbar_smoke.874179987
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1603965703
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2926597415
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2256641332
/workspace/coverage/cover_reg_top/10.xbar_stress_all.965656108
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2775284348
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.902642549
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1237225078
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.877388904
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.187552752
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2516572636
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2127570095
/workspace/coverage/cover_reg_top/11.xbar_error_random.2131237557
/workspace/coverage/cover_reg_top/11.xbar_random.4045366799
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1900335842
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.403772016
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2749278890
/workspace/coverage/cover_reg_top/11.xbar_same_source.1814065019
/workspace/coverage/cover_reg_top/11.xbar_smoke.296149539
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2470726581
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.918805063
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2850228314
/workspace/coverage/cover_reg_top/11.xbar_stress_all.317922298
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.194128443
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3848529390
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3079527594
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3993660450
/workspace/coverage/cover_reg_top/12.chip_csr_rw.983634223
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2543496493
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.300859467
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3012058497
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1478238449
/workspace/coverage/cover_reg_top/12.xbar_error_random.452511384
/workspace/coverage/cover_reg_top/12.xbar_random.3104000788
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3190588290
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3020696404
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1616207243
/workspace/coverage/cover_reg_top/12.xbar_same_source.2370552709
/workspace/coverage/cover_reg_top/12.xbar_smoke.4232779541
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.289530223
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1030729920
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3962083824
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1267341815
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4142532724
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1973387839
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3670397134
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1035266690
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3541918834
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3074616207
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3828237063
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3686973167
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1586599093
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2939779304
/workspace/coverage/cover_reg_top/13.xbar_error_random.1485472927
/workspace/coverage/cover_reg_top/13.xbar_random.3125443387
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.143078134
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3632669056
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.939344029
/workspace/coverage/cover_reg_top/13.xbar_same_source.3502549656
/workspace/coverage/cover_reg_top/13.xbar_smoke.337376955
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2048805943
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2781620633
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3288693922
/workspace/coverage/cover_reg_top/13.xbar_stress_all.966990047
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.363471733
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2529868863
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2544957558
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3211409947
/workspace/coverage/cover_reg_top/14.chip_csr_rw.310033362
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.640571579
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1140395906
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3786986374
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.564848082
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1155817146
/workspace/coverage/cover_reg_top/14.xbar_error_random.3027901073
/workspace/coverage/cover_reg_top/14.xbar_random.1756089021
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1669901279
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/workspace/coverage/default/70.chip_sw_all_escalation_resets.4166468874
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309257783
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3323642717
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082223701
/workspace/coverage/default/72.chip_sw_all_escalation_resets.453394061
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1880941209
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.687518033
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403211371
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3257327450
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1867963522
/workspace/coverage/default/76.chip_sw_all_escalation_resets.246991169
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303520074
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2417771581
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2847223396
/workspace/coverage/default/78.chip_sw_all_escalation_resets.676170971
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3840208454
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1752736133
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.925500034
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3709734216
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3402529825
/workspace/coverage/default/80.chip_sw_all_escalation_resets.307208489
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.500655866
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1757351820
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3957899171
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2948511953
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931389771
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1740013157
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261687112
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1318590892
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2895492021
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2320186188
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3977862668
/workspace/coverage/default/86.chip_sw_all_escalation_resets.34124937
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3718974016
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237651613
/workspace/coverage/default/88.chip_sw_all_escalation_resets.143882213
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3469485388
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.48120866
/workspace/coverage/default/9.chip_sw_all_escalation_resets.293536726
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.183374238
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3655316813
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3755887075
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3357601186
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2162729142
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2163646234
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1541060273
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3205682001
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3971863040
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.226602794
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1079079410
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3180917943
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1302477621
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.517959812
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3258799360
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4004947655
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4093550095

---

Total test records in report: 2771

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1463775167			May 07 04:26:23 PM PDT 24	May 07 04:46:17 PM PDT 24	9983189816 ps
T2	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2066683650			May 07 04:29:52 PM PDT 24	May 07 07:17:00 PM PDT 24	57280511602 ps
T3	/workspace/coverage/default/58.chip_sw_all_escalation_resets.2862159297			May 07 04:54:29 PM PDT 24	May 07 05:03:36 PM PDT 24	6079854928 ps
T55	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2009420883			May 07 04:53:53 PM PDT 24	May 07 05:00:31 PM PDT 24	3870986760 ps
T59	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818272017			May 07 04:53:15 PM PDT 24	May 07 05:00:30 PM PDT 24	3803244192 ps
T81	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1640312633			May 07 04:47:08 PM PDT 24	May 07 04:56:33 PM PDT 24	4313392556 ps
T82	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.550109072			May 07 04:43:28 PM PDT 24	May 07 04:56:23 PM PDT 24	4478974382 ps
T83	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416348030			May 07 04:57:42 PM PDT 24	May 07 05:02:54 PM PDT 24	3583329726 ps
T84	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2467167987			May 07 04:42:17 PM PDT 24	May 07 04:57:02 PM PDT 24	6173074432 ps
T85	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3713373222			May 07 04:48:08 PM PDT 24	May 07 04:58:25 PM PDT 24	5033564894 ps
T265	/workspace/coverage/default/0.chip_sw_example_manufacturer.3757582406			May 07 04:23:01 PM PDT 24	May 07 04:25:33 PM PDT 24	2800594900 ps
T266	/workspace/coverage/default/0.chip_sw_aes_idle.706561932			May 07 04:26:51 PM PDT 24	May 07 04:31:57 PM PDT 24	3122913440 ps
T12	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1092628758			May 07 04:30:22 PM PDT 24	May 07 04:40:43 PM PDT 24	4230148320 ps
T169	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4029882709			May 07 04:51:16 PM PDT 24	May 07 05:01:47 PM PDT 24	4367498910 ps
T77	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3813968483			May 07 04:42:23 PM PDT 24	May 07 05:12:45 PM PDT 24	13205841464 ps
T6	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1196465456			May 07 04:29:20 PM PDT 24	May 07 04:33:42 PM PDT 24	3403412272 ps
T32	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1886329681			May 07 04:38:58 PM PDT 24	May 07 04:42:21 PM PDT 24	2930625696 ps
T41	/workspace/coverage/default/1.rom_e2e_smoke.2091287318			May 07 04:43:08 PM PDT 24	May 07 05:45:03 PM PDT 24	17232370792 ps
T60	/workspace/coverage/default/88.chip_sw_all_escalation_resets.143882213			May 07 04:55:50 PM PDT 24	May 07 05:05:15 PM PDT 24	5506009016 ps
T392	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4200745493			May 07 04:47:04 PM PDT 24	May 07 04:51:07 PM PDT 24	2523065192 ps
T111	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4234445307			May 07 04:22:50 PM PDT 24	May 07 05:11:31 PM PDT 24	13123363250 ps
T681	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443816638			May 07 04:55:12 PM PDT 24	May 07 05:00:18 PM PDT 24	4021910104 ps
T118	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2592769935			May 07 04:34:48 PM PDT 24	May 07 05:00:41 PM PDT 24	7361443940 ps
T15	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2898691099			May 07 04:45:42 PM PDT 24	May 07 05:07:14 PM PDT 24	16883184922 ps
T9	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.81185639			May 07 04:40:25 PM PDT 24	May 07 04:51:16 PM PDT 24	4979124942 ps
T99	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2338287376			May 07 04:34:14 PM PDT 24	May 07 04:54:12 PM PDT 24	7245901852 ps
T100	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3001406014			May 07 04:30:33 PM PDT 24	May 07 04:39:37 PM PDT 24	4674836816 ps
T45	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3875975783			May 07 04:34:42 PM PDT 24	May 07 04:45:26 PM PDT 24	4129186402 ps
T101	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.738347578			May 07 04:49:16 PM PDT 24	May 07 04:57:23 PM PDT 24	3511196036 ps
T102	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.25206793			May 07 04:38:23 PM PDT 24	May 07 04:43:22 PM PDT 24	2988019961 ps
T46	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.482994952			May 07 04:36:34 PM PDT 24	May 07 04:45:12 PM PDT 24	4218161388 ps
T103	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.456535659			May 07 04:37:40 PM PDT 24	May 07 04:57:38 PM PDT 24	5247834584 ps
T67	/workspace/coverage/default/2.chip_tap_straps_dev.2291410963			May 07 04:47:48 PM PDT 24	May 07 05:07:20 PM PDT 24	14149261518 ps
T114	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2925982724			May 07 04:48:43 PM PDT 24	May 07 04:55:59 PM PDT 24	6539964268 ps
T4	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2397384845			May 07 04:30:26 PM PDT 24	May 07 04:39:49 PM PDT 24	4656882248 ps
T128	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1552197161			May 07 04:35:29 PM PDT 24	May 07 04:45:25 PM PDT 24	4814535776 ps
T68	/workspace/coverage/default/4.chip_tap_straps_prod.1202718137			May 07 04:49:34 PM PDT 24	May 07 05:07:22 PM PDT 24	10299475349 ps
T61	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1919964328			May 07 04:42:45 PM PDT 24	May 07 05:03:51 PM PDT 24	12604817012 ps
T216	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3335881586			May 07 04:46:40 PM PDT 24	May 07 04:56:09 PM PDT 24	4287855000 ps
T229	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4273574072			May 07 04:47:27 PM PDT 24	May 07 04:51:21 PM PDT 24	2542861712 ps
T344	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3323247230			May 07 04:51:42 PM PDT 24	May 07 04:57:35 PM PDT 24	3079187800 ps
T185	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2722264127			May 07 04:29:20 PM PDT 24	May 07 04:44:01 PM PDT 24	4741241550 ps
T345	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.86461103			May 07 04:43:08 PM PDT 24	May 07 04:47:24 PM PDT 24	2609567960 ps
T346	/workspace/coverage/default/2.chip_sw_example_manufacturer.2433159453			May 07 04:39:03 PM PDT 24	May 07 04:44:02 PM PDT 24	2811189240 ps
T13	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1188918377			May 07 04:30:23 PM PDT 24	May 07 04:34:30 PM PDT 24	3131361408 ps
T384	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2923704248			May 07 04:25:28 PM PDT 24	May 07 04:45:50 PM PDT 24	7354431306 ps
T115	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1835815929			May 07 04:28:26 PM PDT 24	May 07 04:50:47 PM PDT 24	5483516208 ps
T230	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3488853726			May 07 04:44:01 PM PDT 24	May 07 05:00:33 PM PDT 24	4388314186 ps
T373	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072470533			May 07 04:50:50 PM PDT 24	May 07 04:57:34 PM PDT 24	4422022216 ps
T47	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4193182835			May 07 04:30:36 PM PDT 24	May 07 04:34:58 PM PDT 24	3335063684 ps
T65	/workspace/coverage/default/1.chip_tap_straps_prod.3053267803			May 07 04:36:10 PM PDT 24	May 07 04:38:45 PM PDT 24	3274448629 ps
T310	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2438927402			May 07 04:41:41 PM PDT 24	May 07 04:47:34 PM PDT 24	2903586560 ps
T5	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3516878638			May 07 04:29:20 PM PDT 24	May 07 04:43:07 PM PDT 24	7841682089 ps
T280	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1261867179			May 07 04:35:42 PM PDT 24	May 07 04:42:36 PM PDT 24	5134702680 ps
T231	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3972187274			May 07 04:31:16 PM PDT 24	May 07 05:04:33 PM PDT 24	22656784737 ps
T281	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3980459760			May 07 04:55:04 PM PDT 24	May 07 05:00:41 PM PDT 24	4022571008 ps
T147	/workspace/coverage/default/2.chip_plic_all_irqs_10.1889731346			May 07 04:44:14 PM PDT 24	May 07 04:52:24 PM PDT 24	3954557880 ps
T282	/workspace/coverage/default/0.chip_sw_aes_entropy.3661000069			May 07 04:24:10 PM PDT 24	May 07 04:27:54 PM PDT 24	2849955184 ps
T193	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1382218847			May 07 04:53:06 PM PDT 24	May 07 05:01:34 PM PDT 24	5211781200 ps
T160	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1130378384			May 07 04:30:10 PM PDT 24	May 07 04:41:09 PM PDT 24	4862458312 ps
T78	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2208504223			May 07 04:24:06 PM PDT 24	May 07 04:27:17 PM PDT 24	2908562822 ps
T116	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2923908448			May 07 04:44:33 PM PDT 24	May 07 05:06:34 PM PDT 24	5879476044 ps
T44	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1365924519			May 07 04:24:10 PM PDT 24	May 07 04:59:09 PM PDT 24	33960757901 ps
T213	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3684223628			May 07 04:52:01 PM PDT 24	May 07 05:01:40 PM PDT 24	5635757870 ps
T240	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1106911237			May 07 04:25:51 PM PDT 24	May 07 04:37:18 PM PDT 24	7179700894 ps
T241	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3260038856			May 07 04:51:54 PM PDT 24	May 07 04:57:53 PM PDT 24	3592397600 ps
T242	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1316696143			May 07 04:24:41 PM PDT 24	May 07 04:35:59 PM PDT 24	4101676518 ps
T243	/workspace/coverage/default/73.chip_sw_all_escalation_resets.1880941209			May 07 04:56:30 PM PDT 24	May 07 05:08:31 PM PDT 24	6145346552 ps
T161	/workspace/coverage/default/2.chip_sival_flash_info_access.310635510			May 07 04:39:50 PM PDT 24	May 07 04:45:14 PM PDT 24	3153065400 ps
T244	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1266709557			May 07 04:33:15 PM PDT 24	May 07 04:42:10 PM PDT 24	5161731071 ps
T245	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1867963522			May 07 04:54:30 PM PDT 24	May 07 05:00:05 PM PDT 24	3619561934 ps
T110	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.320684966			May 07 04:24:31 PM PDT 24	May 07 04:26:40 PM PDT 24	2884549080 ps
T246	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765127090			May 07 04:51:14 PM PDT 24	May 07 04:59:09 PM PDT 24	3998510528 ps
T142	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2014896145			May 07 04:26:20 PM PDT 24	May 07 05:23:37 PM PDT 24	17652181554 ps
T186	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.983938408			May 07 04:25:30 PM PDT 24	May 07 04:41:21 PM PDT 24	4882322216 ps
T163	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.836517468			May 07 04:23:23 PM PDT 24	May 07 05:52:47 PM PDT 24	43619403794 ps
T10	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.4264138371			May 07 04:27:14 PM PDT 24	May 07 04:31:13 PM PDT 24	2552850160 ps
T335	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2703275623			May 07 04:24:49 PM PDT 24	May 07 04:50:48 PM PDT 24	9107114555 ps
T887	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1790338713			May 07 04:28:14 PM PDT 24	May 07 04:36:53 PM PDT 24	5089402200 ps
T14	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3402529825			May 07 04:48:44 PM PDT 24	May 07 04:54:53 PM PDT 24	4161380520 ps
T888	/workspace/coverage/default/1.chip_sw_uart_smoketest.3609534559			May 07 04:38:28 PM PDT 24	May 07 04:43:12 PM PDT 24	2707289568 ps
T220	/workspace/coverage/default/25.chip_sw_all_escalation_resets.4215354589			May 07 04:51:12 PM PDT 24	May 07 05:00:29 PM PDT 24	4897240990 ps
T889	/workspace/coverage/default/1.chip_sw_example_rom.1260167890			May 07 04:28:34 PM PDT 24	May 07 04:30:30 PM PDT 24	2722825874 ps
T371	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1302992279			May 07 04:32:13 PM PDT 24	May 07 04:38:54 PM PDT 24	4987987848 ps
T166	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1335904721			May 07 04:47:26 PM PDT 24	May 07 05:01:59 PM PDT 24	9512025783 ps
T178	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1663918175			May 07 04:40:47 PM PDT 24	May 07 04:50:00 PM PDT 24	7741644965 ps
T890	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2729011513			May 07 04:44:30 PM PDT 24	May 07 04:49:38 PM PDT 24	3783269194 ps
T137	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3353483255			May 07 04:24:57 PM PDT 24	May 07 07:32:08 PM PDT 24	64804273229 ps
T891	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2473042023			May 07 04:43:00 PM PDT 24	May 07 04:53:39 PM PDT 24	4846184596 ps
T66	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2307001046			May 07 04:48:10 PM PDT 24	May 07 05:02:35 PM PDT 24	9196106465 ps
T704	/workspace/coverage/default/1.chip_tap_straps_dev.3337501774			May 07 04:33:43 PM PDT 24	May 07 04:37:51 PM PDT 24	3612887177 ps
T892	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.39196730			May 07 04:27:54 PM PDT 24	May 07 04:48:16 PM PDT 24	7742165710 ps
T692	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1534647			May 07 04:51:11 PM PDT 24	May 07 05:02:00 PM PDT 24	6192720956 ps
T680	/workspace/coverage/default/78.chip_sw_all_escalation_resets.676170971			May 07 04:56:26 PM PDT 24	May 07 05:07:50 PM PDT 24	5978523318 ps
T893	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.122524260			May 07 04:27:26 PM PDT 24	May 07 04:33:20 PM PDT 24	3638806326 ps
T189	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3528330917			May 07 04:24:25 PM PDT 24	May 07 08:05:57 PM PDT 24	76752405626 ps
T320	/workspace/coverage/default/44.chip_sw_all_escalation_resets.181303096			May 07 04:56:46 PM PDT 24	May 07 05:07:31 PM PDT 24	5277296760 ps
T357	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2356439802			May 07 04:45:24 PM PDT 24	May 07 05:00:44 PM PDT 24	7704275541 ps
T358	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.257761457			May 07 04:34:29 PM PDT 24	May 07 04:42:41 PM PDT 24	5095072382 ps
T359	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1831546259			May 07 04:53:35 PM PDT 24	May 07 05:03:42 PM PDT 24	5351087420 ps
T360	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1759664381			May 07 04:46:33 PM PDT 24	May 07 04:50:29 PM PDT 24	3044396940 ps
T361	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2435304319			May 07 04:39:07 PM PDT 24	May 07 04:49:54 PM PDT 24	5218366768 ps
T297	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2039482503			May 07 04:50:15 PM PDT 24	May 07 05:12:06 PM PDT 24	8463627140 ps
T362	/workspace/coverage/default/74.chip_sw_all_escalation_resets.948849471			May 07 04:54:32 PM PDT 24	May 07 05:03:20 PM PDT 24	5712256724 ps
T117	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1861005105			May 07 04:29:43 PM PDT 24	May 07 05:09:43 PM PDT 24	10024179762 ps
T16	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.880077889			May 07 04:35:15 PM PDT 24	May 07 04:42:47 PM PDT 24	7042414872 ps
T894	/workspace/coverage/default/4.chip_tap_straps_dev.3479542061			May 07 04:49:36 PM PDT 24	May 07 04:51:48 PM PDT 24	2912502395 ps
T191	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2938093961			May 07 04:43:31 PM PDT 24	May 07 05:05:10 PM PDT 24	7047963976 ps
T179	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4242144333			May 07 04:50:24 PM PDT 24	May 07 05:10:35 PM PDT 24	8278820840 ps
T112	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1580657265			May 07 04:45:57 PM PDT 24	May 07 04:55:06 PM PDT 24	4484064680 ps
T104	/workspace/coverage/default/1.chip_sw_power_sleep_load.2050980859			May 07 04:38:18 PM PDT 24	May 07 04:44:19 PM PDT 24	4329047506 ps
T143	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1762154333			May 07 04:27:24 PM PDT 24	May 07 04:47:10 PM PDT 24	7233460728 ps
T212	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1791063856			May 07 04:31:16 PM PDT 24	May 07 04:41:09 PM PDT 24	5321544300 ps
T194	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3634389374			May 07 04:25:59 PM PDT 24	May 07 04:55:33 PM PDT 24	8164941912 ps
T170	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1968836966			May 07 04:34:58 PM PDT 24	May 07 04:47:09 PM PDT 24	3827222976 ps
T895	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2448589192			May 07 04:43:27 PM PDT 24	May 07 05:01:28 PM PDT 24	8454876856 ps
T896	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1379223347			May 07 04:37:57 PM PDT 24	May 07 04:41:27 PM PDT 24	2965359893 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2266852597			May 07 04:23:19 PM PDT 24	May 07 04:31:07 PM PDT 24	3532325904 ps
T742	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219529725			May 07 04:49:50 PM PDT 24	May 07 04:56:38 PM PDT 24	3958720980 ps
T150	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2366435924			May 07 04:42:33 PM PDT 24	May 07 08:01:20 PM PDT 24	255505985564 ps
T171	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1280961439			May 07 04:27:01 PM PDT 24	May 07 04:31:21 PM PDT 24	2643940504 ps
T273	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3614291877			May 07 04:31:00 PM PDT 24	May 07 04:38:28 PM PDT 24	3430993200 ps
T274	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3620527254			May 07 04:34:59 PM PDT 24	May 07 04:52:17 PM PDT 24	10490215260 ps
T275	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.238280938			May 07 04:43:57 PM PDT 24	May 07 04:47:47 PM PDT 24	3060176146 ps
T276	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2173319610			May 07 04:51:47 PM PDT 24	May 07 05:30:04 PM PDT 24	13053904116 ps
T277	/workspace/coverage/default/1.chip_sw_kmac_entropy.516348949			May 07 04:33:55 PM PDT 24	May 07 04:38:18 PM PDT 24	3045145540 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2079150641			May 07 04:24:09 PM PDT 24	May 07 04:33:20 PM PDT 24	3708326446 ps
T190	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3041358613			May 07 04:34:28 PM PDT 24	May 07 05:16:32 PM PDT 24	23917158400 ps
T172	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.751657844			May 07 04:34:59 PM PDT 24	May 07 04:46:01 PM PDT 24	7993076153 ps
T278	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.313376523			May 07 04:53:12 PM PDT 24	May 07 05:00:19 PM PDT 24	4136775176 ps
T175	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.628405760			May 07 04:42:36 PM PDT 24	May 07 04:49:49 PM PDT 24	3977086280 ps
T682	/workspace/coverage/default/71.chip_sw_all_escalation_resets.3323642717			May 07 04:55:02 PM PDT 24	May 07 05:02:41 PM PDT 24	5184240872 ps
T195	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3306879931			May 07 04:36:15 PM PDT 24	May 07 05:04:58 PM PDT 24	9316251000 ps
T897	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2235804218			May 07 04:28:15 PM PDT 24	May 07 04:31:14 PM PDT 24	2376206900 ps
T221	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1180762114			May 07 04:53:58 PM PDT 24	May 07 05:02:39 PM PDT 24	5510921776 ps
T898	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4159166471			May 07 04:28:39 PM PDT 24	May 07 04:35:46 PM PDT 24	3216048778 ps
T899	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1882651758			May 07 04:50:35 PM PDT 24	May 07 04:57:41 PM PDT 24	3749058728 ps
T900	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3677586415			May 07 04:39:06 PM PDT 24	May 07 04:43:54 PM PDT 24	2633880444 ps
T901	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3783827532			May 07 04:24:56 PM PDT 24	May 07 04:38:05 PM PDT 24	10104153310 ps
T902	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3987838168			May 07 04:48:04 PM PDT 24	May 07 04:58:12 PM PDT 24	6591276796 ps
T741	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3107790090			May 07 04:53:56 PM PDT 24	May 07 05:05:29 PM PDT 24	5037462996 ps
T743	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309257783			May 07 04:53:44 PM PDT 24	May 07 04:59:31 PM PDT 24	3649995864 ps
T903	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2695113142			May 07 04:26:14 PM PDT 24	May 07 04:34:09 PM PDT 24	4319719352 ps
T703	/workspace/coverage/default/1.chip_sw_hmac_smoketest.480932295			May 07 04:38:34 PM PDT 24	May 07 04:45:59 PM PDT 24	3390944420 ps
T772	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.7137190			May 07 04:54:31 PM PDT 24	May 07 05:00:07 PM PDT 24	3538987152 ps
T234	/workspace/coverage/default/1.chip_sw_edn_auto_mode.805850438			May 07 04:33:16 PM PDT 24	May 07 04:45:59 PM PDT 24	3728633808 ps
T398	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.526126009			May 07 04:34:15 PM PDT 24	May 07 05:30:45 PM PDT 24	17062797360 ps
T113	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.648924648			May 07 04:35:43 PM PDT 24	May 07 04:46:49 PM PDT 24	4174054120 ps
T904	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3366603252			May 07 04:29:49 PM PDT 24	May 07 04:34:02 PM PDT 24	3103397854 ps
T905	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.450899235			May 07 04:31:57 PM PDT 24	May 07 04:40:27 PM PDT 24	7314192572 ps
T906	/workspace/coverage/default/2.chip_sw_csrng_kat_test.1463392009			May 07 04:46:22 PM PDT 24	May 07 04:51:07 PM PDT 24	2715186280 ps
T330	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2320186188			May 07 04:56:43 PM PDT 24	May 07 05:05:33 PM PDT 24	5570579090 ps
T712	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237651613			May 07 04:55:51 PM PDT 24	May 07 05:03:30 PM PDT 24	3908626960 ps
T184	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2978996501			May 07 04:39:53 PM PDT 24	May 07 08:16:59 PM PDT 24	77384424537 ps
T907	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1797220914			May 07 04:42:45 PM PDT 24	May 07 05:03:24 PM PDT 24	6267185840 ps
T311	/workspace/coverage/default/0.chip_sw_flash_crash_alert.432996674			May 07 04:26:27 PM PDT 24	May 07 04:40:10 PM PDT 24	4793770210 ps
T196	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.930664357			May 07 04:44:12 PM PDT 24	May 07 05:07:20 PM PDT 24	7885278108 ps
T908	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2236684251			May 07 04:28:57 PM PDT 24	May 07 04:35:15 PM PDT 24	6103986815 ps
T909	/workspace/coverage/default/2.chip_sw_aes_entropy.1520493171			May 07 04:43:10 PM PDT 24	May 07 04:49:02 PM PDT 24	2659346424 ps
T391	/workspace/coverage/default/1.chip_sw_kmac_app_rom.747261978			May 07 04:33:52 PM PDT 24	May 07 04:38:31 PM PDT 24	2911636050 ps
T253	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1219329019			May 07 04:48:07 PM PDT 24	May 07 04:59:30 PM PDT 24	5523844290 ps
T164	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1402377664			May 07 04:43:16 PM PDT 24	May 07 05:14:53 PM PDT 24	26495144901 ps
T254	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1049632137			May 07 04:56:33 PM PDT 24	May 07 05:07:03 PM PDT 24	4751679150 ps
T156	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.550398975			May 07 04:32:12 PM PDT 24	May 07 05:02:59 PM PDT 24	27939401325 ps
T255	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1623071803			May 07 04:51:23 PM PDT 24	May 07 04:59:55 PM PDT 24	6258290638 ps
T256	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.500655866			May 07 04:56:31 PM PDT 24	May 07 05:01:56 PM PDT 24	4087484954 ps
T257	/workspace/coverage/default/0.chip_sw_kmac_idle.265417997			May 07 04:26:11 PM PDT 24	May 07 04:30:26 PM PDT 24	2806132856 ps
T258	/workspace/coverage/default/28.chip_sw_all_escalation_resets.899251771			May 07 04:52:32 PM PDT 24	May 07 04:59:50 PM PDT 24	5557200168 ps
T259	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1974530628			May 07 04:27:03 PM PDT 24	May 07 04:33:10 PM PDT 24	4634205800 ps
T260	/workspace/coverage/default/0.chip_sw_csrng_smoketest.368708792			May 07 04:28:50 PM PDT 24	May 07 04:32:23 PM PDT 24	3047399158 ps
T19	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2362910518			May 07 04:23:42 PM PDT 24	May 07 05:18:07 PM PDT 24	20677099838 ps
T396	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.131596672			May 07 04:33:20 PM PDT 24	May 07 04:55:49 PM PDT 24	6149682968 ps
T313	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3008908969			May 07 04:39:04 PM PDT 24	May 07 04:50:45 PM PDT 24	4291570896 ps
T211	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2608014223			May 07 04:53:46 PM PDT 24	May 07 05:00:07 PM PDT 24	3706964926 ps
T35	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1181603481			May 07 04:28:19 PM PDT 24	May 07 04:37:32 PM PDT 24	5069745800 ps
T910	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1197556671			May 07 04:45:51 PM PDT 24	May 07 04:54:32 PM PDT 24	3722172568 ps
T157	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.95883001			May 07 04:30:14 PM PDT 24	May 07 04:32:06 PM PDT 24	2040290511 ps
T162	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2632683423			May 07 04:42:29 PM PDT 24	May 07 05:17:54 PM PDT 24	33531649988 ps
T321	/workspace/coverage/default/63.chip_sw_all_escalation_resets.766797344			May 07 04:54:25 PM PDT 24	May 07 05:05:41 PM PDT 24	5504366200 ps
T180	/workspace/coverage/default/2.chip_sw_power_sleep_load.235638240			May 07 04:45:39 PM PDT 24	May 07 04:54:30 PM PDT 24	9389391284 ps
T74	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2002444409			May 07 04:36:41 PM PDT 24	May 07 04:46:34 PM PDT 24	5355482852 ps
T217	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1957959954			May 07 04:24:49 PM PDT 24	May 07 04:46:40 PM PDT 24	11657605656 ps
T227	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1475445365			May 07 04:34:44 PM PDT 24	May 07 04:38:30 PM PDT 24	2887865472 ps
T312	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3469011696			May 07 04:47:59 PM PDT 24	May 07 05:10:41 PM PDT 24	8928976040 ps
T911	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2510949106			May 07 04:47:17 PM PDT 24	May 07 04:53:01 PM PDT 24	3167263269 ps
T912	/workspace/coverage/default/0.chip_sw_aes_enc.399890897			May 07 04:25:51 PM PDT 24	May 07 04:29:54 PM PDT 24	2584510214 ps
T729	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1970218458			May 07 04:52:27 PM PDT 24	May 07 05:01:04 PM PDT 24	5576998528 ps
T913	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1280221708			May 07 04:24:28 PM PDT 24	May 07 04:34:11 PM PDT 24	3708156242 ps
T347	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3909773518			May 07 04:32:55 PM PDT 24	May 07 04:43:01 PM PDT 24	5456735723 ps
T914	/workspace/coverage/default/2.chip_sw_example_concurrency.586836968			May 07 04:39:45 PM PDT 24	May 07 04:44:02 PM PDT 24	2843111568 ps
T915	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1796701756			May 07 04:24:58 PM PDT 24	May 07 04:32:18 PM PDT 24	7054105032 ps
T11	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2205272863			May 07 04:39:59 PM PDT 24	May 07 04:51:00 PM PDT 24	5709757765 ps
T62	/workspace/coverage/default/3.chip_tap_straps_rma.3735475884			May 07 04:47:14 PM PDT 24	May 07 04:52:02 PM PDT 24	3815593548 ps
T109	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.953536344			May 07 04:28:30 PM PDT 24	May 07 04:37:04 PM PDT 24	5088874273 ps
T916	/workspace/coverage/default/1.chip_sw_kmac_idle.1415986021			May 07 04:32:39 PM PDT 24	May 07 04:35:53 PM PDT 24	2534282000 ps
T683	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1492322169			May 07 04:45:36 PM PDT 24	May 07 05:00:24 PM PDT 24	6888494956 ps
T247	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1567672648			May 07 04:24:30 PM PDT 24	May 07 04:26:43 PM PDT 24	2839631508 ps
T745	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2162729142			May 07 04:55:34 PM PDT 24	May 07 05:04:51 PM PDT 24	5169993200 ps
T732	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308158374			May 07 04:51:51 PM PDT 24	May 07 04:58:50 PM PDT 24	3919089920 ps
T327	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2893551160			May 07 04:47:12 PM PDT 24	May 07 04:52:24 PM PDT 24	3268160174 ps
T917	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2386537761			May 07 04:26:11 PM PDT 24	May 07 04:50:33 PM PDT 24	9331076330 ps
T165	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.4180660241			May 07 04:30:04 PM PDT 24	May 07 06:05:36 PM PDT 24	50207140352 ps
T918	/workspace/coverage/default/2.chip_sw_aes_enc.3179659448			May 07 04:45:05 PM PDT 24	May 07 04:49:35 PM PDT 24	2748030330 ps
T75	/workspace/coverage/default/1.chip_jtag_mem_access.3842060224			May 07 04:27:52 PM PDT 24	May 07 04:50:03 PM PDT 24	13652629420 ps
T350	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.803429863			May 07 04:43:26 PM PDT 24	May 07 04:52:41 PM PDT 24	5634944776 ps
T267	/workspace/coverage/default/90.chip_sw_all_escalation_resets.4223801561			May 07 04:57:05 PM PDT 24	May 07 05:06:11 PM PDT 24	5795767512 ps
T919	/workspace/coverage/default/2.rom_keymgr_functest.175900857			May 07 04:46:34 PM PDT 24	May 07 04:55:17 PM PDT 24	4042444370 ps
T717	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029252956			May 07 04:30:00 PM PDT 24	May 07 04:37:00 PM PDT 24	4276243440 ps
T920	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2758372121			May 07 04:32:48 PM PDT 24	May 07 04:40:47 PM PDT 24	5400853364 ps
T202	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1893781155			May 07 04:25:28 PM PDT 24	May 07 06:00:57 PM PDT 24	48407222691 ps
T921	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3175771046			May 07 04:37:53 PM PDT 24	May 07 04:45:35 PM PDT 24	2675171286 ps
T176	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1414185109			May 07 04:34:06 PM PDT 24	May 07 04:37:00 PM PDT 24	2696485312 ps
T922	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3624982031			May 07 04:25:31 PM PDT 24	May 07 04:31:12 PM PDT 24	2630401399 ps
T302	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.878952540			May 07 04:39:46 PM PDT 24	May 07 04:49:35 PM PDT 24	4323419050 ps
T158	/workspace/coverage/default/94.chip_sw_all_escalation_resets.27866490			May 07 04:56:23 PM PDT 24	May 07 05:04:39 PM PDT 24	5353402864 ps
T923	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1583813275			May 07 04:30:27 PM PDT 24	May 07 08:00:09 PM PDT 24	78005270099 ps
T341	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536905950			May 07 04:56:12 PM PDT 24	May 07 05:03:05 PM PDT 24	3649926156 ps
T668	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3620493009			May 07 04:54:04 PM PDT 24	May 07 05:02:08 PM PDT 24	5232212120 ps
T183	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1779170681			May 07 04:25:28 PM PDT 24	May 07 04:36:27 PM PDT 24	4579426920 ps
T781	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2948511953			May 07 04:56:58 PM PDT 24	May 07 05:05:50 PM PDT 24	6024783432 ps
T924	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3809915080			May 07 04:33:09 PM PDT 24	May 07 05:07:30 PM PDT 24	8692265660 ps
T726	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.230214434			May 07 04:51:06 PM PDT 24	May 07 05:00:16 PM PDT 24	4101082748 ps
T667	/workspace/coverage/default/2.chip_sw_edn_kat.3170348268			May 07 04:43:03 PM PDT 24	May 07 04:54:28 PM PDT 24	3423009680 ps
T500	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.42259705			May 07 04:24:08 PM PDT 24	May 07 04:37:52 PM PDT 24	4515752788 ps
T293	/workspace/coverage/default/2.chip_plic_all_irqs_20.2149350729			May 07 04:45:34 PM PDT 24	May 07 04:58:04 PM PDT 24	5012077930 ps
T925	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.784234090			May 07 04:26:49 PM PDT 24	May 07 04:36:08 PM PDT 24	5064404028 ps
T926	/workspace/coverage/default/2.chip_sw_kmac_smoketest.3325846811			May 07 04:47:41 PM PDT 24	May 07 04:52:32 PM PDT 24	2599335576 ps
T927	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.539335487			May 07 04:22:56 PM PDT 24	May 07 04:32:40 PM PDT 24	4164094334 ps
T201	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.427114939			May 07 04:32:38 PM PDT 24	May 07 06:00:41 PM PDT 24	49916631816 ps
T348	/workspace/coverage/default/0.chip_sw_edn_boot_mode.469759615			May 07 04:26:43 PM PDT 24	May 07 04:36:14 PM PDT 24	2506191220 ps
T928	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2098253658			May 07 04:50:16 PM PDT 24	May 07 05:00:22 PM PDT 24	3572236545 ps
T379	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.752245089			May 07 04:24:45 PM PDT 24	May 07 04:40:36 PM PDT 24	5362251200 ps
T730	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1452769105			May 07 04:52:24 PM PDT 24	May 07 05:03:34 PM PDT 24	5823841144 ps
T48	/workspace/coverage/default/1.chip_jtag_csr_rw.3413351315			May 07 04:27:45 PM PDT 24	May 07 04:48:31 PM PDT 24	12490988916 ps
T385	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1194844504			May 07 04:47:45 PM PDT 24	May 07 04:56:10 PM PDT 24	7208766647 ps
T386	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.557381494			May 07 04:26:39 PM PDT 24	May 07 04:45:47 PM PDT 24	5891678887 ps
T387	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2865004825			May 07 04:53:55 PM PDT 24	May 07 05:00:07 PM PDT 24	3524953256 ps
T388	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2210156198			May 07 04:28:54 PM PDT 24	May 07 04:32:24 PM PDT 24	2429261500 ps
T283	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470460046			May 07 04:54:03 PM PDT 24	May 07 04:59:01 PM PDT 24	3362036008 ps
T287	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3957899171			May 07 04:54:46 PM PDT 24	May 07 05:01:58 PM PDT 24	4645327400 ps
T288	/workspace/coverage/default/2.chip_sw_example_rom.3056706594			May 07 04:41:21 PM PDT 24	May 07 04:43:25 PM PDT 24	2312163580 ps
T289	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.684035028			May 07 04:34:43 PM PDT 24	May 07 04:42:02 PM PDT 24	5525459533 ps
T290	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2222671199			May 07 04:28:49 PM PDT 24	May 07 04:49:29 PM PDT 24	4395437832 ps
T218	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2742447489			May 07 04:32:19 PM PDT 24	May 07 04:56:34 PM PDT 24	10182107060 ps
T291	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2605982849			May 07 04:44:09 PM PDT 24	May 07 04:53:48 PM PDT 24	4363868864 ps
T70	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.88413174			May 07 04:39:36 PM PDT 24	May 07 04:44:11 PM PDT 24	3915907360 ps
T52	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2380484938			May 07 04:39:07 PM PDT 24	May 07 05:08:34 PM PDT 24	21773362448 ps
T292	/workspace/coverage/default/0.chip_sw_uart_smoketest.1374471055			May 07 04:30:07 PM PDT 24	May 07 04:34:20 PM PDT 24	2976715996 ps
T97	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4127064284			May 07 04:44:49 PM PDT 24	May 07 05:02:33 PM PDT 24	20666210830 ps
T182	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3706952557			May 07 04:33:51 PM PDT 24	May 07 04:46:35 PM PDT 24	4637556118 ps