Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138957	1			T71	84		T72	13		T73	24
values[2]	9285	1			T146	2		T222	3		T223	1
values[3]	3477	1			T466	1		T505	102		T437	36
values[4]	1993	1			T505	46		T437	9		T408	3
values[5]	1268	1			T505	26		T437	10		T408	2
values[6]	853	1			T505	11		T437	14		T408	1
values[7]	709	1			T505	8		T437	4		T408	8
values[8]	472	1			T505	2		T437	1		T408	5
values[9]	434	1			T408	9		T422	1		T820	15
values[10]	365	1			T408	1		T422	1		T820	9
values[11]	343	1			T408	3		T422	1		T823	1
values[12]	281	1			T408	1		T422	1		T823	1
values[13]	250	1			T408	1		T422	1		T823	1
values[14]	230	1			T408	2		T422	1		T823	1
values[15]	285	1			T408	1		T422	1		T823	1
values[16]	266	1			T408	2		T422	1		T823	1
values[17]	287	1			T408	2		T422	1		T823	1
values[18]	255	1			T408	1		T422	1		T823	1
values[19]	248	1			T408	4		T422	1		T823	1
values[20]	253	1			T408	8		T422	1		T823	1
values[21]	248	1			T408	4		T422	1		T823	1
values[22]	274	1			T408	2		T422	1		T823	1
values[23]	261	1			T408	4		T422	1		T823	1
values[24]	254	1			T408	1		T422	1		T823	1
values[25]	276	1			T408	5		T422	1		T823	1
values[26]	264	1			T408	1		T422	1		T823	1
values[27]	269	1			T408	8		T422	1		T823	1
values[28]	275	1			T408	9		T422	1		T823	1
values[29]	262	1			T408	2		T422	1		T823	1
values[30]	249	1			T408	1		T422	1		T823	1
values[31]	237	1			T408	2		T422	1		T823	1
values[32]	244	1			T408	1		T422	1		T823	1
values[33]	251	1			T408	3		T422	1		T823	1
values[34]	238	1			T408	1		T422	1		T823	1
values[35]	260	1			T408	6		T422	1		T823	1
values[36]	235	1			T408	3		T422	1		T823	2
values[37]	235	1			T408	3		T422	1		T823	1
values[38]	235	1			T408	2		T422	1		T823	1
values[39]	225	1			T408	1		T422	1		T823	1
values[40]	199	1			T408	2		T422	1		T823	1
values[41]	220	1			T408	2		T422	1		T823	1
values[42]	222	1			T408	2		T422	1		T823	1
values[43]	264	1			T408	2		T422	1		T823	1
values[44]	264	1			T408	3		T422	1		T823	1
values[45]	237	1			T408	4		T422	1		T823	1
values[46]	208	1			T408	2		T422	1		T823	1
values[47]	268	1			T408	1		T422	1		T823	1
values[48]	270	1			T408	2		T422	1		T823	1
values[49]	243	1			T408	2		T422	1		T823	1
values[50]	219	1			T408	1		T422	1		T823	1
values[51]	214	1			T408	3		T422	1		T823	1
values[52]	243	1			T408	2		T422	1		T823	1
values[53]	201	1			T408	3		T422	1		T823	1
values[54]	197	1			T408	7		T422	1		T823	1
values[55]	203	1			T408	4		T422	1		T823	1
values[56]	214	1			T408	4		T422	1		T823	1
values[57]	212	1			T408	2		T422	1		T823	1
values[58]	191	1			T408	4		T422	1		T823	1
values[59]	181	1			T408	6		T422	1		T823	1
values[60]	176	1			T408	2		T422	1		T823	1
values[61]	185	1			T408	1		T422	1		T823	1
values[62]	169	1			T408	3		T422	1		T823	1
values[63]	132	1			T408	4		T422	1		T823	1
values[64]	195	1			T408	2		T422	1		T823	1
values[65]	145	1			T408	2		T422	1		T823	1
values[66]	138	1			T408	2		T422	1		T823	1
values[67]	150	1			T408	7		T422	1		T823	1
values[68]	141	1			T408	1		T422	1		T823	1
values[69]	175	1			T408	2		T422	1		T823	1
values[70]	120	1			T408	4		T422	1		T823	1
values[71]	119	1			T408	7		T422	1		T823	1
values[72]	99	1			T408	4		T422	1		T823	1
values[73]	85	1			T408	2		T422	1		T823	1
values[74]	89	1			T408	1		T422	1		T823	1
values[75]	94	1			T408	3		T422	1		T823	2
values[76]	95	1			T408	10		T422	1		T823	1
values[77]	114	1			T408	2		T422	1		T823	1
values[78]	102	1			T408	2		T422	1		T823	1
values[79]	121	1			T408	10		T422	1		T823	1
values[80]	109	1			T408	6		T422	1		T823	1
values[81]	80	1			T408	3		T422	1		T823	1
values[82]	78	1			T408	2		T422	1		T823	1
values[83]	82	1			T408	3		T422	1		T823	1
values[84]	63	1			T408	1		T422	1		T823	1
values[85]	70	1			T408	2		T422	1		T823	1
values[86]	60	1			T408	5		T422	1		T823	1
values[87]	55	1			T408	5		T422	1		T823	1
values[88]	71	1			T408	6		T422	1		T823	1
values[89]	80	1			T408	1		T422	1		T823	1
values[90]	68	1			T408	1		T422	1		T823	4
values[91]	76	1			T408	2		T422	1		T823	3
values[92]	84	1			T408	3		T422	1		T823	1
values[93]	86	1			T408	5		T422	1		T823	2
values[94]	74	1			T408	3		T422	1		T823	2
values[95]	86	1			T408	3		T422	1		T823	1
values[96]	81	1			T408	3		T422	1		T823	5
values[97]	76	1			T408	4		T422	1		T823	2
values[98]	73	1			T408	1		T422	1		T823	3
values[99]	70	1			T408	4		T422	1		T823	4
values[100]	91	1			T408	3		T422	1		T823	1
values[101]	75	1			T408	7		T422	1		T823	3
values[102]	72	1			T408	1		T422	1		T823	1
values[103]	79	1			T408	2		T422	1		T823	2
values[104]	92	1			T408	2		T422	1		T823	1
values[105]	81	1			T408	2		T422	1		T823	3
values[106]	93	1			T408	5		T422	1		T823	1
values[107]	115	1			T408	3		T422	10		T823	1
values[108]	105	1			T408	6		T422	1		T823	6
values[109]	84	1			T408	7		T422	3		T823	1
values[110]	91	1			T408	1		T422	1		T823	1
values[111]	79	1			T408	3		T422	6		T823	2
values[112]	81	1			T408	8		T422	2		T823	1
values[113]	87	1			T408	6		T422	1		T823	1
values[114]	85	1			T408	4		T422	2		T823	2
values[115]	90	1			T408	9		T422	1		T823	1
values[116]	73	1			T408	3		T422	3		T823	1
values[117]	85	1			T408	10		T422	6		T823	1
values[118]	83	1			T408	3		T422	2		T823	1
values[119]	83	1			T408	1		T422	1		T823	4
values[120]	70	1			T408	1		T422	4		T823	1
values[121]	67	1			T408	4		T422	7		T823	4
values[122]	67	1			T408	4		T422	1		T823	1
values[123]	69	1			T408	1		T422	3		T823	1
values[124]	71	1			T408	7		T422	1		T823	1
values[125]	98	1			T408	26		T422	2		T823	3
values[126]	165	1			T408	42		T422	3		T823	3
values[127]	963	1			T408	53		T422	43		T823	43
values[128]	7639	1			T408	26		T422	263		T823	318